BGB wrote:
On 4/20/2024 11:28 PM, John Savard wrote:
On Thu, 18 Apr 2024 22:41:01 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:
In the early 1980s someone (Amdahl?) was working on wafer scale
lithography, apparently we have now arrived.....
Actually, several companies were. The one mentioned, Trilogy, was the
one that spun off of Amdahl. There was also the company that was going
to make the solid state storage wafer for the Sinclair, the name of
which was Anamartic. Texas Instruments and ITT also researched its
possibilities.
On the other side of things, I am wondering what sorts of densities and
clock speeds are possible with printed electronics on a plastic
substrate (such as PET).
Information on the subject is fairly sparse, but inks seem to be
available (albeit expensive), albeit with some variation as to printer technology. Seems to be be either organic or inorganic inks, with
inkjet, offset, and screen printing, as the main variations in printer technology (with different inks for the different methods).
To determine wire delay per unit length, one would need the LRC values
of the conductor and insulators. Copper on Epoxy allows for transmission
speeds of ½ that of light, and I think you would be resistance limited.
So, we need:: 1) Ohms per square, 2) inductance per unit length, and
3) capacitance per unit area.
Though, I will assume that by inkjet, they don't mean just using a
repurposed consumer-grade printer (possibly with the ROM's hacked to
allow them to use refilled ink cartridges, with the non-standard inks).
Then again, with these things, they have created a situation where there
are a lot of old inkjet printers around, mostly because it is often
cheaper to buy a whole new printer than to buy the ink refill cartridges
for said printer (vs, say, laser printers where the printer is more expensive, but the toner refills are more reasonable).
Looking around, it seems some people are instead using the more "office style" inkjet printers for this (which apparently allow for refilling
the ink cartridges).
Also seems the N and P doped inks are rarer and more expensive than the conductive metallic and insulator inks.
No information on what sorts of densities are possible; crude guess is
it is roughly a ~ 133333um process, based on the assumption of a 300 dpi printer (possibly more or less).
300 DPI is 1995 technology, I would be surprised if you could not find
4800 DPI printers. This, alone, changes the lambda by 160×.
If one assumes, say, 6-dots width for a transistor, this would be ~
50x50 transistors per square inch, or possibly ~ 200k transistors per
page...
Generally, the planar technologies had 6 lambda (min) source and drains
with 4 Lambda gates and one would need 9 lambda to drop a contact on
a source or drain. So, a minimum contacted transistor would be 9+4+9
= 22 lambda wide. Generally one wanted 4 lambda between different
active regions, to the pitch of this minimum contacted transistor would
be 9+4 = 13 lambda.
I guess, if one could get it to run at MHz speeds, this could be enough
for a CPU.
Though, would likely need multiple passes through the printer to print something like this, say:
Print transistor layers;
Bake the sheet;
Print insulator and metal trace layers;
Bake;
Print more insulator and metal trace layers;
Bake;
...
Your typical 2 layer metal CMOS process in 1.5µ had 200 steps in it.
1) spin on resist
2) bake resist
3) expose resist (mask 1: P-wells and N-well contacts)
4) develop resist
5) etch resist
6) clean wafer
7) ion-implant exposed wafer
8) clean wafer
8 similar steps for N-wells
17) deposit polysilicon
18) bake polysilicon
19) spin on resist
20) bake resist
21) expose resist
22) develop resist
23) etch resist
24) clean wafer
25) spin on resist
26) bake resist
27) expose resist (P-Channel)
28) develop resist
29) etch resist
30) clean wafer
31) P-channel implants (arsenic)
32) spin on resist
33) bake resist
34) expose resist (N-Channel)
35) develop resist
36) etch resist
37) clean wafer
38) N-channel implants (phosphorous)
Then, for each contact layer one has 8 steps, and for each metal layer
one would have 10 steps. Then a thick passivation, then cutting of the
bonding pads, and finally, a back lap of the wafer to clean contaminates
and a 3 atom thick gold sputter so one can solder the Si die to the
package.
So, the problem becomes one of how does one get the pads attached to
the "other" components in the system ??
Possibly, a person could also print vias and then do multiple layers of transistors per page, possibly up to some set limit.
Not entirely sure how one would go about mapping digital logic onto
printable layers though. This may well be the hard part.
Straightforward place and route.
I will make a guess that there are probably no Verilog to semiconductive-ink-PNG compilers.
....
John Savard
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