On Sat, 10 Feb 2024 20:00:06 +0000, MitchAlsup1 wrote:
The very fact that you packed everything everybody ever did into
one ISA is novel and passes the "If it is so obvious, why did nobody
every do it before" test.
At first, I thought that you were talking about the original
Concertina ISA, which indeed tried to pack almost everything anyone
ever did before into a single ISA.
Aside from whether or not doing that is of any utility, instruction
sets have been small and large in the past, so making an instruction
set larger seems too vague to be patentable.
However, on further thought, I saw that in Concertina II, because
I tried to pack a number of different things into it, there was a
potentially patentable invention lurking.
I live in Canada; in the United States, an invention can be patented
within a year of its first disclosure, but most countries have a
stricter standard than that. And Concertina II has been around for
more than a year, and this invention has been part of it from the
start, so I think I'm out of luck.
The invention?
Here's a description worded in mild patentese...
Prior art includes a number of computer designs referred to as
of the Very Long Instruction Word (VLIW) type. Initially, this
referred to architectures such as the Control Data Cyber 203
computer, where a single instruction controlled the actions of
a large number of arithmetic units; later, it came to refer to
computers such as the TMS320C6000 chip from Texas Instruments,
where a block of RISC-like instructions also included, as part
of each instruction, a bit indicating if a given instruction
could be executed in parallel with one or more of the instructions
in the block which preceded it.
The Itanium from Intel, although not designated as VLIW, used
a technique similar to that of the TMS320C6000. In its case,
a 128-bit block consisted of five indicator bits and three
instructions, each 41 bits in length; the indicator bits, among
other things, indicated which of the instructions could execute
in parallel.
The subject of the invention is a novel class of instruction set
architectures where:
The instruction set consists of a set of instructions, all of the
same length, which are in themselves complete for allowing programs
of any type to be written, but which may also be augmented by
additional instructions of other lengths;
The instructions, although identical in each position, are noted as
being organized into blocks of a certain number (most usually a
power of two) of instructiions;
A portion of the opcode space of the instructions of the standard
length is reserved for use as block headers, which may only appear
in the first position within a block.
This model may be extended by allowing headers longer than a
single instruction, or by allowing multiple headers in the first
few positions in a block.
The primary use of the header is to optionally allow the indication
of which instructions, within a block, may be executed in parallel
with those that precede them.
Other header functions are possible, such as specifying instruction predication, also a characteristic associated with embedded processor
designs and VLIW processor designs, or extending the instruction set
while avoiding the need for mode bits that change instruction
interpretation, and which are a potential security hazard if malware
can force execution of code with them set wrongly.
It is intended that an ISA in which specifying an indication of
instruction parallelism is possible but yet optional will be of
use in permitting the use of the same instruction set across a
range of implementations:
Simple implementations, in which the indication of parallelism
is ignored, as they can only execute a single instruction at a
time;
Intermediate implementations, with pipelining and superscalar
capabilities, which make use of the indications of parallelism,
if present, to permit more efficient execution of programs;
Large implementations, which include interlocks and out-of-order
execution, which are able to determine the optimum manner to
execute the instructions in an instruction stream without the
need for an explicit indication of parallelism.
Well-formed programs, where the indication of parallelism, if
given with the program, is correct, in that instructions indicated
as being capable of being executed in parallel may indeed do so
without disturbing each other's results, would execute compatibly
on all three classes of implementation.
Programs with errors in their indication of parallelism would still
execute correctly on the first and third classes of implementation;
they would produce incorrect results on lightweight intermediate implementations, but an intermediate implementation could be given
additional interlock circuitry to enable it to be fully compatible
and execute such programs correctly as well, or, conversely,
implementations of the first and third types could be given additional circuitry to look for, and produce error indications in the case of,
errors in the indication of parallelism.
Given that a program with an indication of parallelism would be
faster on one class of implementation, and not significantly
slower on the other classes of implementation, what is the utility
of this type of ISA?
Primarily, it is presumed that in many cases, programs written for the
ISA will be targeted at only one of the three classes of implementation
given above. Having a common ISA spanning these three classes allows
programs to run on CPUs of all three types, which is a benefit, but it
is also a benefit if a program primarily intended, for example, to be
used on the large implementations only, could be written in assembly
language, or generated by a compiler, in a simpler fashion without
making use of indication of parallelism or other VLIW features.
John Savard
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