• More of my philosophy about DDR5 and the next Sapphire Rapids CPU of In

    From World-News2100@21:1/5 to All on Thu Sep 9 18:11:48 2021
    Hello...


    More of my philosophy about DDR5 and the next Sapphire Rapids CPU of Intel..

    I am a white arab from Morocco, and i think i am smart since i have also invented many scalable algorithms and algorithms..

    I will explain something very important:

    I invite you to read the following about the next Sapphire Rapids CPU of
    Intel here:

    Intel Provides Details About Sapphire Rapids CPU and Ponte Vecchio GPU

    https://www.hpcwire.com/off-the-wire/intel-unveils-details-about-sapphire-rapids-cpu-ponte-vecchio-gpu-ipu/

    So notice carefully that it says the following:

    "The processor is built to drive industry technology transitions with
    advanced memory and next generation I/O, including PCIe 5.0, CXL 1.1,
    DDR5 and HBM technologies."

    And notice that it says the same here:

    https://en.wikipedia.org/wiki/Sapphire_Rapids

    So the next Sapphire Rapids CPU of Intel will support DDR5 and HBM
    technologies for the memory subsystem, but i will say that CPUs have implemented ECC in their caches for at least a decade or so, and DDR5
    memory subsystem implementations are useful for creating large
    capacities with modest bandwidth compared to HBM, and HBM, on the other
    hand, offers large bandwidth with low capacity, but i think that the
    problem with the next Sapphire Rapids CPU of Intel is that DDR5 has a
    problem that it is not fully ECC, read here to notice it:

    "On-die ECC: The presence of on-die ECC on DDR5 memory has been the
    subject of many discussions and a lot of confusion among consumers and
    the press alike. Unlike standard ECC, on-die ECC primarily aims to
    improve yields at advanced process nodes, thereby allowing for cheaper
    DRAM chips. On-die ECC only detects errors if they take place within a
    cell or row during refreshes. When the data is moved from the cell to
    the cache or the CPU, if there’s a bit-flip or data corruption, it won’t
    be corrected by on-die ECC. Standard ECC corrects data corruption within
    the cell and as it is moved to another device or an ECC-supported SoC."

    Read more here to notice it:

    https://www.hardwaretimes.com/ddr5-vs-ddr4-ram-quad-channel-and-on-die-ecc-explained/


    Thank you,
    Amine Moulay Ramdane.

    --- SoupGate-Win32 v1.05
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  • From World-News2100@21:1/5 to All on Sun Mar 13 16:22:04 2022
    Hello...


    More of my philosophy about DDR5 and the next Sapphire Rapids CPU of
    Intel and more of my thoughts..

    I am a white arab from Morocco, and i think i am smart since i have also invented many scalable algorithms and algorithms..


    I will explain something very important:

    I invite you to read the following about the next Sapphire Rapids CPU of
    Intel here:

    Intel Provides Details About Sapphire Rapids CPU and Ponte Vecchio GPU

    https://www.hpcwire.com/off-the-wire/intel-unveils-details-about-sapphire-rapids-cpu-ponte-vecchio-gpu-ipu/

    So notice carefully that it says the following:

    "The processor is built to drive industry technology transitions with
    advanced memory and next generation I/O, including PCIe 5.0, CXL 1.1,
    DDR5 and HBM technologies."

    And notice that it says the same here:

    https://en.wikipedia.org/wiki/Sapphire_Rapids

    So the next Sapphire Rapids CPU of Intel will support DDR5 and HBM
    technologies for the memory subsystem, but i will say that CPUs like the
    kind of CPUs for computer servers have implemented ECC in their caches
    for at least a decade or so, and DDR5 memory subsystem implementations
    are useful for creating large capacities with modest bandwidth compared
    to HBM, and HBM, on the other hand, offers large bandwidth with low
    capacity, but i think that the problem with the next Sapphire Rapids CPU
    of Intel is that DDR5 has a problem that it is not fully ECC, read here
    to notice it:

    "On-die ECC: The presence of on-die ECC on DDR5 memory has been the
    subject of many discussions and a lot of confusion among consumers and
    the press alike. Unlike standard ECC, on-die ECC primarily aims to
    improve yields at advanced process nodes, thereby allowing for cheaper
    DRAM chips. On-die ECC only detects errors if they take place within a
    cell or row during refreshes. When the data is moved from the cell to
    the cache or the CPU, if there’s a bit-flip or data corruption, it won’t
    be corrected by on-die ECC. Standard ECC corrects data corruption within
    the cell and as it is moved to another device or an ECC-supported SoC."

    Read more here to notice it:

    https://www.hardwaretimes.com/ddr5-vs-ddr4-ram-quad-channel-and-on-die-ecc-explained/

    More of my philosophy about HP NonStop to x86 Server Platform
    fault-tolerant computer systems and more..

    Now HP to Extend HP NonStop to x86 Server Platform

    HP announced in 2013 plans to extend its mission-critical HP NonStop
    technology to x86 server architecture, providing the 24/7 availability
    required in an always-on, globally connected world, and increasing
    customer choice.

    Read the following to notice it:

    https://www8.hp.com/us/en/hp-news/press-release.html?id=1519347#.YHSXT-hKiM8

    And today HP provides HP NonStop to x86 Server Platform, and here is
    an example, read here:

    https://www.hpe.com/ca/en/pdfViewer.html?docId=4aa5-7443&parentPage=/ca/en/products/servers/mission-critical-servers/integrity-nonstop-systems&resourceTitle=HPE+NonStop+X+NS7+%E2%80%93+Redefining+continuous+availability+and+scalability+for+x86+data+sheet

    So i think programming the HP NonStop for x86 is now compatible with x86
    programming.

    More of my philosophy about my important thoughts about technology and
    more..

    You can read all my following thoughts that i have thought
    and written quickly , and as you notice i have just grouped them
    in this post so that you can easily read them:

    You can read my thoughts about artificial intelligence and productivity
    and about China and its artificial intelligence and computer chips in
    the following web link:

    https://groups.google.com/g/alt.culture.morocco/c/UOt_4qTgN8M

    And you can read my thoughts about the next industrial revolution and
    about Exascale supercomputers and more in the following web link:

    https://groups.google.com/g/alt.culture.morocco/c/hT6faP8cndE

    And you can read my following thoughts about 3D stacking in CPUs and
    about EUV (extreme ultra violet) and about scalability and more in the following web link:

    https://groups.google.com/g/alt.culture.morocco/c/USMMhMB9WIE

    And you can read my following thoughts about Nanotechnology and about Exponential Progress in the following web link:

    https://groups.google.com/g/alt.culture.morocco/c/mjE_2AG1TKQ


    Thank you,
    Amine Moulay Ramdane.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)