This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vm89vp$2ulja$1@dont-email.me...
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Edward Rawde wrote:
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth, Bill's original LTSpice source worked for me "as is."
Danke,
--
Don, KB7RPU, https://www.qsl.net/kb7rpu
There was a young lady named Bright Whose speed was far faster than light; She set out one day In a relative way And returned on the previous night.
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vm8u2l$pns$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vm89vp$2ulja$1@dont-email.me...
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Actually I was wrong about the simulation time.
For 10 seconds the simulation time will be between 5 and 7 days.
"Don" <g@crcomp.net> wrote in message news:20250115a@crcomp.net...
Edward Rawde wrote:
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth,
Bill's original LTSpice source worked for me "as is."
It did for me too, but because it looked like simulation time would be long I moved it to another machine I use over remote desktop.
On that machine LTSpice asked if I'd like the latest version so I upgraded to 24.1.0.
After the upgrade I got very strange netlist errors which didn't mention BAS70L and it took a while to figure out the cause.
I'm now revising the simulation time to a minimum of 4 days for 10 seconds. 24.1.0 seems to be faster.
On 16/01/2025 7:23 am, Edward Rawde wrote:
"Don" <g@crcomp.net> wrote in message news:20250115a@crcomp.net...
Edward Rawde wrote:
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth, >>> Bill's original LTSpice source worked for me "as is."
It did for me too, but because it looked like simulation time would be long I moved it to another machine I use over remote
desktop.
On that machine LTSpice asked if I'd like the latest version so I upgraded to 24.1.0.
After the upgrade I got very strange netlist errors which didn't mention BAS70L and it took a while to figure out the cause.
I'm now revising the simulation time to a minimum of 4 days for 10 seconds. >> 24.1.0 seems to be faster.
My computer seems to be faster. It mostly simulates at about 25msec/sec for me so I get my 10 seconds in about seven minutes of
real time. There are spots early in the process where it slows down, but not for long.
I pushed up R27 from 9.1R to 13R to make the Ic(Q6) and Ic(Q9) peak currents more nearly equal - you lose some base current in the
second current mirror and R7 corrects for that.
It doesn't make much difference to the third harmonic content in the output which is still only 59 dB below the fundamental. I
suppose I ought to low pass filter the current through R30 with a filter with a 1msec propagation delay, but that would be even
more components.
--
Bill Sloman, Sydney
On 16/01/2025 7:23 am, Edward Rawde wrote:
"Don" <g@crcomp.net> wrote in message news:20250115a@crcomp.net...
Edward Rawde wrote:
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth, >>> Bill's original LTSpice source worked for me "as is."
It did for me too, but because it looked like simulation time would be long I moved it to another machine I use over remote
desktop.
On that machine LTSpice asked if I'd like the latest version so I upgraded to 24.1.0.
After the upgrade I got very strange netlist errors which didn't mention BAS70L and it took a while to figure out the cause.
I'm now revising the simulation time to a minimum of 4 days for 10 seconds. >> 24.1.0 seems to be faster.
My computer seems to be faster. It mostly simulates at about 25msec/sec for me so I get my 10 seconds in about seven minutes of
real time. There are spots early in the process where it slows down, but not for long.
I pushed up R27 from 9.1R to 13R to make the Ic(Q6) and Ic(Q9) peak currents more nearly equal - you lose some base current in the
second current mirror and R7 corrects for that.
It doesn't make much difference to the third harmonic content in the output which is still only 59 dB below the fundamental. I
suppose I ought to low pass filter the current through R30 with a filter with a 1msec propagation delay, but that would be even
more components.
--
Bill Sloman, Sydney
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vm9tod$37i55$1@dont-email.me...
On 16/01/2025 7:23 am, Edward Rawde wrote:
"Don" <g@crcomp.net> wrote in message news:20250115a@crcomp.net...
Edward Rawde wrote:
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth, >>>> Bill's original LTSpice source worked for me "as is."
It did for me too, but because it looked like simulation time would be long I moved it to another machine I use over remote
desktop.
On that machine LTSpice asked if I'd like the latest version so I upgraded to 24.1.0.
After the upgrade I got very strange netlist errors which didn't mention BAS70L and it took a while to figure out the cause.
I'm now revising the simulation time to a minimum of 4 days for 10 seconds. >>> 24.1.0 seems to be faster.
My computer seems to be faster. It mostly simulates at about 25msec/sec for me so I get my 10 seconds in about seven minutes of
real time. There are spots early in the process where it slows down, but not for long.
The Lenovo core i7 3.6GHz with SSD I'm running it on hasn't gone above 30us/s.
If your computer is 1000 times faster I'd like to have one, otherwise there's another explanation somewhere.
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vm9tod$37i55$1@dont-email.me...
On 16/01/2025 7:23 am, Edward Rawde wrote:
"Don" <g@crcomp.net> wrote in message news:20250115a@crcomp.net...
Edward Rawde wrote:
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth, >>>> Bill's original LTSpice source worked for me "as is."
It did for me too, but because it looked like simulation time would be long I moved it to another machine I use over remote
desktop.
On that machine LTSpice asked if I'd like the latest version so I upgraded to 24.1.0.
After the upgrade I got very strange netlist errors which didn't mention BAS70L and it took a while to figure out the cause.
I'm now revising the simulation time to a minimum of 4 days for 10 seconds. >>> 24.1.0 seems to be faster.
My computer seems to be faster. It mostly simulates at about 25msec/sec for me so I get my 10 seconds in about seven minutes of
real time. There are spots early in the process where it slows down, but not for long.
I pushed up R27 from 9.1R to 13R to make the Ic(Q6) and Ic(Q9) peak currents more nearly equal - you lose some base current in the
second current mirror and R7 corrects for that.
It doesn't make much difference to the third harmonic content in the output which is still only 59 dB below the fundamental. I
suppose I ought to low pass filter the current through R30 with a filter with a 1msec propagation delay, but that would be even
more components.
With an FFT from 525-536ms with Blackman-Harris window I'm seeing nearly 100dB down at 1kHz and 80dB at 2kHz.
But there's also crud only 60dB down at 600kHz where crud means an almost contiuous spectrum between 500kHz and 600kHz.
On 16/01/2025 2:41 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vm9tod$37i55$1@dont-email.me...
On 16/01/2025 7:23 am, Edward Rawde wrote:
"Don" <g@crcomp.net> wrote in message news:20250115a@crcomp.net...
Edward Rawde wrote:
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control
the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth, >>>>> Bill's original LTSpice source worked for me "as is."
It did for me too, but because it looked like simulation time would be long I moved it to another machine I use over remote
desktop.
On that machine LTSpice asked if I'd like the latest version so I upgraded to 24.1.0.
After the upgrade I got very strange netlist errors which didn't mention BAS70L and it took a while to figure out the cause.
I'm now revising the simulation time to a minimum of 4 days for 10 seconds.
24.1.0 seems to be faster.
My computer seems to be faster. It mostly simulates at about 25msec/sec for me so I get my 10 seconds in about seven minutes of
real time. There are spots early in the process where it slows down, but not for long.
The Lenovo core i7 3.6GHz with SSD I'm running it on hasn't gone above 30us/s.
If your computer is 1000 times faster I'd like to have one, otherwise there's another explanation somewhere.
My computer uses an i5-3470 CPU running at 3.20GHz. It's more than ten years old. LTSpice uses my SSD card which isn't original,
so your hardware ought to be even faster.
<snip>
--
Bill Sloman, Sydney
On 16/01/2025 2:57 pm, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vm9tod$37i55$1@dont-email.me...
On 16/01/2025 7:23 am, Edward Rawde wrote:
"Don" <g@crcomp.net> wrote in message news:20250115a@crcomp.net...
Edward Rawde wrote:
Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control
the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
First I corrected the usual line wrap issues.
In the latest LTSpice (24.1.0) it took me a good hour or two to find out why I was getting strange netlist errors for all the
opamps
in the circuit.
This turned out to be .ENDS in the BAS70L model. Remove .ENDS and the issues go away.
So this is the circuit I'm simulating in 24.1.0 with no component updates available.
I'm expecting it to take 2 hours to complete.
Thank you for your tip to wait 2 hours for results. For what it's worth, >>>>> Bill's original LTSpice source worked for me "as is."
It did for me too, but because it looked like simulation time would be long I moved it to another machine I use over remote
desktop.
On that machine LTSpice asked if I'd like the latest version so I upgraded to 24.1.0.
After the upgrade I got very strange netlist errors which didn't mention BAS70L and it took a while to figure out the cause.
I'm now revising the simulation time to a minimum of 4 days for 10 seconds.
24.1.0 seems to be faster.
My computer seems to be faster. It mostly simulates at about 25msec/sec for me so I get my 10 seconds in about seven minutes of
real time. There are spots early in the process where it slows down, but not for long.
I pushed up R27 from 9.1R to 13R to make the Ic(Q6) and Ic(Q9) peak currents more nearly equal - you lose some base current in
the
second current mirror and R7 corrects for that.
It doesn't make much difference to the third harmonic content in the output which is still only 59 dB below the fundamental. I
suppose I ought to low pass filter the current through R30 with a filter with a 1msec propagation delay, but that would be even
more components.
With an FFT from 525-536ms with Blackman-Harris window I'm seeing nearly 100dB down at 1kHz and 80dB at 2kHz.
But there's also crud only 60dB down at 600kHz where crud means an almost contiuous spectrum between 500kHz and 600kHz.
This sounds like a typo.
The fundamental is at 1kHz, and I've set up the circuit so that it is just above 0dB. The second harmonic at 2kHz is about
at -80dB, but the third harmonic at 3kHz is at about -60dB. Numerical integration does produce high frequency crud - also known as
rounding error and quantisation error. We'd have to build a real circuit to get a credible idea of how it performed at high
frequencies, and you have to build it fairly carefully to avoid lots of crud on the supply rails, which gets everywhere.
My full-wave rectifier does do some fast switching, which could make it a noise source.
--
Bill Sloman, Sydney
This just reworks my circuit to use a controllable asymmetric current
mirror instead of the FET for gain control. I take the feedback from the
full wave rectifier and switch every half-cycle to reconstruct a
variable amplitude sine wave to control the output amplitude. It does
use a lot of components, but it strikes me as fairly comprehensible.
R30 isn't a real part - it's just there to let me do an FFT on the
correction signal.
The circuit just copes with worst case capacitors - 15.15nF and 14.85nF
- at C5 and C6, as it was intended to do. Using a trim pot to take out component tolerances would let you get away with a smaller correction
signal injecting smaller doses of the odd harmonics.
The circuit does cry out for monolithic dual transisors.The On-Semi NST45010MW6T1G pnp and the
NST45011MW6T1G npn parts are cheap and widely available.
On 15/01/2025 11:33 pm, Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
R30 isn't a real part - it's just there to let me do an FFT on the correction signal.
The circuit just copes with worst case capacitors - 15.15nF and 14.85nF - at C5 and C6, as it was intended to do. Using a trim
pot to take out component tolerances would let you get away with a smaller correction signal injecting smaller doses of the odd
harmonics.
The circuit does cry out for monolithic dual transisors.The On-Semi
NST45010MW6T1G pnp and the
NST45011MW6T1G npn parts are cheap and widely available.
There was a dumb error in the original circuit. The two transistor switch (Q5 and Q6 in the original circuit) that turned the full
wave rectified waveform back into a sine wave was set up with very little headroom. It didn't stop the circuit from working as
intended after it had settled down, but it made start-up a bit tricky.
Here's the corrected version. It's performance isn't noticeably differ
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmlpii$364is$7@dont-email.me...
On 15/01/2025 11:33 pm, Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
R30 isn't a real part - it's just there to let me do an FFT on the correction signal.
The circuit just copes with worst case capacitors - 15.15nF and 14.85nF - at C5 and C6, as it was intended to do. Using a trim
pot to take out component tolerances would let you get away with a smaller correction signal injecting smaller doses of the odd
harmonics.
The circuit does cry out for monolithic dual transisors.The On-Semi
NST45010MW6T1G pnp and the
NST45011MW6T1G npn parts are cheap and widely available.
There was a dumb error in the original circuit. The two transistor switch (Q5 and Q6 in the original circuit) that turned the
full wave rectified waveform back into a sine wave was set up with very little headroom. It didn't stop the circuit from working
as intended after it had settled down, but it made start-up a bit tricky.
Here's the corrected version. It's performance isn't noticeably differ
On 15/01/2025 11:33 pm, Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current
mirror instead of the FET for gain control. I take the feedback from
the full wave rectifier and switch every half-cycle to reconstruct a
variable amplitude sine wave to control the output amplitude. It does
use a lot of components, but it strikes me as fairly comprehensible.
R30 isn't a real part - it's just there to let me do an FFT on the
correction signal.
The circuit just copes with worst case capacitors - 15.15nF and
14.85nF - at C5 and C6, as it was intended to do. Using a trim pot to
take out component tolerances would let you get away with a smaller
correction signal injecting smaller doses of the odd harmonics.
The circuit does cry out for monolithic dual transisors.The On-Semi
NST45010MW6T1G pnp and the
NST45011MW6T1G npn parts are cheap and widely available.
There was a dumb error in the original circuit. The two transistor
switch (Q5 and Q6 in the original circuit) that turned the full wave rectified waveform back into a sine wave was set up with very little headroom. It didn't stop the circuit from working as intended after it
had settled down, but it made start-up a bit tricky.
Here's the corrected version. It's performance isn't noticeably different
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
This just reworks my circuit to use a controllable asymmetric current mirror instead of the FET for gain control. I take the
feedback from the full wave rectifier and switch every half-cycle to reconstruct a variable amplitude sine wave to control the
output amplitude. It does use a lot of components, but it strikes me as fairly comprehensible.
R30 isn't a real part - it's just there to let me do an FFT on the correction signal.
The circuit just copes with worst case capacitors - 15.15nF and 14.85nF - at C5 and C6, as it was intended to do. Using a trim
pot to take out component tolerances would let you get away with a smaller correction signal injecting smaller doses of the odd
harmonics.
The circuit does cry out for monolithic dual transisors.The On-Semi
NST45010MW6T1G pnp and the
NST45011MW6T1G npn parts are cheap and widely available.
There was a dumb error in the original circuit. The two transistor switch (Q5 and Q6 in the original circuit) that turned the
full wave rectified waveform back into a sine wave was set up with very little headroom. It didn't stop the circuit from working
as intended after it had settled down, but it made start-up a bit tricky.
Here's the corrected version. It's performance isn't noticeably different
I've taken Edward Rawles commnents to heart,but I suspect he has inadvertently corrected the circuit into something that simulates
a lot slower that the circuit I'm looking at, which runs at about 30msec/sec.
I've corrected the right transistor to Q6. I've played with the text file in an attempt deal with the line feeds.
U1 is an LT1360 and Linear Technology's LTSpice should know all about that. The relevant lines in the file are
"SYMBOL Opamps\\LT1360 208 -1248 R0
SYMATTR InstName U1"
The BAS70L model file below is
TEXT -2232 -1200 Left 2 !.MODEL BAS70L D
\n+ IS = 3.22E-9
\n+ N = 1.018
\n+ BV = 77 \n+ IBV = 1.67E-7
\n+ RS = 20.89
\n+ CJO = 1.608E-12
\n+ VJ = 0.3891
\n+ M = 0.3683
\n+ FC = 0.5
\n+ EG = 0.69
\n+ XTI = 2
\n.ENDS
The \n+ character string does seem to be the way WordPad deals with line wraps in the .asc file.
Deleting .ENDS from the end of the model string may be one way of keepig LTSpice happy, but it probably isn't the right one.
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
On Tue, 21 Jan 2025 11:58:15 -0500, "Edward Rawde"...
<invalid@invalid.invalid> wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
That circuit is of the category known as "component rich."
"john larkin" <jl@glen--canyon.com> wrote in message news:uitvojh0a603a326e46go11qqcc1o1sv3p@4ax.com...
On Tue, 21 Jan 2025 11:58:15 -0500, "Edward Rawde"...
<invalid@invalid.invalid> wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
That circuit is of the category known as "component rich."
What simulation speed do you get?
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
Copy text from Version 4 to end of file directly from previous post.
Paste into new asc file using Notepad++
Note three line wraps near end of file with lines starting with 1.608E-12, MAX5492 and KF=1e-18
Position cursor at beginning of wrapped part and use backspace key to unwrap it.
Save file with no other changes. Schematic opens in LTSpice with no issues. >Start simulation and click on Vout. Note simulation speed of about 20us/s >Copy file to other computer running LTSpice 24.1.0
Schematic opens without issues.
Attempt to start simulation.
Log file opens with errors claiming issues with U1 - U10. BAS70L is not mentioned.
Close LTSpice.
Edit asc file with Notepad++ to remove only .ENDS (note that includes the dot) from BAS70L line. Save file.
Start simulation. Simulation runs at about 25us/s with no errors.
Stop simulation.
Note that log file opens claiming Simulation Failed when really it was just stopped. 24.0.12 doesn't do that.
Examine schematic more closely.
Find tiny extraneous piece of wire between R12/R28 and R10/C11. Remove it. >Cannot find any other schematic issues. U1 and everything else looks as intended to me.
Simulation still 25us/s
Post schematic file below as it is now on 24.1.0
Version 4.1
SHEET 1 3608 920
WIRE -1680 -2400 -1984 -2400
WIRE -1360 -2400 -1680 -2400
WIRE -1200 -2400 -1360 -2400
WIRE -1104 -2400 -1200 -2400
WIRE -736 -2400 -1104 -2400
WIRE -320 -2400 -736 -2400
WIRE 208 -2400 -320 -2400
WIRE 336 -2400 208 -2400
WIRE 576 -2400 336 -2400
WIRE -736 -2384 -736 -2400
WIRE 208 -2384 208 -2400
WIRE -320 -2368 -320 -2400
WIRE 3376 -2272 -1616 -2272
WIRE 880 -2192 -1776 -2192
WIRE -1360 -2160 -1360 -2400
WIRE -736 -2160 -736 -2320
WIRE -656 -2160 -736 -2160
WIRE -320 -2160 -320 -2304
WIRE -176 -2160 -320 -2160
WIRE 208 -2144 208 -2320
WIRE 336 -2144 208 -2144
WIRE -1200 -2112 -1200 -2400
WIRE -1680 -2096 -1680 -2400
WIRE -1360 -2048 -1360 -2080
WIRE -320 -2000 -320 -2160
WIRE -736 -1984 -736 -2160
WIRE -1776 -1968 -1776 -2192
WIRE 336 -1968 336 -2144
WIRE 576 -1968 576 -2400
WIRE -1360 -1920 -1360 -1968
WIRE -1200 -1920 -1200 -2032
WIRE 1952 -1920 1744 -1920
WIRE 2160 -1920 1952 -1920
WIRE -1616 -1904 -1616 -2272
WIRE 1376 -1904 1072 -1904
WIRE 1536 -1904 1376 -1904
WIRE 336 -1888 336 -1904
WIRE -1280 -1872 -1296 -1872
WIRE -1264 -1872 -1280 -1872
WIRE -576 -1872 -912 -1872
WIRE -32 -1872 -496 -1872
WIRE 1744 -1872 1744 -1920
WIRE 1072 -1856 1072 -1904
WIRE 1952 -1824 1904 -1824
WIRE 2160 -1824 2160 -1920
WIRE 2160 -1824 2032 -1824
WIRE -128 -1808 -272 -1808
WIRE -32 -1808 -32 -1872
WIRE -32 -1808 -64 -1808
WIRE -1776 -1792 -1776 -1888
WIRE -1776 -1792 -2064 -1792
WIRE -1280 -1792 -1280 -1872
WIRE -1200 -1792 -1200 -1824
WIRE -1200 -1792 -1280 -1792
WIRE -912 -1792 -912 -1872
WIRE -864 -1792 -912 -1792
WIRE -544 -1792 -784 -1792
WIRE -1200 -1776 -1200 -1792
WIRE 576 -1776 576 -1904
WIRE 768 -1776 576 -1776
WIRE 2160 -1776 2160 -1824
WIRE 2288 -1776 2160 -1776
WIRE 2432 -1776 2368 -1776
WIRE 2496 -1776 2432 -1776
WIRE 2800 -1776 2576 -1776
WIRE 2864 -1776 2800 -1776
WIRE 3088 -1776 2944 -1776
WIRE 1280 -1760 1232 -1760
WIRE 1536 -1760 1536 -1904
WIRE 1536 -1760 1360 -1760
WIRE -1776 -1728 -1776 -1792
WIRE -1360 -1728 -1360 -1824
WIRE -1360 -1728 -1520 -1728
WIRE -1264 -1728 -1360 -1728
WIRE -544 -1728 -544 -1792
WIRE 3088 -1728 3088 -1776
WIRE -1984 -1712 -1984 -2400
WIRE -272 -1712 -272 -1808
WIRE -128 -1712 -272 -1712
WIRE -32 -1712 -32 -1808
WIRE -32 -1712 -64 -1712
WIRE 2432 -1712 2432 -1776
WIRE -2064 -1696 -2064 -1792
WIRE -2016 -1696 -2064 -1696
WIRE -1840 -1680 -1952 -1680
WIRE -2016 -1664 -2064 -1664
WIRE 1648 -1648 1392 -1648
WIRE 2064 -1648 1648 -1648
WIRE -912 -1632 -912 -1792
WIRE -848 -1632 -912 -1632
WIRE -544 -1632 -544 -1648
WIRE -544 -1632 -784 -1632
WIRE -1200 -1616 -1200 -1680
WIRE -1200 -1616 -1360 -1616
WIRE -1072 -1616 -1200 -1616
WIRE -912 -1616 -912 -1632
WIRE -912 -1616 -992 -1616
WIRE -272 -1616 -272 -1712
WIRE -144 -1616 -272 -1616
WIRE -32 -1616 -32 -1712
WIRE -32 -1616 -64 -1616
WIRE 2064 -1616 2064 -1648
WIRE 1392 -1600 1392 -1648
WIRE 1904 -1600 1904 -1824
WIRE 2032 -1600 1904 -1600
WIRE -2064 -1584 -2064 -1664
WIRE -544 -1584 -544 -1632
WIRE -512 -1584 -544 -1584
WIRE -432 -1584 -448 -1584
WIRE -272 -1584 -272 -1616
WIRE -272 -1584 -352 -1584
WIRE 1232 -1584 1232 -1760
WIRE 1360 -1584 1232 -1584
WIRE 2160 -1584 2160 -1776
WIRE 2160 -1584 2096 -1584
WIRE 2432 -1584 2432 -1632
WIRE 1536 -1568 1536 -1760
WIRE 1536 -1568 1424 -1568
WIRE 1584 -1568 1536 -1568
WIRE 1744 -1568 1744 -1808
WIRE 1744 -1568 1664 -1568
WIRE 1792 -1568 1744 -1568
WIRE 2000 -1568 1872 -1568
WIRE 2032 -1568 2000 -1568
WIRE -176 -1552 -176 -2160
WIRE 880 -1552 880 -2192
WIRE 912 -1552 880 -1552
WIRE 1072 -1552 1072 -1792
WIRE 1072 -1552 992 -1552
WIRE 1120 -1552 1072 -1552
WIRE 1328 -1552 1200 -1552
WIRE 1360 -1552 1328 -1552
WIRE -272 -1536 -272 -1584
WIRE -208 -1536 -272 -1536
WIRE 2800 -1536 2800 -1776
WIRE 2848 -1536 2800 -1536
WIRE 3088 -1536 3088 -1664
WIRE 3088 -1536 2912 -1536
WIRE -32 -1520 -32 -1616
WIRE -32 -1520 -144 -1520
WIRE 16 -1520 -32 -1520
WIRE 64 -1520 16 -1520
WIRE 112 -1520 64 -1520
WIRE 432 -1520 192 -1520
WIRE -208 -1504 -288 -1504
WIRE -288 -1456 -288 -1504
WIRE 256 -1456 144 -1456
WIRE 368 -1456 336 -1456
WIRE 496 -1456 368 -1456
WIRE 1392 -1456 1392 -1536
WIRE 1632 -1456 1392 -1456
WIRE 2064 -1456 2064 -1552
WIRE 2064 -1456 1632 -1456
WIRE 2432 -1456 2288 -1456
WIRE 2992 -1456 2432 -1456
WIRE 3264 -1456 2992 -1456
WIRE -656 -1440 -656 -2160
WIRE 1232 -1440 1232 -1584
WIRE 2288 -1440 2288 -1456
WIRE -1520 -1424 -1520 -1728
WIRE -1360 -1424 -1360 -1616
WIRE -912 -1424 -912 -1616
WIRE -688 -1424 -912 -1424
WIRE 2992 -1424 2992 -1456
WIRE -544 -1408 -544 -1584
WIRE -544 -1408 -624 -1408
WIRE 768 -1408 768 -1776
WIRE 2800 -1408 2800 -1536
WIRE 2960 -1408 2800 -1408
WIRE -688 -1392 -704 -1392
WIRE 496 -1392 496 -1456
WIRE 1328 -1392 1328 -1552
WIRE 1904 -1392 1904 -1600
WIRE 3088 -1392 3088 -1536
WIRE 3088 -1392 3024 -1392
WIRE 3152 -1392 3088 -1392
WIRE -1680 -1376 -1680 -2016
WIRE -1584 -1376 -1680 -1376
WIRE -992 -1376 -1296 -1376
WIRE 2960 -1376 2800 -1376
WIRE 144 -1360 144 -1456
WIRE 256 -1360 144 -1360
WIRE 368 -1360 368 -1456
WIRE 368 -1360 320 -1360
WIRE -992 -1344 -992 -1376
WIRE -432 -1344 -992 -1344
WIRE 64 -1344 64 -1520
WIRE 64 -1344 -352 -1344
WIRE 2000 -1344 2000 -1568
WIRE -1680 -1328 -1680 -1376
WIRE 64 -1328 64 -1344
WIRE 368 -1312 368 -1360
WIRE 3152 -1312 3152 -1392
WIRE -1520 -1296 -1520 -1328
WIRE -1440 -1296 -1520 -1296
WIRE -1360 -1296 -1360 -1328
WIRE -1360 -1296 -1440 -1296
WIRE -992 -1280 -992 -1344
WIRE 2288 -1264 2288 -1376
WIRE 2384 -1264 2288 -1264
WIRE 576 -1232 576 -1776
WIRE -736 -1216 -736 -1920
WIRE -736 -1216 -848 -1216
WIRE -704 -1216 -704 -1392
WIRE -704 -1216 -736 -1216
WIRE -560 -1216 -704 -1216
WIRE -320 -1216 -320 -1936
WIRE -320 -1216 -560 -1216
WIRE 208 -1216 208 -2144
WIRE 432 -1216 432 -1520
WIRE 496 -1216 496 -1312
WIRE 496 -1216 432 -1216
WIRE 544 -1216 496 -1216
WIRE -1440 -1200 -1440 -1296
WIRE 64 -1200 64 -1248
WIRE 144 -1200 144 -1360
WIRE 144 -1200 64 -1200
WIRE 176 -1200 144 -1200
WIRE 880 -1200 880 -1552
WIRE 880 -1200 608 -1200
WIRE 368 -1184 368 -1248
WIRE 368 -1184 240 -1184
WIRE 544 -1184 464 -1184
WIRE 2288 -1184 2288 -1264
WIRE -320 -1168 -320 -1216
WIRE -48 -1168 -144 -1168
WIRE 176 -1168 -48 -1168
WIRE 1232 -1168 1232 -1360
WIRE 1328 -1168 1328 -1328
WIRE 1328 -1168 1232 -1168
WIRE 1520 -1168 1328 -1168
WIRE 1904 -1168 1904 -1312
WIRE 1904 -1168 1520 -1168
WIRE 2000 -1168 2000 -1280
WIRE 2000 -1168 1904 -1168
WIRE -1776 -1152 -1776 -1632
WIRE -1504 -1152 -1776 -1152
WIRE -848 -1152 -848 -1216
WIRE -560 -1152 -560 -1216
WIRE 464 -1152 464 -1184
WIRE 1520 -1152 1520 -1168
WIRE 2384 -1152 2384 -1264
WIRE 2416 -1152 2384 -1152
WIRE 2752 -1152 2704 -1152
WIRE 2800 -1152 2800 -1376
WIRE 2800 -1152 2752 -1152
WIRE -144 -1136 -144 -1168
WIRE -48 -1136 -48 -1168
WIRE 2800 -1120 2800 -1152
WIRE -1104 -1104 -1104 -2400
WIRE 368 -1088 368 -1184
WIRE 2384 -1088 2384 -1152
WIRE 2416 -1088 2384 -1088
WIRE 2752 -1088 2752 -1152
WIRE 2752 -1088 2704 -1088
WIRE -1440 -1072 -1440 -1104
WIRE -1440 -1072 -1568 -1072
WIRE 432 -1072 432 -1216
WIRE 640 -1072 432 -1072
WIRE 880 -1072 880 -1200
WIRE 880 -1072 704 -1072
WIRE 3264 -1056 3264 -1456
WIRE -144 -1040 -144 -1072
WIRE -80 -1040 -144 -1040
WIRE -48 -1040 -48 -1056
WIRE -48 -1040 -80 -1040
WIRE 3152 -1040 3152 -1232
WIRE 3232 -1040 3152 -1040
WIRE -48 -1024 -48 -1040
WIRE 3376 -1024 3376 -2272
WIRE 3376 -1024 3296 -1024
WIRE -1776 -1008 -1776 -1152
WIRE -1440 -1008 -1440 -1072
WIRE -1104 -1008 -1104 -1024
WIRE -1104 -1008 -1264 -1008
WIRE -848 -1008 -848 -1088
WIRE -656 -1008 -656 -1376
WIRE -656 -1008 -848 -1008
WIRE -320 -1008 -320 -1104
WIRE -176 -1008 -176 -1488
WIRE -176 -1008 -320 -1008
WIRE 768 -1008 768 -1344
WIRE 2288 -1008 2288 -1120
WIRE 2288 -1008 768 -1008
WIRE 2560 -1008 2560 -1056
WIRE 2560 -1008 2288 -1008
WIRE 2576 -1008 2560 -1008
WIRE 2800 -1008 2800 -1056
WIRE 2800 -1008 2576 -1008
WIRE 3232 -1008 2800 -1008
WIRE -1264 -992 -1264 -1008
WIRE -1568 -960 -1568 -1072
WIRE -1568 -960 -1712 -960
WIRE -1504 -960 -1568 -960
WIRE -1104 -960 -1104 -1008
WIRE -176 -960 -176 -1008
WIRE 2576 -960 2576 -1008
WIRE 64 -944 64 -1200
WIRE 96 -944 64 -944
WIRE 368 -944 368 -1024
WIRE 368 -944 160 -944
WIRE -656 -928 -656 -1008
WIRE 3152 -928 3152 -1040
WIRE 432 -912 432 -1072
WIRE 464 -912 432 -912
WIRE 624 -912 544 -912
WIRE 880 -912 880 -1072
WIRE 880 -912 704 -912
WIRE 64 -880 64 -944
WIRE -1776 -848 -1776 -912
WIRE -1616 -848 -1616 -1824
WIRE -1616 -848 -1776 -848
WIRE -1776 -832 -1776 -848
WIRE -80 -816 -80 -1040
WIRE 768 -800 768 -1008
WIRE 3152 -800 3152 -848
WIRE 3376 -800 3376 -1024
WIRE 3376 -800 3152 -800
WIRE 64 -784 64 -800
WIRE 368 -784 368 -944
WIRE 368 -784 64 -784
WIRE 576 -720 576 -1168
WIRE 768 -720 768 -736
WIRE 768 -720 576 -720
WIRE -1984 -704 -1984 -1648
WIRE -1776 -704 -1776 -752
WIRE -1776 -704 -1984 -704
WIRE -1680 -704 -1680 -1248
WIRE -1680 -704 -1776 -704
WIRE -1440 -704 -1440 -912
WIRE -1440 -704 -1680 -704
WIRE -1104 -704 -1104 -880
WIRE -1104 -704 -1440 -704
WIRE -1040 -704 -1104 -704
WIRE -992 -704 -992 -1200
WIRE -992 -704 -1040 -704
WIRE -656 -704 -656 -864
WIRE -656 -704 -992 -704
WIRE -176 -704 -176 -896
WIRE -176 -704 -656 -704
WIRE -80 -704 -80 -752
WIRE 208 -704 208 -1152
WIRE 208 -704 -80 -704
WIRE 576 -704 576 -720
WIRE 208 -624 208 -640
WIRE 416 -624 208 -624
WIRE 576 -624 576 -640
WIRE 576 -624 416 -624
WIRE 2992 -624 2992 -1360
WIRE 2992 -624 576 -624
WIRE 3264 -624 3264 -992
WIRE 3264 -624 2992 -624
FLAG 464 -1152 0
FLAG -48 -1024 0
FLAG -1264 -992 0
FLAG 336 -2400 Vcc
FLAG 416 -624 Vee
FLAG -560 -1152 0
FLAG 16 -1520 Vout
FLAG 2576 -960 0
FLAG 2432 -1456 Vcc
FLAG -1040 -704 Vee
FLAG -288 -1456 0
FLAG 336 -1888 0
FLAG 1376 -1904 filt1
FLAG 1648 -1648 Vcc
FLAG 1632 -1456 Vee
FLAG 1520 -1152 0
FLAG 1952 -1920 filter2
FLAG 2432 -1584 0
FLAG -2064 -1584 0
SYMBOL Opamps\\LT1360 208 -1184 R0
SYMATTR InstName U1
SYMBOL res 48 -1344 R0
WINDOW 0 41 37 Left 2
WINDOW 3 36 71 Left 2
SYMATTR InstName R1
SYMATTR Value 10k
SYMATTR SpiceLine tol=0.1
SYMBOL res -64 -1152 R0
WINDOW 3 41 74 Left 2
WINDOW 0 43 31 Left 2
SYMATTR Value 4k02
SYMATTR InstName R2
SYMATTR SpiceLine tol=1
SYMBOL cap -160 -1136 R0
SYMATTR InstName C1
SYMATTR Value 3.3n
SYMBOL schottky 352 -1312 R0
WINDOW 3 -89 62 Left 2
WINDOW 0 -92 37 Left 2
SYMATTR Value BAS70L
SYMATTR InstName D1
SYMBOL schottky 352 -1088 R0
WINDOW 3 -78 61 Left 2
WINDOW 0 -81 40 Left 2
SYMATTR Value BAS70L
SYMATTR InstName D2
SYMBOL res 352 -1472 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1a
SYMATTR Value 10k
SYMATTR SpiceLine tol=0.1
SYMBOL res 208 -1536 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 20k
SYMATTR SpiceLine tol=1
SYMBOL res 480 -1408 R0
WINDOW 0 41 41 Left 2
WINDOW 3 34 79 Left 2
SYMATTR InstName R2a
SYMATTR Value 10k
SYMATTR SpiceLine tol=0.1
SYMBOL res 560 -928 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2b
SYMATTR Value 10k
SYMATTR SpiceLine tol=0.1
SYMBOL res 720 -928 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2c
SYMATTR Value 10k
SYMATTR SpiceLine tol=0.1
SYMBOL cap 160 -960 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C4
SYMATTR Value 3.3p
SYMBOL res 48 -896 R0
WINDOW 0 39 33 Left 2
WINDOW 3 40 74 Left 2
SYMATTR InstName R1b
SYMATTR Value 10k
SYMATTR SpiceLine tol=0.1
SYMBOL voltage -1104 -1120 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 12
SYMBOL voltage -1104 -976 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value 12
SYMBOL cap -448 -1600 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C5
SYMATTR Value 15n
SYMATTR SpiceLine V=63 Rser=4 Lser=12n
SYMBOL res -448 -1568 R270
WINDOW 0 27 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 10.7k
SYMATTR SpiceLine tol=1
SYMBOL cap -64 -1728 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C6
SYMATTR Value 15n
SYMATTR SpiceLine V=63 Rser=4 Lser=12n
SYMBOL cap 3104 -1664 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 8 Left 2
SYMATTR InstName C8
SYMATTR Value 22n
SYMBOL res 2848 -1760 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R10
SYMATTR Value 220k
SYMBOL Opamps\\LT1056A 2992 -1456 R0
SYMATTR InstName U5
SYMBOL cap 2784 -1120 R0
SYMATTR InstName C10
SYMATTR Value 3.3µ
SYMBOL cap 2912 -1552 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C11
SYMATTR Value 3.3p
SYMBOL Opamps\\OP27 576 -1264 R0
SYMATTR InstName U2
SYMBOL FerriteBead 576 -672 R0
SYMATTR InstName L2
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL cap 752 -1408 R0
SYMATTR InstName C15
SYMATTR Value 100n
SYMBOL cap 752 -800 R0
SYMATTR InstName C16
SYMATTR Value 100n
SYMBOL FerriteBead -176 -928 R0
SYMATTR InstName L4
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL cap -336 -2000 R0
WINDOW 0 -60 15 Left 2
WINDOW 3 -62 54 Left 2
SYMATTR InstName C17
SYMATTR Value 100n
SYMBOL cap -336 -1168 R0
WINDOW 0 -60 15 Left 2
WINDOW 3 -62 54 Left 2
SYMATTR InstName C18
SYMATTR Value 100n
SYMBOL cap 2272 -1184 R0
SYMATTR InstName C21
SYMATTR Value 100n
SYMBOL FerriteBead 2288 -1408 R0
SYMATTR InstName L7
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL res -480 -1888 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R22
SYMATTR Value 2.49k
SYMATTR SpiceLine tol=1
SYMBOL FerriteBead -320 -2336 R0
SYMATTR InstName L8
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL cap -752 -1984 R0
WINDOW 0 -60 15 Left 2
WINDOW 3 -62 54 Left 2
SYMATTR InstName C7
SYMATTR Value 100n
SYMBOL FerriteBead -736 -2352 R0
SYMATTR InstName L3
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL FerriteBead -656 -896 R0
SYMATTR InstName L9
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL cap -864 -1152 R0
WINDOW 0 -60 15 Left 2
WINDOW 3 -62 54 Left 2
SYMATTR InstName C23
SYMATTR Value 100n
SYMBOL res -160 -1600 R270
WINDOW 0 27 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName R26
SYMATTR Value 10.7k
SYMATTR SpiceLine tol=1
SYMBOL res -768 -1808 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R5
SYMATTR Value 4.99k
SYMATTR SpiceLine tol=1
SYMBOL cap -784 -1648 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C19
SYMATTR Value 10p
SYMBOL FerriteBead 208 -672 R0
SYMATTR InstName L5
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL FerriteBead 208 -2352 R0
SYMATTR InstName L6
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL cap 320 -1968 R0
WINDOW 0 -60 15 Left 2
WINDOW 3 -62 54 Left 2
SYMATTR InstName C20
SYMATTR Value 100n
SYMBOL cap -96 -816 R0
WINDOW 0 -60 15 Left 2
WINDOW 3 -62 54 Left 2
SYMATTR InstName C22
SYMATTR Value 100n
SYMBOL References\\LTC6655-1.25 2560 -1120 R0
SYMATTR InstName U4
SYMBOL cap -64 -1824 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C9
SYMATTR Value 10p
SYMBOL FerriteBead 576 -1936 R0
SYMATTR InstName L13
SYMATTR Value 1000n
SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth Elektronik" pn="782422601 WE-CBA 0402"
SYMBOL cap 704 -1088 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C13
SYMATTR Value 10p
SYMBOL res 2592 -1792 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R12
SYMATTR Value 137k
SYMBOL res 1376 -1776 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 14k
SYMBOL res 1216 -1456 R0
SYMATTR InstName R13
SYMATTR Value 56k
SYMBOL cap 1312 -1392 R0
SYMATTR InstName C3
SYMATTR Value 18n
SYMBOL cap 1056 -1856 R0
SYMATTR InstName C12
SYMATTR Value 18n
SYMBOL res 1216 -1568 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R14
SYMATTR Value 14k
SYMBOL Opamps\\LT1013 1392 -1632 R0
SYMATTR InstName U6
SYMBOL res 896 -1536 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R15
SYMATTR Value 18.7k
SYMBOL res 2048 -1840 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R16
SYMATTR Value 14k
SYMBOL cap 1728 -1872 R0
SYMATTR InstName C14
SYMATTR Value 18n
SYMBOL res 1888 -1584 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R17
SYMATTR Value 14k
SYMBOL Opamps\\LT1013 2064 -1648 R0
SYMATTR InstName U7
SYMBOL res 1568 -1552 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R18
SYMATTR Value 18.7k
SYMBOL res 1888 -1408 R0
SYMATTR InstName R19
SYMATTR Value 56k
SYMBOL cap 1984 -1344 R0
SYMATTR InstName C24
SYMATTR Value 18n
SYMBOL npn -1504 -1008 R0
SYMATTR InstName Q1
SYMATTR Value 2N5089
SYMBOL npn -1712 -1008 M0
SYMATTR InstName Q2
SYMATTR Value 2N5089
SYMBOL res 2384 -1792 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R9
SYMATTR Value 17k
SYMBOL res 2416 -1728 R0
SYMATTR InstName R28
SYMATTR Value 68k
SYMBOL Opamps\\LT1115 -656 -1472 R0
SYMATTR InstName U3
SYMBOL Opamps\\LT1115 -176 -1584 R0
SYMATTR InstName U8
SYMBOL cap 320 -1376 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C2
SYMATTR Value 3.3p
SYMBOL res -1792 -848 R0
SYMATTR InstName R7
SYMATTR Value 68
SYMBOL pnp -1840 -1632 M180
WINDOW 3 84 0 Left 2
SYMATTR Value 2N5087
SYMATTR InstName Q3
SYMBOL res -1792 -1984 R0
SYMATTR InstName R11
SYMATTR Value 270k
SYMBOL res -1632 -1920 R0
SYMATTR InstName R21
SYMATTR Value 47k
SYMBOL pnp -1296 -1824 R180
WINDOW 3 84 0 Left 2
SYMATTR Value 2N5087
SYMATTR InstName Q7
SYMBOL pnp -1264 -1824 M180
WINDOW 0 57 29 Left 2
WINDOW 3 60 62 Left 2
SYMATTR InstName Q8
SYMATTR Value 2N5087
SYMBOL res -448 -1328 R270
WINDOW 0 27 56 VTop 2
WINDOW 3 5 56 VBottom 2
SYMATTR InstName R23
SYMATTR Value 10k
SYMATTR SpiceLine tol=1
SYMBOL res -1376 -2176 R0
SYMATTR InstName R6
SYMATTR Value 1.5k
SYMBOL res -1216 -2128 R0
SYMATTR InstName R24
SYMATTR Value 1.5k
SYMBOL pnp -1264 -1680 M180
WINDOW 0 57 29 Left 2
WINDOW 3 60 62 Left 2
SYMATTR InstName Q9
SYMATTR Value 2N5087
SYMBOL npn -1504 -1200 R0
SYMATTR InstName Q10
SYMATTR Value 2N5089
SYMBOL res -1376 -2064 R0
SYMATTR InstName R27
SYMATTR Value 6.2
SYMBOL Opamps\\LT1013 -1984 -1744 R0
SYMATTR InstName U9
SYMBOL res -560 -1744 R0
SYMATTR InstName R20
SYMATTR Value 120
SYMBOL Opamps\\LT1056A 3264 -1088 R0
SYMATTR InstName U10
SYMBOL res 3136 -1328 R0
SYMATTR InstName R25
SYMATTR Value 10k
SYMBOL res 3136 -944 R0
SYMATTR InstName R29
SYMATTR Value 10k
SYMBOL res -976 -1632 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R30
SYMATTR Value 1
SYMATTR SpiceLine tol=1
SYMBOL res -1008 -1296 R0
SYMATTR InstName R31
SYMATTR Value 20k
SYMBOL res -1696 -2112 R0
SYMATTR InstName R32
SYMATTR Value 36k
SYMATTR SpiceLine tol=1
SYMBOL res -1696 -1344 R0
SYMATTR InstName R33
SYMATTR Value 18k
SYMBOL npn -1584 -1424 R0
SYMATTR InstName Q5
SYMATTR Value 2N5089
SYMBOL npn -1296 -1424 M0
SYMATTR InstName Q6
SYMATTR Value 2N5089
TEXT -2232 -1200 Left 2 !.MODEL BAS70L D \n+ IS = 3.22E-9 \n+ N = 1.018 \n+ BV = 77 \n+ IBV = 1.67E-7 \n+ RS = 20.89 \n+ CJO =
1.608E-12 \n+ VJ = 0.3891 \n+ M = 0.3683 \n+ FC = 0.5 \n+ EG = 0.69 \n+ XTI = 2 \n
TEXT -336 -528 Left 2 ;\\;R2 a,b,c, Vishay Beschlag ACAS06S0830372P1AT precision 10k resistor \n at R1a, R1b \\Maxim
MAX5492LB10000+T 10K resistive divider in a SOT-23-5 package
TEXT -720 -464 Left 2 !.MODEL MMBF4391 NJF VTO=-4.6 BETA=0.02779 LAMBDA=0.00595 RD=1 RS=1 IS=1e-14 CGD=14p CGS=10.5p PB=1 B=1
KF=1e-18 AF=1 FC=0.5 mfg=Motorola
TEXT -1112 -464 Left 2 !.tran 0 10s 0s startup
On Tue, 21 Jan 2025 14:52:03 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:uitvojh0a603a326e46go11qqcc1o1sv3p@4ax.com...
On Tue, 21 Jan 2025 11:58:15 -0500, "Edward Rawde"...
<invalid@invalid.invalid> wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
That circuit is of the category known as "component rich."
What simulation speed do you get?
It runs at about 25ms (simulation time) per second real time.
On Tue, 21 Jan 2025 14:52:03 -0500, "Edward Rawde"
<invalid@invalid.invalid> wrote:
"john larkin" <jl@glen--canyon.com> wrote in message news:uitvojh0a603a326e46go11qqcc1o1sv3p@4ax.com...
On Tue, 21 Jan 2025 11:58:15 -0500, "Edward Rawde"...
<invalid@invalid.invalid> wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
That circuit is of the category known as "component rich."
What simulation speed do you get?
That's too repulsive to sumulate.
A super-low distortion oscillator would be interesting, but a few
fundamental issues would need to be addressed first.
I'd expect that a 1 PPM THD, variable fequency sine generator
shouldn't be too difficult, but how would you measure it?
On 22/01/2025 3:58 am, Edward Rawde wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
Copy text from Version 4 to end of file directly from previous post.
Paste into new asc file using Notepad++
Note three line wraps near end of file with lines starting with 1.608E-12, MAX5492 and KF=1e-18
Position cursor at beginning of wrapped part and use backspace key to unwrap it.
Save file with no other changes. Schematic opens in LTSpice with no issues. >> Start simulation and click on Vout. Note simulation speed of about 20us/s
Copy file to other computer running LTSpice 24.1.0
Schematic opens without issues.
Attempt to start simulation.
Log file opens with errors claiming issues with U1 - U10. BAS70L is not mentioned.
Close LTSpice.
Edit asc file with Notepad++ to remove only .ENDS (note that includes the dot) from BAS70L line. Save file.
Start simulation. Simulation runs at about 25us/s with no errors.
Stop simulation.
Note that log file opens claiming Simulation Failed when really it was just stopped. 24.0.12 doesn't do that.
Examine schematic more closely.
Find tiny extraneous piece of wire between R12/R28 and R10/C11. Remove it. >> Cannot find any other schematic issues. U1 and everything else looks as intended to me.
Simulation still 25us/s
Post schematic file below as it is now on 24.1.0
I copied and pasted your file, and - after I'd sorted out the line wraps - turning off "Line Wrap" in Notepad made that a lot
easier, which was very useful advice - it run painlessly at about 25msec/sec.
It is running on LTSpice 17.0 on Windows 7, and I do have to download 17.1, which I'm going to do right now.
--
Bill Sloman, Sydney
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
Copy text from Version 4 to end of file directly from previous post.
Paste into new asc file using Notepad++
Note three line wraps near end of file with lines starting with 1.608E-12, MAX5492 and KF=1e-18
Position cursor at beginning of wrapped part and use backspace key to unwrap it.
Save file with no other changes. Schematic opens in LTSpice with no issues. Start simulation and click on Vout. Note simulation speed of about 20us/s Copy file to other computer running LTSpice 24.1.0
Schematic opens without issues.
Attempt to start simulation.
Log file opens with errors claiming issues with U1 - U10. BAS70L is not mentioned.
Close LTSpice.
Edit asc file with Notepad++ to remove only .ENDS (note that includes the dot) from BAS70L line. Save file.
Start simulation. Simulation runs at about 25us/s with no errors.
Stop simulation.
Note that log file opens claiming Simulation Failed when really it was just stopped. 24.0.12 doesn't do that.
Examine schematic more closely.
Find tiny extraneous piece of wire between R12/R28 and R10/C11. Remove it. Cannot find any other schematic issues. U1 and everything else looks as intended to me.
Simulation still 25us/s
Post schematic file below as it is now on 24.1.0
On 22/01/2025 3:58 am, Edward Rawde wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message
news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message
news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
It is running on LTSpice 17.0 on Windows 7, and I do have to download
17.1, which I'm going to do right now.
On 22/01/2025 12:32 pm, Bill Sloman wrote:
On 22/01/2025 3:58 am, Edward Rawde wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
<snip>
It is running on LTSpice 17.0 on Windows 7, and I do have to download 17.1, which I'm going to do right now.
What you get if you are running Windows 7 is version 17.0.36.0, which may explain the difference. The sim runs just as fast on the
newly uploaded software. It's unlikely that John May has stuck to Window 7. and he has reported here that he is getting the same
kind of speed.
Don posted much the same observation earlier.
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmpj6v$i521$1@dont-email.me...
On 22/01/2025 12:32 pm, Bill Sloman wrote:
On 22/01/2025 3:58 am, Edward Rawde wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
<snip>
It is running on LTSpice 17.0 on Windows 7, and I do have to download 17.1, which I'm going to do right now.
What you get if you are running Windows 7 is version 17.0.36.0, which may explain the difference. The sim runs just as fast on the
newly uploaded software. It's unlikely that John May has stuck to Window 7. and he has reported here that he is getting the same
kind of speed.
Don posted much the same observation earlier.
I put LTSpice XVII(X64) (17.0.34.0) in the administrator account of an older core i5 2.8GHz (not SSD) running Windows 11 home 23H2.
I'll be upgrading it to Windows 10 pro when I get a chance.
I didn't install any suggested LTSpice updates.
U1 was out of position but this time I had to move it up and connect the -ve power rail.
Simulation speed varies between about 6ms/s and 15 ms/s.
Vout shows a single transient at startup which peaks at about 600mv pk and settles to a constant level of around 100mV pk in a few
hundred ms.
FFT of a sample of about 100ms near 10s with Blackman Harris window shows 1kHz a little below -20dB,
2kHz -90dB (so at least 70 dB down on 1 kHz)
3kHz -70dB
4kHz -85dB
5kHz -75dB
There are no higher peaks or crud at higher frequencies.
The raw file didn't go above 1.1 GB
Now move exactly the same circuit to LTSpice 24.1.0 on a core i7 SSD Windows 10 pro 22H2.
LTSpice component updates available today 22 Jan 2025 were also installed.
U1 now has to be moved down and the +ve rail has to be connected.
Note that after saving the file in 24.1.0 the version at the top of the file becomes 4.1
Take a sample of about 10us of Vout between 300-350us and do FFT with Blackman-Harris window.
This shows a peak of -43dB at 24MHz and the next highest peak -93dB at 400MHz.
Zoom to fit and watch progress. Reported speed is about 25us/s.
Leave simulation running and do some other work.
Come back after an hour and find it has peaked at 600mV pk after 86ms simulation time and is now falling.
Take a sample of a few cycles at 86ms and run FFT with Blackman-Harris window.
1kHz -9dB
2kHz -95dB
3kHz -85dB
4kHz -110dB
24MHz -63dB
raw file has reached 40GB and simulation time is now 130ms. Level is 200mv pk and still falling
Level seems reasonably stable (100mv pk) at 220ms but take a sample and you can see it has parasitic HF crud in it.
raw file has now reached 74GB. Stop simulation.
All signal amplitude levels given are pk. pk-pk would be twice.
To avoid any doubt of what I'm simulating, it's below.
On 23/01/2025 10:56 am, Edward Rawde wrote:
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmpj6v$i521$1@dont-email.me...
On 22/01/2025 12:32 pm, Bill Sloman wrote:
On 22/01/2025 3:58 am, Edward Rawde wrote:
"Edward Rawde" <invalid@invalid.invalid> wrote in message news:vmogqg$23tl$1@nnrp.usenet.blueworldhosting.com...
"Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vmninh$3t6oi$1@dont-email.me...
On 21/01/2025 2:19 am, Bill Sloman wrote:
On 15/01/2025 11:33 pm, Bill Sloman wrote:
<snip>
It is running on LTSpice 17.0 on Windows 7, and I do have to download 17.1, which I'm going to do right now.
What you get if you are running Windows 7 is version 17.0.36.0, which may explain the difference. The sim runs just as fast on
the
newly uploaded software. It's unlikely that John May has stuck to Window 7. and he has reported here that he is getting the same
kind of speed.
Don posted much the same observation earlier.
I put LTSpice XVII(X64) (17.0.34.0) in the administrator account of an older core i5 2.8GHz (not SSD) running Windows 11 home
23H2.
I'll be upgrading it to Windows 10 pro when I get a chance.
I didn't install any suggested LTSpice updates.
U1 was out of position but this time I had to move it up and connect the -ve power rail.
Simulation speed varies between about 6ms/s and 15 ms/s.
Vout shows a single transient at startup which peaks at about 600mv pk and settles to a constant level of around 100mV pk in a
few
hundred ms.
FFT of a sample of about 100ms near 10s with Blackman Harris window shows 1kHz a little below -20dB,
2kHz -90dB (so at least 70 dB down on 1 kHz)
3kHz -70dB
4kHz -85dB
5kHz -75dB
There are no higher peaks or crud at higher frequencies.
The raw file didn't go above 1.1 GB
Now move exactly the same circuit to LTSpice 24.1.0 on a core i7 SSD Windows 10 pro 22H2.
LTSpice component updates available today 22 Jan 2025 were also installed. >> U1 now has to be moved down and the +ve rail has to be connected.
Note that after saving the file in 24.1.0 the version at the top of the file becomes 4.1
Take a sample of about 10us of Vout between 300-350us and do FFT with Blackman-Harris window.
This shows a peak of -43dB at 24MHz and the next highest peak -93dB at 400MHz.
Zoom to fit and watch progress. Reported speed is about 25us/s.
Leave simulation running and do some other work.
Come back after an hour and find it has peaked at 600mV pk after 86ms simulation time and is now falling.
Take a sample of a few cycles at 86ms and run FFT with Blackman-Harris window.
1kHz -9dB
2kHz -95dB
3kHz -85dB
4kHz -110dB
24MHz -63dB
raw file has reached 40GB and simulation time is now 130ms. Level is 200mv pk and still falling
Level seems reasonably stable (100mv pk) at 220ms but take a sample and you can see it has parasitic HF crud in it.
raw file has now reached 74GB. Stop simulation.
All signal amplitude levels given are pk. pk-pk would be twice.
To avoid any doubt of what I'm simulating, it's below.
And the problem with your version of the circuit is that C10 on the output of U4 was 3.3? rather than 3.3u, We've had that problem
before.
The LTC6655-1.25 at U1 is an an excellent voltage reference if it is loaded with at least 2.7uF. Technically speaking I should be
using the Greek symbol. Using 3300nF is safer, because not every LTSpice user takes advantage of the option to treat "u" as if was
the correct Greek alphabet look-alike.
Without enough output capacitance the LTSpice model for the LTC6655-1.25 behaves oddly. I screwed up early on and only used 1uF
and the part oscillated.
In your version of the circuit it presents a slowly rising ramp starting at 0V which had crept up to 10mV after 2 seconds.
This doesn't produce the behaviour I intended.
There's also a problem with the BAS70L diode model - your version leaves off the .ENDS line at the end of the Spice directive. The
simulation appears to run fine without it, at 30msec/sec, but I'm still nervous about it.
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