I was thinking that I might do some 32-bit phase accumulators in my
FPGA, from the highest clock frequency it can stand, and only pull out
a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
filters and schmitt gate comparators, then divide down.
In article <fmknkjpda1s2nc6d67nlqhf559v5j558ks@4ax.com>,
john larkin <JL@gct.com> wrote:
I was thinking that I might do some 32-bit phase accumulators in my
FPGA, from the highest clock frequency it can stand, and only pull out
a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
filters and schmitt gate comparators, then divide down.
I tried doing some waveform generation by something like this method
in an ICE40 FPGA, creating a 10.7 MHz IF signal for an FM-stereo
alignment generator. As I recall I used three output pins,
and a very simple resistor DAC.
The result was a nasty-looking waveform, with some serious switching
glitches at some transitions between values. There was enough
difference in signal-propagation time between the pins and the
driving gates to cause some race conditions, leading to a short
high-value spike during the transition.
Even putting the pins into registered-output mode didn't help very
much... the register-being-clocked-to-pin-transition delays weren't
constant. I think I was just asking a low-end FPGA to do things
it wasn't really designed to do.
It would have taken multiple filter stages to get rid of this.
Using Schmitt comparators (such as you suggest) would have
gotten rid of the glitches (assuming that board and part
parasitics didn't let them bleed through) but then I'd have
had to low-pass filter the comparator output again to get
something like a sinewave.
One possible way around this problem would be to arrange the outputs
to operate as a Gray code (or similar), so that one can guarantee only
a single pin transition per clock. I imagine there's probably an
R-type DAC topology which could support this, but I haven't worked
with one personally.
We have an old product, a 4-channel arb, that specifically simulates
pickups from complex rotating machines, namely jet engines.
https://highlandtechnology.com/Product/V375
It has four DDS clock synthesizers; I used AD9830s and fancy LC
filters and comparators for the clocks. They have 32-bit frequency set >registers and I'm clocking at 40 MHz, max out 15 MHz.
The design is 22 years old and, amazingly, 2024 has been its best
selling year ever. But all sorts of stuff is going EOL so I have to
redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
all the waveform memories on-chip.
I'd like an easier/cheaper way to do the DDS clocks. Maybe some RF
jocks have suggestions.
We do need the *exact* same settability as the ADI part, and it's
critical that, if we set several frequencies at some multiple of the
lowest one, the frequencies are exact and the phase relationships
never change; gears don't change their teeth or slip.
Jitter isn't too big a deal; we are simulating machines.
I was thinking that I might do some 32-bit phase accumulators in my
FPGA, from the highest clock frequency it can stand, and only pull out
a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
filters and schmitt gate comparators, then divide down. The max final >frequency could be maybe 20 or 25 MHz, somewhat higher than the old
system could do.
Any thoughts or dirty tricks? I'll brainstorm this with my >signals-and-systems jocks, but want to think about it first so I don't
look too silly.
We have an old product, a 4-channel arb, that specifically simulates
pickups from complex rotating machines, namely jet engines.
https://highlandtechnology.com/Product/V375
It has four DDS clock synthesizers; I used AD9830s and fancy LC
filters and comparators for the clocks. They have 32-bit frequency set registers and I'm clocking at 40 MHz, max out 15 MHz.
The design is 22 years old and, amazingly, 2024 has been its best
selling year ever. But all sorts of stuff is going EOL so I have to
redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
all the waveform memories on-chip.
I'd like an easier/cheaper way to do the DDS clocks. Maybe some RF
jocks have suggestions.
We do need the *exact* same settability as the ADI part, and it's
critical that, if we set several frequencies at some multiple of the
lowest one, the frequencies are exact and the phase relationships
never change; gears don't change their teeth or slip.
Jitter isn't too big a deal; we are simulating machines.
I was thinking that I might do some 32-bit phase accumulators in my
FPGA, from the highest clock frequency it can stand, and only pull out
a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
filters and schmitt gate comparators, then divide down. The max final frequency could be maybe 20 or 25 MHz, somewhat higher than the old
system could do.
Any thoughts or dirty tricks? I'll brainstorm this with my signals-and-systems jocks, but want to think about it first so I don't
look too silly.
I might simulate some cases, filter and all, but LT Spice is
impressively klutzy at digital stuff.
On 12/1/24 22:43, john larkin wrote:
I might simulate some cases, filter and all, but LT Spice is
impressively klutzy at digital stuff.
you could try Qspice, you can use verilog models in that
but it would be easier to do in matlab,octave, python, basic, c whatever
or just run verilog in a simulator
On 12/1/24 04:43, john larkin wrote:
We have an old product, a 4-channel arb, that specifically simulates
pickups from complex rotating machines, namely jet engines.
https://highlandtechnology.com/Product/V375
It has four DDS clock synthesizers; I used AD9830s and fancy LC
filters and comparators for the clocks. They have 32-bit frequency set
registers and I'm clocking at 40 MHz, max out 15 MHz.
The design is 22 years old and, amazingly, 2024 has been its best
selling year ever. But all sorts of stuff is going EOL so I have to
redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
all the waveform memories on-chip.
I'd like an easier/cheaper way to do the DDS clocks. Maybe some RF
jocks have suggestions.
We do need the *exact* same settability as the ADI part, and it's
critical that, if we set several frequencies at some multiple of the
lowest one, the frequencies are exact and the phase relationships
never change; gears don't change their teeth or slip.
Jitter isn't too big a deal; we are simulating machines.
I was thinking that I might do some 32-bit phase accumulators in my
FPGA, from the highest clock frequency it can stand, and only pull out
a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
filters and schmitt gate comparators, then divide down. The max final
frequency could be maybe 20 or 25 MHz, somewhat higher than the old
system could do.
Any thoughts or dirty tricks? I'll brainstorm this with my
signals-and-systems jocks, but want to think about it first so I don't
look too silly.
afaict the AD9830 is just a phase accumulator and a lookup table, you
should be able to do that quite a bit faster than 40MHz in an FPGA
It might be possible to use some deserialiser DDR trickery to place
edges between the main clock edges
https://highlandtechnology.com/Product/V375
It has four DDS clock synthesizers; I used AD9830s and fancy LC
filters and comparators for the clocks. They have 32-bit frequency set
registers and I'm clocking at 40 MHz, max out 15 MHz.
The design is 22 years old and, amazingly, 2024 has been its best
selling year ever. But all sorts of stuff is going EOL so I have to
redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
all the waveform memories on-chip.
afaict the AD9830 is just a phase accumulator and a lookup table, you
should be able to do that quite a bit faster than 40MHz in an FPGA
I have to make the 32-bit DDS look like it has a 40 MHz clock, for compatibility with older products.
So why have sine tables and DACs and filters and comparators? Why not
use the MSB of the phase accumulator as my system clock? I can
synthesize one octave and divide down below that.
It might be possible to spin a faster clock and make a digital filter, esentially, lowpass the accumulator triangle waveform to reduce
jitter; too much work.
I can't see the virtue of a sine lookup. The phase accumulator makes a triangle and, near the zero crossing, a sine wave looks just like a
triangle. Well, it's 2*pi steeper, but a zero crossing comparator
isn't impressed by that.
Why take a perfectly beautiful triangle and spin the poor thing all
around in a circle?
Am 07.12.24 um 00:01 schrieb john larkin:
https://highlandtechnology.com/Product/V375
It has four DDS clock synthesizers; I used AD9830s and fancy LC
filters and comparators for the clocks. They have 32-bit frequency set >>>> registers and I'm clocking at 40 MHz, max out 15 MHz.
The design is 22 years old and, amazingly, 2024 has been its best
selling year ever. But all sorts of stuff is going EOL so I have to
redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
all the waveform memories on-chip.
afaict the AD9830 is just a phase accumulator and a lookup table, you
should be able to do that quite a bit faster than 40MHz in an FPGA
I have to make the 32-bit DDS look like it has a 40 MHz clock, for
compatibility with older products.
So why have sine tables and DACs and filters and comparators? Why not
use the MSB of the phase accumulator as my system clock? I can
synthesize one octave and divide down below that.
It might be possible to spin a faster clock and make a digital filter,
esentially, lowpass the accumulator triangle waveform to reduce
jitter; too much work.
I can't see the virtue of a sine lookup. The phase accumulator makes a
triangle and, near the zero crossing, a sine wave looks just like a
triangle. Well, it's 2*pi steeper, but a zero crossing comparator
isn't impressed by that.
Why take a perfectly beautiful triangle and spin the poor thing all
around in a circle?
I published a DDS maybe 15 years ago. It ran at CLK = 230 MHz including
sine table in a Spartan-6 on a SP605 eval board. If you don't want the
sine table, leave it away. That won't make it slower :-)
It is pure VHDL, no Matlab or Xilinx macros.
< http://opencores.org/project,sincos >
The number of pipeline stages (0..10) and resolution can be set by
a constant, output width(s)is taken automagically by the buses that
are connected.
The sine ROM has only 90°, mirroring etc included. sin/cos outputs are >available at the same time yet do not need another ROM.
I needed it for an all-digital PLL, so a Cordic with it's long delays
was not an option.
cheers, Gerhard
On 07/12/2024 16:37, john larkin wrote:
On Sat, 7 Dec 2024 12:24:57 +0100, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:
Am 07.12.24 um 00:01 schrieb john larkin:
https://highlandtechnology.com/Product/V375
It has four DDS clock synthesizers; I used AD9830s and fancy LC
filters and comparators for the clocks. They have 32-bit frequency set >>>>>> registers and I'm clocking at 40 MHz, max out 15 MHz.
The design is 22 years old and, amazingly, 2024 has been its best
selling year ever. But all sorts of stuff is going EOL so I have to >>>>>> redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with >>>>>> all the waveform memories on-chip.
afaict the AD9830 is just a phase accumulator and a lookup table, you >>>>> should be able to do that quite a bit faster than 40MHz in an FPGA
I have to make the 32-bit DDS look like it has a 40 MHz clock, for
compatibility with older products.
So why have sine tables and DACs and filters and comparators? Why not
use the MSB of the phase accumulator as my system clock? I can
synthesize one octave and divide down below that.
It might be possible to spin a faster clock and make a digital filter, >>>> esentially, lowpass the accumulator triangle waveform to reduce
jitter; too much work.
I can't see the virtue of a sine lookup. The phase accumulator makes a >>>> triangle and, near the zero crossing, a sine wave looks just like a
triangle. Well, it's 2*pi steeper, but a zero crossing comparator
isn't impressed by that.
Why take a perfectly beautiful triangle and spin the poor thing all
around in a circle?
I published a DDS maybe 15 years ago. It ran at CLK = 230 MHz including
sine table in a Spartan-6 on a SP605 eval board. If you don't want the
sine table, leave it away. That won't make it slower :-)
It is pure VHDL, no Matlab or Xilinx macros.
< http://opencores.org/project,sincos >
The number of pipeline stages (0..10) and resolution can be set by
a constant, output width(s)is taken automagically by the buses that
are connected.
The sine ROM has only 90°, mirroring etc included. sin/cos outputs are
available at the same time yet do not need another ROM.
I needed it for an all-digital PLL, so a Cordic with it's long delays
was not an option.
cheers, Gerhard
Was that for an RF application? My feeling is that a
programmable-frequency digital clock doesn't care about a lot of RF
virtues. Most all that matters to us is jitter.
We're simulating rotating machines which are shaking and bending and
howling anyhow. Maybe we should add programmable jitter as a feature!
We do care about latency of a frequency change, but nobody would
notice a microsecond. Users will program many channels of new
frequencty and strobe install all atomically.
I can sort of see why one wants a sine table to make a really good RF
synth that pushes the Nyquist limits, but that's not our problem now.
An FIR lowpass filter, after the DAC, reaches out infininitely in both
directions, so shouldn't be allowed to see any gnarly edges or
anything any time in history.
Surely you mean an IIR filter...
FIR filters don't know about anything about what happens beyond
the limits of their coefficient table.
John
On Fri, 6 Dec 2024 17:46:05 +0100, Lasse Langwadt <llc@fonz.dk> wrote:
On 12/1/24 04:43, john larkin wrote:
We have an old product, a 4-channel arb, that specifically simulates
pickups from complex rotating machines, namely jet engines.
https://highlandtechnology.com/Product/V375
It has four DDS clock synthesizers; I used AD9830s and fancy LC
filters and comparators for the clocks. They have 32-bit frequency set
registers and I'm clocking at 40 MHz, max out 15 MHz.
The design is 22 years old and, amazingly, 2024 has been its best
selling year ever. But all sorts of stuff is going EOL so I have to
redesign it. I can go from 7 FPGAs and many SRAMs to one Efinix with
all the waveform memories on-chip.
I'd like an easier/cheaper way to do the DDS clocks. Maybe some RF
jocks have suggestions.
We do need the *exact* same settability as the ADI part, and it's
critical that, if we set several frequencies at some multiple of the
lowest one, the frequencies are exact and the phase relationships
never change; gears don't change their teeth or slip.
Jitter isn't too big a deal; we are simulating machines.
I was thinking that I might do some 32-bit phase accumulators in my
FPGA, from the highest clock frequency it can stand, and only pull out
a few MSBs into homemade resistor DACs, and use cheap/bad lowpass
filters and schmitt gate comparators, then divide down. The max final
frequency could be maybe 20 or 25 MHz, somewhat higher than the old
system could do.
Any thoughts or dirty tricks? I'll brainstorm this with my
signals-and-systems jocks, but want to think about it first so I don't
look too silly.
afaict the AD9830 is just a phase accumulator and a lookup table, you
should be able to do that quite a bit faster than 40MHz in an FPGA
It might be possible to use some deserialiser DDR trickery to place
edges between the main clock edges
I have to make the 32-bit DDS look like it has a 40 MHz clock, for compatibility with older products.
So why have sine tables and DACs and filters and comparators? Why not
use the MSB of the phase accumulator as my system clock? I can
synthesize one octave and divide down below that.
It might be possible to spin a faster clock and make a digital filter, esentially, lowpass the accumulator triangle waveform to reduce
jitter; too much work.
I can't see the virtue of a sine lookup. The phase accumulator makes a triangle and, near the zero crossing, a sine wave looks just like a
triangle. Well, it's 2*pi steeper, but a zero crossing comparator
isn't impressed by that.
Why take a perfectly beautiful triangle and spin the poor thing all
around in a circle?
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