• Re: Final final 1kHz oscillator

    From Bill Sloman@21:1/5 to Edward Rawde on Sat Nov 9 23:27:46 2024
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.

    If a prototype is ever built, attention to the type and quality of the capacitors used will be needed.
    Electrolytics are not intended. Put C1 and C2 near U1 supply pins.

    If electrolytics are not intended, why are most of the capacitors rated at 10V?

    Yes


    When I cut and pasted the file the capacitors were mostly labelled as 10?, 1? and - in the case of the wein bridge capacitors
    0.015?


    When I cut and pasted the file into notepad++ and removed line 391 and subsequent lines (or fixed wraps) and under encoding
    converted to ANSI everything worked fine.

    The 15nF capacitors are rated at 16V - the polypropylene parts you can actually buy that are offered with a +/-1% tolerance are
    63V and 250V parts

    You'd have to take that up with the LTSpice parts library.

    You put that parts in.

    I presume you intended u or the Greek mu symbol, and after I'd done that substitution the simulation did work, if not well.

    No substitution is required if you convert to ANSI in notepad++

    Perhaps.

    The feedback loop doesn't settle well, and I suspect that I know why. R4 should probably be in series with C3, not in parallel.
    More later.

    In fact I also had to take out C6 and R9. Once I'd done that the circuit simulated a lot faster, and settled down after about 20 seconds. The
    next 20 seconds showed a third harmonic spike about 60DB below the
    fundamental - respectable but not great. Putting too much delay into a
    feedback loop makes it unstable - that's what Bode plots are all about.

    --
    Bill Sloman, Sydney

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to All on Sat Nov 9 13:16:30 2024
    On Sat, 9 Nov 2024 18:54:46 +1100, Bill Sloman <bill.sloman@ieee.org>
    wrote:

    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.

    If a prototype is ever built, attention to the type and quality of the capacitors used will be needed.
    Electrolytics are not intended. Put C1 and C2 near U1 supply pins.

    If electrolytics are not intended, why are most of the capacitors rated
    at 10V?

    When I cut and pasted the file the capacitors were mostly labelled as
    10?, 1? and - in the case of the wein bridge capacitors 0.015?

    The 15nF capacitors are rated at 16V - the polypropylene parts you can >actually buy that are offered with a +/-1% tolerance are 63V and 250V parts

    I presume you intended u or the Greek mu symbol, and after I'd done that >substitution the simulation did work, if not well.

    The feedback loop doesn't settle well, and I suspect that I know why. R4 >should probably be in series with C3, not in parallel. More later.

    --
    Bill Sloman, Sydney

    Those characters are also rendering incorrectly here, too.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sat Nov 9 12:50:30 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.

    If a prototype is ever built, attention to the type and quality of the capacitors used will be needed.
    Electrolytics are not intended. Put C1 and C2 near U1 supply pins.

    ...

    In fact I also had to take out C6 and R9. Once I'd done that the circuit simulated a lot faster, and settled down after about 20
    seconds. The next 20 seconds showed a third harmonic spike about 60DB below the fundamental - respectable but not great. Putting
    too much delay into a feedback loop makes it unstable - that's what Bode plots are all about.

    There certainly are issues with this circuit despite its ability in simulation to show 80dB down on harmonics.

    So perhaps this is not the final final circuit after all.

    U2A is not operateing as intended.
    C3 can be removed for testing.


    --
    Bill Sloman, Sydney

    --
    Bill Sloman, Sydney



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sun Nov 10 00:49:36 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers.
    This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    There are two things I don't understand about my own circuit.

    1. Why does LT1678 work fine in position U2 but LT1057 does not.
    2. Why is the DC stabilization circuit (U3 and associated components) needed and would it work just the same in reality?

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    TEXT -624 272 Left 2 !.tran 0 150s 0s startup

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to invalid@invalid.invalid on Sun Nov 10 12:17:34 2024
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers.
    This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place, even if the sim is left to run its
    full course. Also, what's the purpose of the 6 diodes in series at the
    top of the schematic? If you need to drop 4V there ought to be a more
    elegant way of doing it!



    There are two things I don't understand about my own circuit.

    1. Why does LT1678 work fine in position U2 but LT1057 does not.
    2. Why is the DC stabilization circuit (U3 and associated components) needed and would it work just the same in reality?

    Version 4
    SHEET 1 2196 932
    WIRE -64 -576 -96 -576
    WIRE 48 -576 16 -576
    WIRE 128 -528 112 -528
    WIRE 208 -528 192 -528
    WIRE 288 -528 272 -528
    WIRE 368 -528 352 -528
    WIRE 448 -528 432 -528
    WIRE 528 -528 512 -528
    WIRE 640 -528 592 -528
    WIRE 640 -512 640 -528
    WIRE -32 -464 -32 -480
    WIRE 48 -448 48 -576
    WIRE 48 -448 0 -448
    WIRE -96 -432 -96 -576
    WIRE -64 -432 -96 -432
    WIRE 112 -416 112 -528
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    WIRE 160 -416 112 -416
    WIRE 208 -416 160 -416
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    WIRE -176 96 -240 96
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    WIRE 112 96 64 96
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    WIRE 512 96 272 96
    WIRE -32 128 -96 128
    WIRE 112 128 -32 128
    WIRE -320 144 -320 96
    WIRE 624 144 624 -224
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    WIRE 752 144 720 144
    WIRE -176 160 -176 96
    WIRE -32 160 -32 128
    WIRE 112 160 64 160
    WIRE 624 160 624 144
    WIRE 624 160 272 160
    WIRE 752 176 752 144
    WIRE 144 224 144 208
    WIRE -32 256 -32 224
    WIRE 64 272 64 160
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    WIRE 64 288 64 272
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    WIRE 752 288 752 256
    WIRE 880 288 752 288
    WIRE 928 288 880 288
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    WIRE -320 320 -400 320
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    WIRE -320 336 -320 320
    WIRE -176 336 -176 224
    WIRE -176 336 -320 336
    WIRE -96 336 -96 128
    WIRE 64 384 64 368
    WIRE 160 384 160 352
    WIRE 160 384 64 384
    WIRE -320 416 -320 336
    WIRE 64 416 64 384
    WIRE -176 432 -176 336
    WIRE 192 432 144 432
    WIRE 304 432 272 432
    WIRE 384 432 368 432
    WIRE 928 432 928 400
    WIRE 512 448 512 272
    WIRE 624 448 624 160
    WIRE 288 544 288 528
    WIRE 384 560 384 432
    WIRE 384 560 320 560
    WIRE 624 560 624 512
    WIRE 624 560 384 560
    WIRE -96 576 -96 416
    WIRE -48 576 -96 576
    WIRE 32 576 -48 576
    WIRE 144 576 144 432
    WIRE 144 576 112 576
    WIRE 208 576 144 576
    WIRE 256 576 208 576
    WIRE -320 592 -320 496
    WIRE -240 592 -320 592
    WIRE -176 592 -176 496
    WIRE -176 592 -240 592
    WIRE 432 592 320 592
    WIRE 512 592 512 512
    WIRE 512 592 432 592
    WIRE 624 592 624 560
    WIRE 704 592 624 592
    WIRE -96 624 -96 576
    WIRE -48 624 -48 576
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    WIRE 704 624 704 592
    WIRE 432 640 432 592
    WIRE 624 640 624 592
    WIRE -96 736 -96 688
    WIRE -48 736 -48 688
    WIRE -48 736 -96 736
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    WIRE 512 736 512 704
    WIRE 512 736 432 736
    WIRE 624 736 624 704
    WIRE 624 736 512 736
    WIRE 704 736 704 704
    WIRE 704 736 624 736
    WIRE -96 768 -96 736
    WIRE 432 768 432 736
    FLAG -400 336 0
    FLAG 288 528 V+
    FLAG 144 224 V-
    FLAG -240 96 V+
    FLAG -240 592 V-
    FLAG 880 288 output
    FLAG 144 32 V+
    FLAG 288 624 V-
    FLAG 432 768 0
    FLAG -32 256 0
    FLAG -32 -480 V+
    FLAG -32 -384 V-
    FLAG -256 0 0
    FLAG 400 -240 0
    FLAG 160 -240 0
    FLAG 64 416 0
    FLAG 336 -240 0
    FLAG -96 768 0
    FLAG 208 576 dc-trim
    FLAG 640 -512 0
    FLAG 48 -240 0
    FLAG 928 432 0
    SYMBOL voltage -320 128 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL res 496 256 R90
    WINDOW 0 1 52 VBottom 2
    WINDOW 3 33 45 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 10.5k
    SYMBOL cap 352 256 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 35 30 VTop 2
    SYMATTR InstName C8
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL res 240 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 448 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL njf -128 -176 R90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -320 400 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V2
    SYMATTR Value 6
    SYMBOL res 48 272 R0
    WINDOW 3 36 65 Left 2
    SYMATTR Value 10.5k
    SYMATTR InstName R10
    SYMBOL schottky 496 -288 R0
    WINDOW 3 -17 -26 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -112 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 82
    SYMBOL OpAmps\\LT1994 176 128 R0
    WINDOW 3 10 -65 Left 2
    WINDOW 0 11 -95 Left 2
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1057 288 512 M0
    WINDOW 0 19 104 Left 2
    WINDOW 3 18 130 Left 2
    SYMATTR InstName U3
    SYMBOL schottky 528 448 M0
    WINDOW 3 52 -26 VRight 2
    WINDOW 0 -18 3 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D3
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL schottky 640 448 M0
    WINDOW 3 49 -26 VRight 2
    WINDOW 0 -21 4 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D4
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 528 608 M0
    WINDOW 3 25 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R16
    SYMBOL res 720 608 M0
    WINDOW 3 27 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R17
    SYMBOL res -112 -256 R0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 320 -384 R0
    WINDOW 0 -50 69 Left 2
    WINDOW 3 -54 98 Left 2
    SYMATTR InstName R13
    SYMATTR Value 220k
    SYMBOL res 448 -32 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 1.0469Meg
    SYMBOL res -80 -288 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res -80 432 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 33k
    SYMBOL res 176 416 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R15
    SYMATTR Value 220
    SYMBOL res 16 560 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 10k
    SYMBOL cap 176 352 R180
    WINDOW 0 -37 41 Left 2
    WINDOW 3 -50 13 Left 2
    SYMATTR InstName C7
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL cap 720 128 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 100000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
    SYMBOL res 736 160 R0
    SYMATTR InstName R18
    SYMATTR Value 600
    SYMBOL res 192 -400 R270
    WINDOW 0 35 55 VTop 2
    WINDOW 3 -6 55 VBottom 2
    SYMATTR InstName R12
    SYMATTR Value 220k
    SYMBOL cap 176 -352 M0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 48 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 -352 M0
    WINDOW 0 -32 51 Left 2
    WINDOW 3 -72 7 Left 2
    SYMATTR InstName C10
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 368 448 M270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C9
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 640 R0
    WINDOW 0 -37 6 Left 2
    WINDOW 3 -77 53 Left 2
    SYMATTR InstName C11
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 608 640 R0
    WINDOW 0 -33 9 Left 2
    WINDOW 3 -72 51 Left 2
    SYMATTR InstName C12
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 160 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -79 48 Left 2
    SYMATTR InstName C1
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 432 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 50 Left 2
    SYMATTR InstName C2
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -16 224 R180
    WINDOW 0 23 78 Left 2
    WINDOW 3 -74 78 Left 2
    SYMATTR InstName C4
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL diode -80 688 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL cap -64 688 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM032R60J105ME05" type="X5R"
    SYMBOL OpAmps\\LT1678 -32 -432 M0
    WINDOW 0 -47 50 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2
    SYMBOL diode 192 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D6
    SYMATTR Value 1N914
    SYMBOL diode 272 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D7
    SYMATTR Value 1N914
    SYMBOL diode 352 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D8
    SYMATTR Value 1N914
    SYMBOL diode 432 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D9
    SYMATTR Value 1N914
    SYMBOL diode 512 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D10
    SYMATTR Value 1N914
    SYMBOL schottky 608 -288 R0
    SYMATTR Value BAS40HY
    SYMATTR InstName D2
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -80 -560 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 32 -384 R0
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL diode 592 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D11
    SYMATTR Value 1N914
    SYMBOL res 912 304 R0
    SYMATTR InstName R19
    SYMATTR Value 600
    TEXT -624 272 Left 2 !.tran 0 150s 0s startup


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Cursitor Doom on Sun Nov 10 12:12:34 2024
    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers.
    This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place,

    Change R9 to 1.07Meg does it amplitude stabilize now?
    Adjustment will be needed in any real circuit.

    even if the sim is left to run its
    full course. Also, what's the purpose of the 6 diodes in series at the
    top of the schematic? If you need to drop 4V there ought to be a more
    elegant way of doing it!



    There are two things I don't understand about my own circuit.

    1. Why does LT1678 work fine in position U2 but LT1057 does not.
    2. Why is the DC stabilization circuit (U3 and associated components) needed and would it work just the same in reality?

    Version 4
    SHEET 1 2196 932
    WIRE -64 -576 -96 -576
    WIRE 48 -576 16 -576
    WIRE 128 -528 112 -528
    WIRE 208 -528 192 -528
    WIRE 288 -528 272 -528
    WIRE 368 -528 352 -528
    WIRE 448 -528 432 -528
    WIRE 528 -528 512 -528
    WIRE 640 -528 592 -528
    WIRE 640 -512 640 -528
    WIRE -32 -464 -32 -480
    WIRE 48 -448 48 -576
    WIRE 48 -448 0 -448
    WIRE -96 -432 -96 -576
    WIRE -64 -432 -96 -432
    WIRE 112 -416 112 -528
    WIRE 112 -416 0 -416
    WIRE 160 -416 112 -416
    WIRE 208 -416 160 -416
    WIRE 336 -416 288 -416
    WIRE 400 -416 336 -416
    WIRE 512 -416 400 -416
    WIRE 624 -416 512 -416
    WIRE -96 -384 -96 -432
    WIRE -32 -384 -32 -400
    WIRE 48 -368 48 -448
    WIRE 336 -368 336 -416
    WIRE 160 -352 160 -416
    WIRE 400 -352 400 -416
    WIRE 512 -288 512 -416
    WIRE 624 -288 624 -416
    WIRE -96 -272 -96 -304
    WIRE -96 -272 -192 -272
    WIRE -96 -240 -96 -272
    WIRE 48 -240 48 -288
    WIRE 160 -240 160 -288
    WIRE 336 -240 336 -288
    WIRE 400 -240 400 -288
    WIRE -192 -176 -192 -272
    WIRE -224 -128 -256 -128
    WIRE -96 -128 -96 -160
    WIRE -96 -128 -128 -128
    WIRE -80 -128 -96 -128
    WIRE 144 -128 -80 -128
    WIRE 288 -128 224 -128
    WIRE 352 -128 288 -128
    WIRE 512 -128 512 -224
    WIRE 512 -128 432 -128
    WIRE -256 -48 -256 -128
    WIRE -208 -48 -256 -48
    WIRE -80 -48 -80 -128
    WIRE -80 -48 -128 -48
    WIRE 288 -16 288 -128
    WIRE 288 -16 64 -16
    WIRE 352 -16 288 -16
    WIRE 512 -16 512 -128
    WIRE 512 -16 432 -16
    WIRE -256 0 -256 -48
    WIRE 144 48 144 32
    WIRE -240 96 -320 96
    WIRE -176 96 -240 96
    WIRE 64 96 64 -16
    WIRE 112 96 64 96
    WIRE 512 96 512 -16
    WIRE 512 96 272 96
    WIRE -32 128 -96 128
    WIRE 112 128 -32 128
    WIRE -320 144 -320 96
    WIRE 624 144 624 -224
    WIRE 656 144 624 144
    WIRE 752 144 720 144
    WIRE -176 160 -176 96
    WIRE -32 160 -32 128
    WIRE 112 160 64 160
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    WIRE 624 160 272 160
    WIRE 752 176 752 144
    WIRE 144 224 144 208
    WIRE -32 256 -32 224
    WIRE 64 272 64 160
    WIRE 160 272 64 272
    WIRE 288 272 160 272
    WIRE 400 272 352 272
    WIRE 512 272 512 96
    WIRE 512 272 480 272
    WIRE 64 288 64 272
    WIRE 160 288 160 272
    WIRE 752 288 752 256
    WIRE 880 288 752 288
    WIRE 928 288 880 288
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    WIRE -320 320 -400 320
    WIRE 928 320 928 288
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    WIRE -320 336 -320 320
    WIRE -176 336 -176 224
    WIRE -176 336 -320 336
    WIRE -96 336 -96 128
    WIRE 64 384 64 368
    WIRE 160 384 160 352
    WIRE 160 384 64 384
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    WIRE 64 416 64 384
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    WIRE 384 560 320 560
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    WIRE -48 576 -96 576
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    WIRE 144 576 112 576
    WIRE 208 576 144 576
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    WIRE -320 592 -320 496
    WIRE -240 592 -320 592
    WIRE -176 592 -176 496
    WIRE -176 592 -240 592
    WIRE 432 592 320 592
    WIRE 512 592 512 512
    WIRE 512 592 432 592
    WIRE 624 592 624 560
    WIRE 704 592 624 592
    WIRE -96 624 -96 576
    WIRE -48 624 -48 576
    WIRE 288 624 288 608
    WIRE 512 624 512 592
    WIRE 704 624 704 592
    WIRE 432 640 432 592
    WIRE 624 640 624 592
    WIRE -96 736 -96 688
    WIRE -48 736 -48 688
    WIRE -48 736 -96 736
    WIRE 432 736 432 704
    WIRE 512 736 512 704
    WIRE 512 736 432 736
    WIRE 624 736 624 704
    WIRE 624 736 512 736
    WIRE 704 736 704 704
    WIRE 704 736 624 736
    WIRE -96 768 -96 736
    WIRE 432 768 432 736
    FLAG -400 336 0
    FLAG 288 528 V+
    FLAG 144 224 V-
    FLAG -240 96 V+
    FLAG -240 592 V-
    FLAG 880 288 output
    FLAG 144 32 V+
    FLAG 288 624 V-
    FLAG 432 768 0
    FLAG -32 256 0
    FLAG -32 -480 V+
    FLAG -32 -384 V-
    FLAG -256 0 0
    FLAG 400 -240 0
    FLAG 160 -240 0
    FLAG 64 416 0
    FLAG 336 -240 0
    FLAG -96 768 0
    FLAG 208 576 dc-trim
    FLAG 640 -512 0
    FLAG 48 -240 0
    FLAG 928 432 0
    SYMBOL voltage -320 128 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL res 496 256 R90
    WINDOW 0 1 52 VBottom 2
    WINDOW 3 33 45 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 10.5k
    SYMBOL cap 352 256 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 35 30 VTop 2
    SYMATTR InstName C8
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL res 240 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 448 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL njf -128 -176 R90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -320 400 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V2
    SYMATTR Value 6
    SYMBOL res 48 272 R0
    WINDOW 3 36 65 Left 2
    SYMATTR Value 10.5k
    SYMATTR InstName R10
    SYMBOL schottky 496 -288 R0
    WINDOW 3 -17 -26 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -112 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 82
    SYMBOL OpAmps\\LT1994 176 128 R0
    WINDOW 3 10 -65 Left 2
    WINDOW 0 11 -95 Left 2
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1057 288 512 M0
    WINDOW 0 19 104 Left 2
    WINDOW 3 18 130 Left 2
    SYMATTR InstName U3
    SYMBOL schottky 528 448 M0
    WINDOW 3 52 -26 VRight 2
    WINDOW 0 -18 3 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D3
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL schottky 640 448 M0
    WINDOW 3 49 -26 VRight 2
    WINDOW 0 -21 4 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D4
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 528 608 M0
    WINDOW 3 25 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R16
    SYMBOL res 720 608 M0
    WINDOW 3 27 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R17
    SYMBOL res -112 -256 R0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 320 -384 R0
    WINDOW 0 -50 69 Left 2
    WINDOW 3 -54 98 Left 2
    SYMATTR InstName R13
    SYMATTR Value 220k
    SYMBOL res 448 -32 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 1.0469Meg
    SYMBOL res -80 -288 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res -80 432 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 33k
    SYMBOL res 176 416 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R15
    SYMATTR Value 220
    SYMBOL res 16 560 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 10k
    SYMBOL cap 176 352 R180
    WINDOW 0 -37 41 Left 2
    WINDOW 3 -50 13 Left 2
    SYMATTR InstName C7
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL cap 720 128 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 100000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
    SYMBOL res 736 160 R0
    SYMATTR InstName R18
    SYMATTR Value 600
    SYMBOL res 192 -400 R270
    WINDOW 0 35 55 VTop 2
    WINDOW 3 -6 55 VBottom 2
    SYMATTR InstName R12
    SYMATTR Value 220k
    SYMBOL cap 176 -352 M0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 48 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 -352 M0
    WINDOW 0 -32 51 Left 2
    WINDOW 3 -72 7 Left 2
    SYMATTR InstName C10
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 368 448 M270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C9
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 640 R0
    WINDOW 0 -37 6 Left 2
    WINDOW 3 -77 53 Left 2
    SYMATTR InstName C11
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 608 640 R0
    WINDOW 0 -33 9 Left 2
    WINDOW 3 -72 51 Left 2
    SYMATTR InstName C12
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 160 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -79 48 Left 2
    SYMATTR InstName C1
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 432 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 50 Left 2
    SYMATTR InstName C2
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -16 224 R180
    WINDOW 0 23 78 Left 2
    WINDOW 3 -74 78 Left 2
    SYMATTR InstName C4
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL diode -80 688 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL cap -64 688 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM032R60J105ME05" type="X5R"
    SYMBOL OpAmps\\LT1678 -32 -432 M0
    WINDOW 0 -47 50 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2
    SYMBOL diode 192 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D6
    SYMATTR Value 1N914
    SYMBOL diode 272 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D7
    SYMATTR Value 1N914
    SYMBOL diode 352 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D8
    SYMATTR Value 1N914
    SYMBOL diode 432 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D9
    SYMATTR Value 1N914
    SYMBOL diode 512 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D10
    SYMATTR Value 1N914
    SYMBOL schottky 608 -288 R0
    SYMATTR Value BAS40HY
    SYMATTR InstName D2
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -80 -560 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 32 -384 R0
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL diode 592 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D11
    SYMATTR Value 1N914
    SYMBOL res 912 304 R0
    SYMATTR InstName R19
    SYMATTR Value 600
    TEXT -624 272 Left 2 !.tran 0 150s 0s startup


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Cursitor Doom on Sun Nov 10 11:42:03 2024
    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers.
    This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place, even if the sim is left to run its
    full course.

    In that case there is some unknown difference between your simulation and mine. I just copy/pasted it directly from my post into sine.asc and ran the simulation.
    The output is totally stable after 20 seconds and remains stable for the rest of the simulation.

    One of the reasons this circuit can produce such a pure output is the filter components R12 and C6.
    This makes it so that what is sent to the FET gate can't be much different from DC when the amplitude control loop is locked on to
    the correct control point.

    But the filter components introduce a lot of lag (Bill also pointed this out). So I tried another op amp as a lag compensator (which also inverted so I change to a P FET).
    This worked fine and the output was almost immediately stable at the correct level.
    But it also had the effect of introducing noise to the extent that I couldn't get below 50dB down.

    So I looked for another solution.
    One way to force the amplitude control loop to lock is to do just that.
    Make it so that the control voltage can't go too far outside the required range.
    That's what the diode clamp does.

    Is your version of LTSpice fully up to date both main program and library?
    If so then it wouldn't surprise me if differences between computers cause differences in simulation of this circuit.
    Try adjusting the last two digits of the value of R9

    Also, what's the purpose of the 6 diodes in series at the
    top of the schematic? If you need to drop 4V there ought to be a more
    elegant way of doing it!



    There are two things I don't understand about my own circuit.

    1. Why does LT1678 work fine in position U2 but LT1057 does not.
    2. Why is the DC stabilization circuit (U3 and associated components) needed and would it work just the same in reality?

    Version 4
    SHEET 1 2196 932
    WIRE -64 -576 -96 -576
    WIRE 48 -576 16 -576
    WIRE 128 -528 112 -528
    WIRE 208 -528 192 -528
    WIRE 288 -528 272 -528
    WIRE 368 -528 352 -528
    WIRE 448 -528 432 -528
    WIRE 528 -528 512 -528
    WIRE 640 -528 592 -528
    WIRE 640 -512 640 -528
    WIRE -32 -464 -32 -480
    WIRE 48 -448 48 -576
    WIRE 48 -448 0 -448
    WIRE -96 -432 -96 -576
    WIRE -64 -432 -96 -432
    WIRE 112 -416 112 -528
    WIRE 112 -416 0 -416
    WIRE 160 -416 112 -416
    WIRE 208 -416 160 -416
    WIRE 336 -416 288 -416
    WIRE 400 -416 336 -416
    WIRE 512 -416 400 -416
    WIRE 624 -416 512 -416
    WIRE -96 -384 -96 -432
    WIRE -32 -384 -32 -400
    WIRE 48 -368 48 -448
    WIRE 336 -368 336 -416
    WIRE 160 -352 160 -416
    WIRE 400 -352 400 -416
    WIRE 512 -288 512 -416
    WIRE 624 -288 624 -416
    WIRE -96 -272 -96 -304
    WIRE -96 -272 -192 -272
    WIRE -96 -240 -96 -272
    WIRE 48 -240 48 -288
    WIRE 160 -240 160 -288
    WIRE 336 -240 336 -288
    WIRE 400 -240 400 -288
    WIRE -192 -176 -192 -272
    WIRE -224 -128 -256 -128
    WIRE -96 -128 -96 -160
    WIRE -96 -128 -128 -128
    WIRE -80 -128 -96 -128
    WIRE 144 -128 -80 -128
    WIRE 288 -128 224 -128
    WIRE 352 -128 288 -128
    WIRE 512 -128 512 -224
    WIRE 512 -128 432 -128
    WIRE -256 -48 -256 -128
    WIRE -208 -48 -256 -48
    WIRE -80 -48 -80 -128
    WIRE -80 -48 -128 -48
    WIRE 288 -16 288 -128
    WIRE 288 -16 64 -16
    WIRE 352 -16 288 -16
    WIRE 512 -16 512 -128
    WIRE 512 -16 432 -16
    WIRE -256 0 -256 -48
    WIRE 144 48 144 32
    WIRE -240 96 -320 96
    WIRE -176 96 -240 96
    WIRE 64 96 64 -16
    WIRE 112 96 64 96
    WIRE 512 96 512 -16
    WIRE 512 96 272 96
    WIRE -32 128 -96 128
    WIRE 112 128 -32 128
    WIRE -320 144 -320 96
    WIRE 624 144 624 -224
    WIRE 656 144 624 144
    WIRE 752 144 720 144
    WIRE -176 160 -176 96
    WIRE -32 160 -32 128
    WIRE 112 160 64 160
    WIRE 624 160 624 144
    WIRE 624 160 272 160
    WIRE 752 176 752 144
    WIRE 144 224 144 208
    WIRE -32 256 -32 224
    WIRE 64 272 64 160
    WIRE 160 272 64 272
    WIRE 288 272 160 272
    WIRE 400 272 352 272
    WIRE 512 272 512 96
    WIRE 512 272 480 272
    WIRE 64 288 64 272
    WIRE 160 288 160 272
    WIRE 752 288 752 256
    WIRE 880 288 752 288
    WIRE 928 288 880 288
    WIRE -320 320 -320 224
    WIRE -320 320 -400 320
    WIRE 928 320 928 288
    WIRE -400 336 -400 320
    WIRE -320 336 -320 320
    WIRE -176 336 -176 224
    WIRE -176 336 -320 336
    WIRE -96 336 -96 128
    WIRE 64 384 64 368
    WIRE 160 384 160 352
    WIRE 160 384 64 384
    WIRE -320 416 -320 336
    WIRE 64 416 64 384
    WIRE -176 432 -176 336
    WIRE 192 432 144 432
    WIRE 304 432 272 432
    WIRE 384 432 368 432
    WIRE 928 432 928 400
    WIRE 512 448 512 272
    WIRE 624 448 624 160
    WIRE 288 544 288 528
    WIRE 384 560 384 432
    WIRE 384 560 320 560
    WIRE 624 560 624 512
    WIRE 624 560 384 560
    WIRE -96 576 -96 416
    WIRE -48 576 -96 576
    WIRE 32 576 -48 576
    WIRE 144 576 144 432
    WIRE 144 576 112 576
    WIRE 208 576 144 576
    WIRE 256 576 208 576
    WIRE -320 592 -320 496
    WIRE -240 592 -320 592
    WIRE -176 592 -176 496
    WIRE -176 592 -240 592
    WIRE 432 592 320 592
    WIRE 512 592 512 512
    WIRE 512 592 432 592
    WIRE 624 592 624 560
    WIRE 704 592 624 592
    WIRE -96 624 -96 576
    WIRE -48 624 -48 576
    WIRE 288 624 288 608
    WIRE 512 624 512 592
    WIRE 704 624 704 592
    WIRE 432 640 432 592
    WIRE 624 640 624 592
    WIRE -96 736 -96 688
    WIRE -48 736 -48 688
    WIRE -48 736 -96 736
    WIRE 432 736 432 704
    WIRE 512 736 512 704
    WIRE 512 736 432 736
    WIRE 624 736 624 704
    WIRE 624 736 512 736
    WIRE 704 736 704 704
    WIRE 704 736 624 736
    WIRE -96 768 -96 736
    WIRE 432 768 432 736
    FLAG -400 336 0
    FLAG 288 528 V+
    FLAG 144 224 V-
    FLAG -240 96 V+
    FLAG -240 592 V-
    FLAG 880 288 output
    FLAG 144 32 V+
    FLAG 288 624 V-
    FLAG 432 768 0
    FLAG -32 256 0
    FLAG -32 -480 V+
    FLAG -32 -384 V-
    FLAG -256 0 0
    FLAG 400 -240 0
    FLAG 160 -240 0
    FLAG 64 416 0
    FLAG 336 -240 0
    FLAG -96 768 0
    FLAG 208 576 dc-trim
    FLAG 640 -512 0
    FLAG 48 -240 0
    FLAG 928 432 0
    SYMBOL voltage -320 128 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL res 496 256 R90
    WINDOW 0 1 52 VBottom 2
    WINDOW 3 33 45 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 10.5k
    SYMBOL cap 352 256 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 35 30 VTop 2
    SYMATTR InstName C8
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL res 240 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 448 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL njf -128 -176 R90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -320 400 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V2
    SYMATTR Value 6
    SYMBOL res 48 272 R0
    WINDOW 3 36 65 Left 2
    SYMATTR Value 10.5k
    SYMATTR InstName R10
    SYMBOL schottky 496 -288 R0
    WINDOW 3 -17 -26 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -112 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 82
    SYMBOL OpAmps\\LT1994 176 128 R0
    WINDOW 3 10 -65 Left 2
    WINDOW 0 11 -95 Left 2
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1057 288 512 M0
    WINDOW 0 19 104 Left 2
    WINDOW 3 18 130 Left 2
    SYMATTR InstName U3
    SYMBOL schottky 528 448 M0
    WINDOW 3 52 -26 VRight 2
    WINDOW 0 -18 3 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D3
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL schottky 640 448 M0
    WINDOW 3 49 -26 VRight 2
    WINDOW 0 -21 4 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D4
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 528 608 M0
    WINDOW 3 25 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R16
    SYMBOL res 720 608 M0
    WINDOW 3 27 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R17
    SYMBOL res -112 -256 R0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 320 -384 R0
    WINDOW 0 -50 69 Left 2
    WINDOW 3 -54 98 Left 2
    SYMATTR InstName R13
    SYMATTR Value 220k
    SYMBOL res 448 -32 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 1.0469Meg
    SYMBOL res -80 -288 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res -80 432 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 33k
    SYMBOL res 176 416 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R15
    SYMATTR Value 220
    SYMBOL res 16 560 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 10k
    SYMBOL cap 176 352 R180
    WINDOW 0 -37 41 Left 2
    WINDOW 3 -50 13 Left 2
    SYMATTR InstName C7
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL cap 720 128 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 100000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
    SYMBOL res 736 160 R0
    SYMATTR InstName R18
    SYMATTR Value 600
    SYMBOL res 192 -400 R270
    WINDOW 0 35 55 VTop 2
    WINDOW 3 -6 55 VBottom 2
    SYMATTR InstName R12
    SYMATTR Value 220k
    SYMBOL cap 176 -352 M0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 48 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 -352 M0
    WINDOW 0 -32 51 Left 2
    WINDOW 3 -72 7 Left 2
    SYMATTR InstName C10
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 368 448 M270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C9
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 640 R0
    WINDOW 0 -37 6 Left 2
    WINDOW 3 -77 53 Left 2
    SYMATTR InstName C11
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 608 640 R0
    WINDOW 0 -33 9 Left 2
    WINDOW 3 -72 51 Left 2
    SYMATTR InstName C12
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 160 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -79 48 Left 2
    SYMATTR InstName C1
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 432 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 50 Left 2
    SYMATTR InstName C2
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -16 224 R180
    WINDOW 0 23 78 Left 2
    WINDOW 3 -74 78 Left 2
    SYMATTR InstName C4
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL diode -80 688 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL cap -64 688 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM032R60J105ME05" type="X5R"
    SYMBOL OpAmps\\LT1678 -32 -432 M0
    WINDOW 0 -47 50 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2
    SYMBOL diode 192 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D6
    SYMATTR Value 1N914
    SYMBOL diode 272 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D7
    SYMATTR Value 1N914
    SYMBOL diode 352 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D8
    SYMATTR Value 1N914
    SYMBOL diode 432 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D9
    SYMATTR Value 1N914
    SYMBOL diode 512 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D10
    SYMATTR Value 1N914
    SYMBOL schottky 608 -288 R0
    SYMATTR Value BAS40HY
    SYMATTR InstName D2
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -80 -560 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 32 -384 R0
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL diode 592 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D11
    SYMATTR Value 1N914
    SYMBOL res 912 304 R0
    SYMATTR InstName R19
    SYMATTR Value 600
    TEXT -624 272 Left 2 !.tran 0 150s 0s startup


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to invalid@invalid.invalid on Sun Nov 10 17:45:00 2024
    On Sun, 10 Nov 2024 12:12:34 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers. >>>This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place,

    Change R9 to 1.07Meg does it amplitude stabilize now?
    Adjustment will be needed in any real circuit.

    Indeed, but for a simulation we should be seeing identical results!
    I've made the change as you suggested and it's increased the sim time considerably. I'll post again when it's completed.



    even if the sim is left to run its
    full course. Also, what's the purpose of the 6 diodes in series at the
    top of the schematic? If you need to drop 4V there ought to be a more
    elegant way of doing it!



    There are two things I don't understand about my own circuit.

    1. Why does LT1678 work fine in position U2 but LT1057 does not.
    2. Why is the DC stabilization circuit (U3 and associated components) needed and would it work just the same in reality?

    Version 4
    SHEET 1 2196 932
    WIRE -64 -576 -96 -576
    WIRE 48 -576 16 -576
    WIRE 128 -528 112 -528
    WIRE 208 -528 192 -528
    WIRE 288 -528 272 -528
    WIRE 368 -528 352 -528
    WIRE 448 -528 432 -528
    WIRE 528 -528 512 -528
    WIRE 640 -528 592 -528
    WIRE 640 -512 640 -528
    WIRE -32 -464 -32 -480
    WIRE 48 -448 48 -576
    WIRE 48 -448 0 -448
    WIRE -96 -432 -96 -576
    WIRE -64 -432 -96 -432
    WIRE 112 -416 112 -528
    WIRE 112 -416 0 -416
    WIRE 160 -416 112 -416
    WIRE 208 -416 160 -416
    WIRE 336 -416 288 -416
    WIRE 400 -416 336 -416
    WIRE 512 -416 400 -416
    WIRE 624 -416 512 -416
    WIRE -96 -384 -96 -432
    WIRE -32 -384 -32 -400
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    WIRE 336 -368 336 -416
    WIRE 160 -352 160 -416
    WIRE 400 -352 400 -416
    WIRE 512 -288 512 -416
    WIRE 624 -288 624 -416
    WIRE -96 -272 -96 -304
    WIRE -96 -272 -192 -272
    WIRE -96 -240 -96 -272
    WIRE 48 -240 48 -288
    WIRE 160 -240 160 -288
    WIRE 336 -240 336 -288
    WIRE 400 -240 400 -288
    WIRE -192 -176 -192 -272
    WIRE -224 -128 -256 -128
    WIRE -96 -128 -96 -160
    WIRE -96 -128 -128 -128
    WIRE -80 -128 -96 -128
    WIRE 144 -128 -80 -128
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    WIRE 352 -128 288 -128
    WIRE 512 -128 512 -224
    WIRE 512 -128 432 -128
    WIRE -256 -48 -256 -128
    WIRE -208 -48 -256 -48
    WIRE -80 -48 -80 -128
    WIRE -80 -48 -128 -48
    WIRE 288 -16 288 -128
    WIRE 288 -16 64 -16
    WIRE 352 -16 288 -16
    WIRE 512 -16 512 -128
    WIRE 512 -16 432 -16
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    WIRE -176 96 -240 96
    WIRE 64 96 64 -16
    WIRE 112 96 64 96
    WIRE 512 96 512 -16
    WIRE 512 96 272 96
    WIRE -32 128 -96 128
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    WIRE 656 144 624 144
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    WIRE 112 160 64 160
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    WIRE 752 176 752 144
    WIRE 144 224 144 208
    WIRE -32 256 -32 224
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    WIRE 384 560 320 560
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    WIRE 624 560 384 560
    WIRE -96 576 -96 416
    WIRE -48 576 -96 576
    WIRE 32 576 -48 576
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    WIRE 144 576 112 576
    WIRE 208 576 144 576
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    WIRE -320 592 -320 496
    WIRE -240 592 -320 592
    WIRE -176 592 -176 496
    WIRE -176 592 -240 592
    WIRE 432 592 320 592
    WIRE 512 592 512 512
    WIRE 512 592 432 592
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    WIRE 704 592 624 592
    WIRE -96 624 -96 576
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    WIRE 512 624 512 592
    WIRE 704 624 704 592
    WIRE 432 640 432 592
    WIRE 624 640 624 592
    WIRE -96 736 -96 688
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    WIRE 512 736 432 736
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    WIRE 624 736 512 736
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    WIRE 704 736 624 736
    WIRE -96 768 -96 736
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    FLAG -400 336 0
    FLAG 288 528 V+
    FLAG 144 224 V-
    FLAG -240 96 V+
    FLAG -240 592 V-
    FLAG 880 288 output
    FLAG 144 32 V+
    FLAG 288 624 V-
    FLAG 432 768 0
    FLAG -32 256 0
    FLAG -32 -480 V+
    FLAG -32 -384 V-
    FLAG -256 0 0
    FLAG 400 -240 0
    FLAG 160 -240 0
    FLAG 64 416 0
    FLAG 336 -240 0
    FLAG -96 768 0
    FLAG 208 576 dc-trim
    FLAG 640 -512 0
    FLAG 48 -240 0
    FLAG 928 432 0
    SYMBOL voltage -320 128 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL res 496 256 R90
    WINDOW 0 1 52 VBottom 2
    WINDOW 3 33 45 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 10.5k
    SYMBOL cap 352 256 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 35 30 VTop 2
    SYMATTR InstName C8
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL res 240 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 448 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL njf -128 -176 R90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -320 400 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V2
    SYMATTR Value 6
    SYMBOL res 48 272 R0
    WINDOW 3 36 65 Left 2
    SYMATTR Value 10.5k
    SYMATTR InstName R10
    SYMBOL schottky 496 -288 R0
    WINDOW 3 -17 -26 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -112 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 82
    SYMBOL OpAmps\\LT1994 176 128 R0
    WINDOW 3 10 -65 Left 2
    WINDOW 0 11 -95 Left 2
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1057 288 512 M0
    WINDOW 0 19 104 Left 2
    WINDOW 3 18 130 Left 2
    SYMATTR InstName U3
    SYMBOL schottky 528 448 M0
    WINDOW 3 52 -26 VRight 2
    WINDOW 0 -18 3 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D3
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL schottky 640 448 M0
    WINDOW 3 49 -26 VRight 2
    WINDOW 0 -21 4 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D4
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 528 608 M0
    WINDOW 3 25 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R16
    SYMBOL res 720 608 M0
    WINDOW 3 27 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R17
    SYMBOL res -112 -256 R0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 320 -384 R0
    WINDOW 0 -50 69 Left 2
    WINDOW 3 -54 98 Left 2
    SYMATTR InstName R13
    SYMATTR Value 220k
    SYMBOL res 448 -32 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 1.0469Meg
    SYMBOL res -80 -288 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res -80 432 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 33k
    SYMBOL res 176 416 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R15
    SYMATTR Value 220
    SYMBOL res 16 560 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 10k
    SYMBOL cap 176 352 R180
    WINDOW 0 -37 41 Left 2
    WINDOW 3 -50 13 Left 2
    SYMATTR InstName C7
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL cap 720 128 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 100000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
    SYMBOL res 736 160 R0
    SYMATTR InstName R18
    SYMATTR Value 600
    SYMBOL res 192 -400 R270
    WINDOW 0 35 55 VTop 2
    WINDOW 3 -6 55 VBottom 2
    SYMATTR InstName R12
    SYMATTR Value 220k
    SYMBOL cap 176 -352 M0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 48 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 -352 M0
    WINDOW 0 -32 51 Left 2
    WINDOW 3 -72 7 Left 2
    SYMATTR InstName C10
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 368 448 M270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C9
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 640 R0
    WINDOW 0 -37 6 Left 2
    WINDOW 3 -77 53 Left 2
    SYMATTR InstName C11
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 608 640 R0
    WINDOW 0 -33 9 Left 2
    WINDOW 3 -72 51 Left 2
    SYMATTR InstName C12
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 160 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -79 48 Left 2
    SYMATTR InstName C1
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 432 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 50 Left 2
    SYMATTR InstName C2
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -16 224 R180
    WINDOW 0 23 78 Left 2
    WINDOW 3 -74 78 Left 2
    SYMATTR InstName C4
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL diode -80 688 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL cap -64 688 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM032R60J105ME05" type="X5R"
    SYMBOL OpAmps\\LT1678 -32 -432 M0
    WINDOW 0 -47 50 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2
    SYMBOL diode 192 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D6
    SYMATTR Value 1N914
    SYMBOL diode 272 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D7
    SYMATTR Value 1N914
    SYMBOL diode 352 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D8
    SYMATTR Value 1N914
    SYMBOL diode 432 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D9
    SYMATTR Value 1N914
    SYMBOL diode 512 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D10
    SYMATTR Value 1N914
    SYMBOL schottky 608 -288 R0
    SYMATTR Value BAS40HY
    SYMATTR InstName D2
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -80 -560 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 32 -384 R0
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL diode 592 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D11
    SYMATTR Value 1N914
    SYMBOL res 912 304 R0
    SYMATTR InstName R19
    SYMATTR Value 600
    TEXT -624 272 Left 2 !.tran 0 150s 0s startup



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to All on Sun Nov 10 18:00:01 2024
    On Sun, 10 Nov 2024 17:45:00 +0000, Cursitor Doom <cd@notformail.com>
    wrote:

    On Sun, 10 Nov 2024 12:12:34 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers. >>>>This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place,

    Change R9 to 1.07Meg does it amplitude stabilize now?
    Adjustment will be needed in any real circuit.

    Indeed, but for a simulation we should be seeing identical results!
    I've made the change as you suggested and it's increased the sim time >considerably. I'll post again when it's completed.

    Update: looking *much* better at 25% done. Settled after 7.5s. I will
    let it run its course anyway and post again at the end with the final
    outcome.




    even if the sim is left to run its
    full course. Also, what's the purpose of the 6 diodes in series at the
    top of the schematic? If you need to drop 4V there ought to be a more
    elegant way of doing it!



    There are two things I don't understand about my own circuit.

    1. Why does LT1678 work fine in position U2 but LT1057 does not.
    2. Why is the DC stabilization circuit (U3 and associated components) needed and would it work just the same in reality?

    Version 4
    SHEET 1 2196 932
    WIRE -64 -576 -96 -576
    WIRE 48 -576 16 -576
    WIRE 128 -528 112 -528
    WIRE 208 -528 192 -528
    WIRE 288 -528 272 -528
    WIRE 368 -528 352 -528
    WIRE 448 -528 432 -528
    WIRE 528 -528 512 -528
    WIRE 640 -528 592 -528
    WIRE 640 -512 640 -528
    WIRE -32 -464 -32 -480
    WIRE 48 -448 48 -576
    WIRE 48 -448 0 -448
    WIRE -96 -432 -96 -576
    WIRE -64 -432 -96 -432
    WIRE 112 -416 112 -528
    WIRE 112 -416 0 -416
    WIRE 160 -416 112 -416
    WIRE 208 -416 160 -416
    WIRE 336 -416 288 -416
    WIRE 400 -416 336 -416
    WIRE 512 -416 400 -416
    WIRE 624 -416 512 -416
    WIRE -96 -384 -96 -432
    WIRE -32 -384 -32 -400
    WIRE 48 -368 48 -448
    WIRE 336 -368 336 -416
    WIRE 160 -352 160 -416
    WIRE 400 -352 400 -416
    WIRE 512 -288 512 -416
    WIRE 624 -288 624 -416
    WIRE -96 -272 -96 -304
    WIRE -96 -272 -192 -272
    WIRE -96 -240 -96 -272
    WIRE 48 -240 48 -288
    WIRE 160 -240 160 -288
    WIRE 336 -240 336 -288
    WIRE 400 -240 400 -288
    WIRE -192 -176 -192 -272
    WIRE -224 -128 -256 -128
    WIRE -96 -128 -96 -160
    WIRE -96 -128 -128 -128
    WIRE -80 -128 -96 -128
    WIRE 144 -128 -80 -128
    WIRE 288 -128 224 -128
    WIRE 352 -128 288 -128
    WIRE 512 -128 512 -224
    WIRE 512 -128 432 -128
    WIRE -256 -48 -256 -128
    WIRE -208 -48 -256 -48
    WIRE -80 -48 -80 -128
    WIRE -80 -48 -128 -48
    WIRE 288 -16 288 -128
    WIRE 288 -16 64 -16
    WIRE 352 -16 288 -16
    WIRE 512 -16 512 -128
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    WIRE -256 0 -256 -48
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    WIRE -240 96 -320 96
    WIRE -176 96 -240 96
    WIRE 64 96 64 -16
    WIRE 112 96 64 96
    WIRE 512 96 512 -16
    WIRE 512 96 272 96
    WIRE -32 128 -96 128
    WIRE 112 128 -32 128
    WIRE -320 144 -320 96
    WIRE 624 144 624 -224
    WIRE 656 144 624 144
    WIRE 752 144 720 144
    WIRE -176 160 -176 96
    WIRE -32 160 -32 128
    WIRE 112 160 64 160
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    WIRE 752 176 752 144
    WIRE 144 224 144 208
    WIRE -32 256 -32 224
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    WIRE 512 272 512 96
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    WIRE 928 288 880 288
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    WIRE -320 320 -400 320
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    WIRE 384 560 320 560
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    WIRE 624 560 384 560
    WIRE -96 576 -96 416
    WIRE -48 576 -96 576
    WIRE 32 576 -48 576
    WIRE 144 576 144 432
    WIRE 144 576 112 576
    WIRE 208 576 144 576
    WIRE 256 576 208 576
    WIRE -320 592 -320 496
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    WIRE -176 592 -176 496
    WIRE -176 592 -240 592
    WIRE 432 592 320 592
    WIRE 512 592 512 512
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    WIRE 624 640 624 592
    WIRE -96 736 -96 688
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    WIRE -48 736 -96 736
    WIRE 432 736 432 704
    WIRE 512 736 512 704
    WIRE 512 736 432 736
    WIRE 624 736 624 704
    WIRE 624 736 512 736
    WIRE 704 736 704 704
    WIRE 704 736 624 736
    WIRE -96 768 -96 736
    WIRE 432 768 432 736
    FLAG -400 336 0
    FLAG 288 528 V+
    FLAG 144 224 V-
    FLAG -240 96 V+
    FLAG -240 592 V-
    FLAG 880 288 output
    FLAG 144 32 V+
    FLAG 288 624 V-
    FLAG 432 768 0
    FLAG -32 256 0
    FLAG -32 -480 V+
    FLAG -32 -384 V-
    FLAG -256 0 0
    FLAG 400 -240 0
    FLAG 160 -240 0
    FLAG 64 416 0
    FLAG 336 -240 0
    FLAG -96 768 0
    FLAG 208 576 dc-trim
    FLAG 640 -512 0
    FLAG 48 -240 0
    FLAG 928 432 0
    SYMBOL voltage -320 128 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL res 496 256 R90
    WINDOW 0 1 52 VBottom 2
    WINDOW 3 33 45 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 10.5k
    SYMBOL cap 352 256 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 35 30 VTop 2
    SYMATTR InstName C8
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL res 240 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 448 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL njf -128 -176 R90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -320 400 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V2
    SYMATTR Value 6
    SYMBOL res 48 272 R0
    WINDOW 3 36 65 Left 2
    SYMATTR Value 10.5k
    SYMATTR InstName R10
    SYMBOL schottky 496 -288 R0
    WINDOW 3 -17 -26 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -112 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 82
    SYMBOL OpAmps\\LT1994 176 128 R0
    WINDOW 3 10 -65 Left 2
    WINDOW 0 11 -95 Left 2
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1057 288 512 M0
    WINDOW 0 19 104 Left 2
    WINDOW 3 18 130 Left 2
    SYMATTR InstName U3
    SYMBOL schottky 528 448 M0
    WINDOW 3 52 -26 VRight 2
    WINDOW 0 -18 3 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D3
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL schottky 640 448 M0
    WINDOW 3 49 -26 VRight 2
    WINDOW 0 -21 4 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D4
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 528 608 M0
    WINDOW 3 25 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R16
    SYMBOL res 720 608 M0
    WINDOW 3 27 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R17
    SYMBOL res -112 -256 R0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 320 -384 R0
    WINDOW 0 -50 69 Left 2
    WINDOW 3 -54 98 Left 2
    SYMATTR InstName R13
    SYMATTR Value 220k
    SYMBOL res 448 -32 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 1.0469Meg
    SYMBOL res -80 -288 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res -80 432 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 33k
    SYMBOL res 176 416 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R15
    SYMATTR Value 220
    SYMBOL res 16 560 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 10k
    SYMBOL cap 176 352 R180
    WINDOW 0 -37 41 Left 2
    WINDOW 3 -50 13 Left 2
    SYMATTR InstName C7
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL cap 720 128 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 100000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
    SYMBOL res 736 160 R0
    SYMATTR InstName R18
    SYMATTR Value 600
    SYMBOL res 192 -400 R270
    WINDOW 0 35 55 VTop 2
    WINDOW 3 -6 55 VBottom 2
    SYMATTR InstName R12
    SYMATTR Value 220k
    SYMBOL cap 176 -352 M0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 48 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 -352 M0
    WINDOW 0 -32 51 Left 2
    WINDOW 3 -72 7 Left 2
    SYMATTR InstName C10
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 368 448 M270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C9
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 640 R0
    WINDOW 0 -37 6 Left 2
    WINDOW 3 -77 53 Left 2
    SYMATTR InstName C11
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 608 640 R0
    WINDOW 0 -33 9 Left 2
    WINDOW 3 -72 51 Left 2
    SYMATTR InstName C12
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 160 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -79 48 Left 2
    SYMATTR InstName C1
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 432 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 50 Left 2
    SYMATTR InstName C2
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -16 224 R180
    WINDOW 0 23 78 Left 2
    WINDOW 3 -74 78 Left 2
    SYMATTR InstName C4
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL diode -80 688 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL cap -64 688 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM032R60J105ME05" type="X5R"
    SYMBOL OpAmps\\LT1678 -32 -432 M0
    WINDOW 0 -47 50 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2
    SYMBOL diode 192 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D6
    SYMATTR Value 1N914
    SYMBOL diode 272 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D7
    SYMATTR Value 1N914
    SYMBOL diode 352 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D8
    SYMATTR Value 1N914
    SYMBOL diode 432 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D9
    SYMATTR Value 1N914
    SYMBOL diode 512 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D10
    SYMATTR Value 1N914
    SYMBOL schottky 608 -288 R0
    SYMATTR Value BAS40HY
    SYMATTR InstName D2
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -80 -560 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 32 -384 R0
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL diode 592 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D11
    SYMATTR Value 1N914
    SYMBOL res 912 304 R0
    SYMATTR InstName R19
    SYMATTR Value 600
    TEXT -624 272 Left 2 !.tran 0 150s 0s startup



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to All on Sun Nov 10 21:31:31 2024
    On Sun, 10 Nov 2024 18:00:01 +0000, Cursitor Doom <cd@notformail.com>
    wrote:

    On Sun, 10 Nov 2024 17:45:00 +0000, Cursitor Doom <cd@notformail.com>
    wrote:

    On Sun, 10 Nov 2024 12:12:34 -0500, "Edward Rawde" >><invalid@invalid.invalid> wrote:

    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers. >>>>>This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place,

    Change R9 to 1.07Meg does it amplitude stabilize now?
    Adjustment will be needed in any real circuit.

    Indeed, but for a simulation we should be seeing identical results!
    I've made the change as you suggested and it's increased the sim time >>considerably. I'll post again when it's completed.

    Update: looking *much* better at 25% done. Settled after 7.5s. I will
    let it run its course anyway and post again at the end with the final >outcome.

    Looks really stable now; 4.5V peak to peak and none of the
    fluctuations of the earlier simulations. Weird how it took *so* much
    longer to complete this time, though.






    even if the sim is left to run its
    full course. Also, what's the purpose of the 6 diodes in series at the >>>> top of the schematic? If you need to drop 4V there ought to be a more
    elegant way of doing it!



    There are two things I don't understand about my own circuit.

    1. Why does LT1678 work fine in position U2 but LT1057 does not.
    2. Why is the DC stabilization circuit (U3 and associated components) needed and would it work just the same in reality?

    Version 4
    SHEET 1 2196 932
    WIRE -64 -576 -96 -576
    WIRE 48 -576 16 -576
    WIRE 128 -528 112 -528
    WIRE 208 -528 192 -528
    WIRE 288 -528 272 -528
    WIRE 368 -528 352 -528
    WIRE 448 -528 432 -528
    WIRE 528 -528 512 -528
    WIRE 640 -528 592 -528
    WIRE 640 -512 640 -528
    WIRE -32 -464 -32 -480
    WIRE 48 -448 48 -576
    WIRE 48 -448 0 -448
    WIRE -96 -432 -96 -576
    WIRE -64 -432 -96 -432
    WIRE 112 -416 112 -528
    WIRE 112 -416 0 -416
    WIRE 160 -416 112 -416
    WIRE 208 -416 160 -416
    WIRE 336 -416 288 -416
    WIRE 400 -416 336 -416
    WIRE 512 -416 400 -416
    WIRE 624 -416 512 -416
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    WIRE -32 -384 -32 -400
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    WIRE 336 -368 336 -416
    WIRE 160 -352 160 -416
    WIRE 400 -352 400 -416
    WIRE 512 -288 512 -416
    WIRE 624 -288 624 -416
    WIRE -96 -272 -96 -304
    WIRE -96 -272 -192 -272
    WIRE -96 -240 -96 -272
    WIRE 48 -240 48 -288
    WIRE 160 -240 160 -288
    WIRE 336 -240 336 -288
    WIRE 400 -240 400 -288
    WIRE -192 -176 -192 -272
    WIRE -224 -128 -256 -128
    WIRE -96 -128 -96 -160
    WIRE -96 -128 -128 -128
    WIRE -80 -128 -96 -128
    WIRE 144 -128 -80 -128
    WIRE 288 -128 224 -128
    WIRE 352 -128 288 -128
    WIRE 512 -128 512 -224
    WIRE 512 -128 432 -128
    WIRE -256 -48 -256 -128
    WIRE -208 -48 -256 -48
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    WIRE -80 -48 -128 -48
    WIRE 288 -16 288 -128
    WIRE 288 -16 64 -16
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    WIRE -176 96 -240 96
    WIRE 64 96 64 -16
    WIRE 112 96 64 96
    WIRE 512 96 512 -16
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    WIRE -32 128 -96 128
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    WIRE 160 272 64 272
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    WIRE 400 272 352 272
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    WIRE 512 624 512 592
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    WIRE 432 640 432 592
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    WIRE 624 736 624 704
    WIRE 624 736 512 736
    WIRE 704 736 704 704
    WIRE 704 736 624 736
    WIRE -96 768 -96 736
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    FLAG -400 336 0
    FLAG 288 528 V+
    FLAG 144 224 V-
    FLAG -240 96 V+
    FLAG -240 592 V-
    FLAG 880 288 output
    FLAG 144 32 V+
    FLAG 288 624 V-
    FLAG 432 768 0
    FLAG -32 256 0
    FLAG -32 -480 V+
    FLAG -32 -384 V-
    FLAG -256 0 0
    FLAG 400 -240 0
    FLAG 160 -240 0
    FLAG 64 416 0
    FLAG 336 -240 0
    FLAG -96 768 0
    FLAG 208 576 dc-trim
    FLAG 640 -512 0
    FLAG 48 -240 0
    FLAG 928 432 0
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    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL res 496 256 R90
    WINDOW 0 1 52 VBottom 2
    WINDOW 3 33 45 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 10.5k
    SYMBOL cap 352 256 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 35 30 VTop 2
    SYMATTR InstName C8
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL res 240 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
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    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL njf -128 -176 R90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -320 400 R0
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    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
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    SYMATTR Value 6
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    SYMATTR InstName R10
    SYMBOL schottky 496 -288 R0
    WINDOW 3 -17 -26 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -112 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
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    SYMATTR Value 82
    SYMBOL OpAmps\\LT1994 176 128 R0
    WINDOW 3 10 -65 Left 2
    WINDOW 0 11 -95 Left 2
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1057 288 512 M0
    WINDOW 0 19 104 Left 2
    WINDOW 3 18 130 Left 2
    SYMATTR InstName U3
    SYMBOL schottky 528 448 M0
    WINDOW 3 52 -26 VRight 2
    WINDOW 0 -18 3 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D3
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL schottky 640 448 M0
    WINDOW 3 49 -26 VRight 2
    WINDOW 0 -21 4 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D4
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 528 608 M0
    WINDOW 3 25 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R16
    SYMBOL res 720 608 M0
    WINDOW 3 27 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R17
    SYMBOL res -112 -256 R0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 320 -384 R0
    WINDOW 0 -50 69 Left 2
    WINDOW 3 -54 98 Left 2
    SYMATTR InstName R13
    SYMATTR Value 220k
    SYMBOL res 448 -32 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 1.0469Meg
    SYMBOL res -80 -288 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res -80 432 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 33k
    SYMBOL res 176 416 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R15
    SYMATTR Value 220
    SYMBOL res 16 560 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 10k
    SYMBOL cap 176 352 R180
    WINDOW 0 -37 41 Left 2
    WINDOW 3 -50 13 Left 2
    SYMATTR InstName C7
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL cap 720 128 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 100000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
    SYMBOL res 736 160 R0
    SYMATTR InstName R18
    SYMATTR Value 600
    SYMBOL res 192 -400 R270
    WINDOW 0 35 55 VTop 2
    WINDOW 3 -6 55 VBottom 2
    SYMATTR InstName R12
    SYMATTR Value 220k
    SYMBOL cap 176 -352 M0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 48 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 -352 M0
    WINDOW 0 -32 51 Left 2
    WINDOW 3 -72 7 Left 2
    SYMATTR InstName C10
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 368 448 M270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C9
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 640 R0
    WINDOW 0 -37 6 Left 2
    WINDOW 3 -77 53 Left 2
    SYMATTR InstName C11
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 608 640 R0
    WINDOW 0 -33 9 Left 2
    WINDOW 3 -72 51 Left 2
    SYMATTR InstName C12
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 160 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -79 48 Left 2
    SYMATTR InstName C1
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -192 432 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 50 Left 2
    SYMATTR InstName C2
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -16 224 R180
    WINDOW 0 23 78 Left 2
    WINDOW 3 -74 78 Left 2
    SYMATTR InstName C4
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL diode -80 688 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL cap -64 688 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM032R60J105ME05" type="X5R"
    SYMBOL OpAmps\\LT1678 -32 -432 M0
    WINDOW 0 -47 50 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2
    SYMBOL diode 192 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D6
    SYMATTR Value 1N914
    SYMBOL diode 272 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D7
    SYMATTR Value 1N914
    SYMBOL diode 352 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D8
    SYMATTR Value 1N914
    SYMBOL diode 432 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D9
    SYMATTR Value 1N914
    SYMBOL diode 512 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D10
    SYMATTR Value 1N914
    SYMBOL schottky 608 -288 R0
    SYMATTR Value BAS40HY
    SYMATTR InstName D2
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -80 -560 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 32 -384 R0
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL diode 592 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D11
    SYMATTR Value 1N914
    SYMBOL res 912 304 R0
    SYMATTR InstName R19
    SYMATTR Value 600
    TEXT -624 272 Left 2 !.tran 0 150s 0s startup



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Cursitor Doom on Sun Nov 10 17:21:26 2024
    "Cursitor Doom" <cd@notformail.com> wrote in message news:ee92jjllg5kudr83e8bvvbsjba754aecjs@4ax.com...
    On Sun, 10 Nov 2024 18:00:01 +0000, Cursitor Doom <cd@notformail.com>
    wrote:

    On Sun, 10 Nov 2024 17:45:00 +0000, Cursitor Doom <cd@notformail.com> >>wrote:

    On Sun, 10 Nov 2024 12:12:34 -0500, "Edward Rawde" >>><invalid@invalid.invalid> wrote:

    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers. >>>>>>This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many
    harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place,

    Change R9 to 1.07Meg does it amplitude stabilize now?
    Adjustment will be needed in any real circuit.

    Indeed, but for a simulation we should be seeing identical results!
    I've made the change as you suggested and it's increased the sim time >>>considerably. I'll post again when it's completed.

    Update: looking *much* better at 25% done. Settled after 7.5s. I will
    let it run its course anyway and post again at the end with the final >>outcome.

    Looks really stable now; 4.5V peak to peak and none of the
    fluctuations of the earlier simulations. Weird how it took *so* much
    longer to complete this time, though.

    An FFT on the last 10 seconds should show peformance approaching 90dB down.

    I likely won't be working on this any further unless anyone else wants further discussion.

    The goal was to get the purest possible sine wave at the lowest cost and in simulation I don't think I can improve on this circuit.
    I'm not able to build this circuit and even if I did I don't have equipment capable of measuring distortion 90dB down.

    I'd still like to know why LT1057 doesn't work in position U2. It's not like rail to rail is needed.
    LT1678 works exactly as expected. LT1057 probably would in reality but not sure I'd risk it.

    I'd also like to know exactly how and why U3 stabilizes U1 and the operation of D1 and D2.
    Would this work the same in reality?

    The diode clamp should probably be made from a single diode and another op amp with two resistors to allow the clamp level to be
    easily adjusted.

    If it's ever buil for real I'd make R1, R2, R7, R8 easily changeable.
    I'd also make R3 220 ohm ten turn and R9 1Meg 10 turn in series with 470k.

    The definitely final circuit is included below.
    This has no text or titles or dates so add that yourself if you wish.

    Version 4
    SHEET 1 2196 932
    WIRE -64 -576 -96 -576
    WIRE 48 -576 16 -576
    WIRE 128 -528 112 -528
    WIRE 208 -528 192 -528
    WIRE 288 -528 272 -528
    WIRE 368 -528 352 -528
    WIRE 448 -528 432 -528
    WIRE 528 -528 512 -528
    WIRE 640 -528 592 -528
    WIRE 640 -512 640 -528
    WIRE -32 -464 -32 -480
    WIRE 48 -448 48 -576
    WIRE 48 -448 0 -448
    WIRE -96 -432 -96 -576
    WIRE -64 -432 -96 -432
    WIRE 112 -416 112 -528
    WIRE 112 -416 0 -416
    WIRE 160 -416 112 -416
    WIRE 208 -416 160 -416
    WIRE 336 -416 288 -416
    WIRE 400 -416 336 -416
    WIRE 512 -416 400 -416
    WIRE 624 -416 512 -416
    WIRE -96 -384 -96 -432
    WIRE -32 -384 -32 -400
    WIRE 48 -368 48 -448
    WIRE 336 -368 336 -416
    WIRE 160 -352 160 -416
    WIRE 400 -352 400 -416
    WIRE 512 -288 512 -416
    WIRE 624 -288 624 -416
    WIRE -96 -272 -96 -304
    WIRE -96 -272 -192 -272
    WIRE -96 -240 -96 -272
    WIRE 48 -240 48 -288
    WIRE 160 -240 160 -288
    WIRE 336 -240 336 -288
    WIRE 400 -240 400 -288
    WIRE -192 -176 -192 -272
    WIRE -224 -128 -256 -128
    WIRE -96 -128 -96 -160
    WIRE -96 -128 -128 -128
    WIRE -80 -128 -96 -128
    WIRE 144 -128 -80 -128
    WIRE 288 -128 224 -128
    WIRE 352 -128 288 -128
    WIRE 512 -128 512 -224
    WIRE 512 -128 432 -128
    WIRE -256 -48 -256 -128
    WIRE -208 -48 -256 -48
    WIRE -80 -48 -80 -128
    WIRE -80 -48 -128 -48
    WIRE 288 -16 288 -128
    WIRE 288 -16 64 -16
    WIRE 352 -16 288 -16
    WIRE 512 -16 512 -128
    WIRE 512 -16 432 -16
    WIRE -256 0 -256 -48
    WIRE 144 48 144 32
    WIRE -272 96 -352 96
    WIRE -208 96 -272 96
    WIRE 64 96 64 -16
    WIRE 112 96 64 96
    WIRE 512 96 512 -16
    WIRE 512 96 272 96
    WIRE -32 128 -96 128
    WIRE 112 128 -32 128
    WIRE -352 144 -352 96
    WIRE 624 144 624 -224
    WIRE 656 144 624 144
    WIRE 752 144 720 144
    WIRE -208 160 -208 96
    WIRE -32 160 -32 128
    WIRE 112 160 64 160
    WIRE 624 160 624 144
    WIRE 624 160 272 160
    WIRE 752 176 752 144
    WIRE 144 224 144 208
    WIRE -32 256 -32 224
    WIRE 64 272 64 160
    WIRE 160 272 64 272
    WIRE 288 272 160 272
    WIRE 400 272 352 272
    WIRE 512 272 512 96
    WIRE 512 272 480 272
    WIRE 64 288 64 272
    WIRE 160 288 160 272
    WIRE 752 288 752 256
    WIRE 880 288 752 288
    WIRE 928 288 880 288
    WIRE -352 320 -352 224
    WIRE -352 320 -432 320
    WIRE 928 320 928 288
    WIRE -432 336 -432 320
    WIRE -352 336 -352 320
    WIRE -208 336 -208 224
    WIRE -208 336 -352 336
    WIRE -96 336 -96 128
    WIRE 64 384 64 368
    WIRE 160 384 160 352
    WIRE 160 384 64 384
    WIRE -352 416 -352 336
    WIRE 64 416 64 384
    WIRE -208 432 -208 336
    WIRE 192 432 144 432
    WIRE 304 432 272 432
    WIRE 384 432 368 432
    WIRE 928 432 928 400
    WIRE 512 448 512 272
    WIRE 624 448 624 160
    WIRE 288 544 288 528
    WIRE 384 560 384 432
    WIRE 384 560 320 560
    WIRE 624 560 624 512
    WIRE 624 560 384 560
    WIRE -96 576 -96 416
    WIRE -48 576 -96 576
    WIRE 32 576 -48 576
    WIRE 144 576 144 432
    WIRE 144 576 112 576
    WIRE 208 576 144 576
    WIRE 256 576 208 576
    WIRE -352 592 -352 496
    WIRE -272 592 -352 592
    WIRE -208 592 -208 496
    WIRE -208 592 -272 592
    WIRE 432 592 320 592
    WIRE 512 592 512 512
    WIRE 512 592 432 592
    WIRE 624 592 624 560
    WIRE 704 592 624 592
    WIRE -96 624 -96 576
    WIRE -48 624 -48 576
    WIRE 288 624 288 608
    WIRE 512 624 512 592
    WIRE 704 624 704 592
    WIRE 432 640 432 592
    WIRE 624 640 624 592
    WIRE -96 736 -96 688
    WIRE -48 736 -48 688
    WIRE -48 736 -96 736
    WIRE 432 736 432 704
    WIRE 512 736 512 704
    WIRE 512 736 432 736
    WIRE 624 736 624 704
    WIRE 624 736 512 736
    WIRE 704 736 704 704
    WIRE 704 736 624 736
    WIRE -96 768 -96 736
    WIRE 432 768 432 736
    FLAG -432 336 0
    FLAG 288 528 V+
    FLAG 144 224 V-
    FLAG -272 96 V+
    FLAG -272 592 V-
    FLAG 880 288 output
    FLAG 144 32 V+
    FLAG 288 624 V-
    FLAG 432 768 0
    FLAG -32 256 0
    FLAG -32 -480 V+
    FLAG -32 -384 V-
    FLAG -256 0 0
    FLAG 400 -240 0
    FLAG 160 -240 0
    FLAG 64 416 0
    FLAG 336 -240 0
    FLAG -96 768 0
    FLAG 208 576 dc-trim
    FLAG 640 -512 0
    FLAG 48 -240 0
    FLAG 928 432 0
    SYMBOL voltage -352 128 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL res 496 256 R90
    WINDOW 0 1 52 VBottom 2
    WINDOW 3 33 45 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 10.5k
    SYMBOL cap 352 256 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 35 30 VTop 2
    SYMATTR InstName C8
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL res 240 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 448 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL njf -128 -176 R90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -352 400 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V2
    SYMATTR Value 6
    SYMBOL res 48 272 R0
    WINDOW 3 36 65 Left 2
    SYMATTR Value 10.5k
    SYMATTR InstName R10
    SYMBOL schottky 496 -288 R0
    WINDOW 3 -17 -26 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -112 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 82
    SYMBOL OpAmps\\LT1994 176 128 R0
    WINDOW 3 10 -65 Left 2
    WINDOW 0 11 -95 Left 2
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1057 288 512 M0
    WINDOW 0 19 104 Left 2
    WINDOW 3 18 130 Left 2
    SYMATTR InstName U3
    SYMBOL schottky 528 448 M0
    WINDOW 3 52 -26 VRight 2
    WINDOW 0 -18 3 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D3
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL schottky 640 448 M0
    WINDOW 3 49 -26 VRight 2
    WINDOW 0 -21 4 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D4
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 528 608 M0
    WINDOW 3 25 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R16
    SYMBOL res 720 608 M0
    WINDOW 3 27 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R17
    SYMBOL res -112 -256 R0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 320 -384 R0
    WINDOW 0 -50 69 Left 2
    WINDOW 3 -54 98 Left 2
    SYMATTR InstName R13
    SYMATTR Value 220k
    SYMBOL res 448 -32 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 1.07Meg
    SYMBOL res -80 -288 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res -80 432 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 33k
    SYMBOL res 176 416 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R15
    SYMATTR Value 220
    SYMBOL res 16 560 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 10k
    SYMBOL cap 176 352 R180
    WINDOW 0 -37 41 Left 2
    WINDOW 3 -50 13 Left 2
    SYMATTR InstName C7
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL cap 720 128 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 100000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
    SYMBOL res 736 160 R0
    SYMATTR InstName R18
    SYMATTR Value 600
    SYMBOL res 192 -400 R270
    WINDOW 0 35 55 VTop 2
    WINDOW 3 -6 55 VBottom 2
    SYMATTR InstName R12
    SYMATTR Value 220k
    SYMBOL cap 176 -352 M0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 48 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 -352 M0
    WINDOW 0 -32 51 Left 2
    WINDOW 3 -72 7 Left 2
    SYMATTR InstName C10
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 368 448 M270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C9
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 640 R0
    WINDOW 0 -37 6 Left 2
    WINDOW 3 -77 53 Left 2
    SYMATTR InstName C11
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 608 640 R0
    WINDOW 0 -33 9 Left 2
    WINDOW 3 -72 51 Left 2
    SYMATTR InstName C12
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -224 160 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -79 48 Left 2
    SYMATTR InstName C1
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -224 432 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 50 Left 2
    SYMATTR InstName C2
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -16 224 R180
    WINDOW 0 23 78 Left 2
    WINDOW 3 -74 78 Left 2
    SYMATTR InstName C4
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL diode -80 688 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL cap -64 688 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM032R60J105ME05" type="X5R"
    SYMBOL OpAmps\\LT1678 -32 -432 M0
    WINDOW 0 -47 50 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2
    SYMBOL diode 192 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D6
    SYMATTR Value 1N914
    SYMBOL diode 272 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D7
    SYMATTR Value 1N914
    SYMBOL diode 352 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D8
    SYMATTR Value 1N914
    SYMBOL diode 432 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D9
    SYMATTR Value 1N914
    SYMBOL diode 512 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D10
    SYMATTR Value 1N914
    SYMBOL schottky 608 -288 R0
    WINDOW 3 -16 -25 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D2
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -80 -560 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 32 -384 R0
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL diode 592 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D11
    SYMATTR Value 1N914
    SYMBOL res 912 304 R0
    SYMATTR InstName R19
    SYMATTR Value 600
    TEXT -448 632 Left 2 !.tran 0 150s 0s startup

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to invalid@invalid.invalid on Mon Nov 11 00:04:53 2024
    On Sun, 10 Nov 2024 19:01:31 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vgrbl7$30bo$1@nnrp.usenet.blueworldhosting.com...
    "Cursitor Doom" <cd@notformail.com> wrote in message news:ee92jjllg5kudr83e8bvvbsjba754aecjs@4ax.com...
    On Sun, 10 Nov 2024 18:00:01 +0000, Cursitor Doom <cd@notformail.com>
    wrote:

    On Sun, 10 Nov 2024 17:45:00 +0000, Cursitor Doom <cd@notformail.com> >>>>wrote:

    On Sun, 10 Nov 2024 12:12:34 -0500, "Edward Rawde" >>>>><invalid@invalid.invalid> wrote:

    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers. >>>>>>>>This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many
    harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place,

    Change R9 to 1.07Meg does it amplitude stabilize now?
    Adjustment will be needed in any real circuit.

    Indeed, but for a simulation we should be seeing identical results! >>>>>I've made the change as you suggested and it's increased the sim time >>>>>considerably. I'll post again when it's completed.

    Update: looking *much* better at 25% done. Settled after 7.5s. I will >>>>let it run its course anyway and post again at the end with the final >>>>outcome.

    Looks really stable now; 4.5V peak to peak and none of the
    fluctuations of the earlier simulations. Weird how it took *so* much
    longer to complete this time, though.

    An FFT on the last 10 seconds should show peformance approaching 90dB down. >>
    I likely won't be woBerking on this any further unless anyone else wants further discussion.

    The goal was to get the purest possible sine wave at the lowest cost and in simulation I don't think I can improve on this
    circuit.
    I'm not able to build this circuit and even if I did I don't have equipment capable of measuring distortion 90dB down.

    I'd still like to know why LT1057 doesn't work in position U2. It's not like rail to rail is needed.
    LT1678 works exactly as expected. LT1057 probably would in reality but not sure I'd risk it.

    To answer my own question a wild guess says that the simulation model is hard coded to keep the output 2V away from the rail.
    Seems pretty poor to me that an op amp operating on 6V can't do more than 4V out.
    I wonder what a real device would do.
    The LT1678 works because it's rail to rail.



    A good deal better than 4V I would imagine! If I had one lying around
    I would gladly try it, but I'm 99% certain I haven't.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Edward Rawde on Sun Nov 10 19:01:31 2024
    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vgrbl7$30bo$1@nnrp.usenet.blueworldhosting.com...
    "Cursitor Doom" <cd@notformail.com> wrote in message news:ee92jjllg5kudr83e8bvvbsjba754aecjs@4ax.com...
    On Sun, 10 Nov 2024 18:00:01 +0000, Cursitor Doom <cd@notformail.com>
    wrote:

    On Sun, 10 Nov 2024 17:45:00 +0000, Cursitor Doom <cd@notformail.com> >>>wrote:

    On Sun, 10 Nov 2024 12:12:34 -0500, "Edward Rawde" >>>><invalid@invalid.invalid> wrote:

    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers. >>>>>>>This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many
    harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place,

    Change R9 to 1.07Meg does it amplitude stabilize now?
    Adjustment will be needed in any real circuit.

    Indeed, but for a simulation we should be seeing identical results! >>>>I've made the change as you suggested and it's increased the sim time >>>>considerably. I'll post again when it's completed.

    Update: looking *much* better at 25% done. Settled after 7.5s. I will
    let it run its course anyway and post again at the end with the final >>>outcome.

    Looks really stable now; 4.5V peak to peak and none of the
    fluctuations of the earlier simulations. Weird how it took *so* much
    longer to complete this time, though.

    An FFT on the last 10 seconds should show peformance approaching 90dB down.

    I likely won't be working on this any further unless anyone else wants further discussion.

    The goal was to get the purest possible sine wave at the lowest cost and in simulation I don't think I can improve on this
    circuit.
    I'm not able to build this circuit and even if I did I don't have equipment capable of measuring distortion 90dB down.

    I'd still like to know why LT1057 doesn't work in position U2. It's not like rail to rail is needed.
    LT1678 works exactly as expected. LT1057 probably would in reality but not sure I'd risk it.

    To answer my own question a wild guess says that the simulation model is hard coded to keep the output 2V away from the rail.
    Seems pretty poor to me that an op amp operating on 6V can't do more than 4V out.
    I wonder what a real device would do.
    The LT1678 works because it's rail to rail.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to invalid@invalid.invalid on Mon Nov 11 15:35:10 2024
    On Sun, 10 Nov 2024 17:21:26 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Cursitor Doom" <cd@notformail.com> wrote in message news:ee92jjllg5kudr83e8bvvbsjba754aecjs@4ax.com...
    On Sun, 10 Nov 2024 18:00:01 +0000, Cursitor Doom <cd@notformail.com>
    wrote:

    On Sun, 10 Nov 2024 17:45:00 +0000, Cursitor Doom <cd@notformail.com> >>>wrote:

    On Sun, 10 Nov 2024 12:12:34 -0500, "Edward Rawde" >>>><invalid@invalid.invalid> wrote:

    "Cursitor Doom" <cd@notformail.com> wrote in message news:bs81jjt7d064jc1ktmvihgn30qkhf67taj@4ax.com...
    On Sun, 10 Nov 2024 00:49:36 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgnkgg$3p31a$1@dont-email.me...
    On 9/11/2024 7:39 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.


    I have fixed my circuit but it raises more questions than it answers. >>>>>>>This circuit deliberately has no text and no u symbols so should be ready to simulate.
    If you let it complete (about 20 minutes on a fast PC) the FFT should show at least 80dB purity and there aren't many
    harmonics
    standing in the way of 90dB.
    Startup isn't fast and it takes at least 20 seconds of simulation to fully settle.

    Spectral purity might be fine for all I can tell but the output
    amplitude is all over the place,

    Change R9 to 1.07Meg does it amplitude stabilize now?
    Adjustment will be needed in any real circuit.

    Indeed, but for a simulation we should be seeing identical results! >>>>I've made the change as you suggested and it's increased the sim time >>>>considerably. I'll post again when it's completed.

    Update: looking *much* better at 25% done. Settled after 7.5s. I will
    let it run its course anyway and post again at the end with the final >>>outcome.

    Looks really stable now; 4.5V peak to peak and none of the
    fluctuations of the earlier simulations. Weird how it took *so* much
    longer to complete this time, though.

    An FFT on the last 10 seconds should show peformance approaching 90dB down.

    I likely won't be working on this any further unless anyone else wants further discussion.

    The goal was to get the purest possible sine wave at the lowest cost and in simulation I don't think I can improve on this circuit.
    I'm not able to build this circuit and even if I did I don't have equipment capable of measuring distortion 90dB down.

    I would add that achieving shielding effectiveness of 90 dB is very
    difficult to achieve in practice, so even if it's only 80 dB,
    interference leaking in is likely to dominate in practice, even of the
    sky is quiet.

    Joe

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to All on Fri Nov 8 15:43:41 2024
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.

    If a prototype is ever built, attention to the type and quality of the capacitors used will be needed.
    Electrolytics are not intended. Put C1 and C2 near U1 supply pins.
    Also pay attention to the stability of +/- 6V.
    It would be nice to have a single 12V rail version but so far I can't get it to work.

    R1 and R2 and probably R7 should be easily changeable.
    R3 should be 220 ohm ten turn. R9 should be 1M ohm ten turn in series with 470k.

    I don't fully understand why the DC stabilization circuit through U2B achieves what it does
    and this makes me concerned about whether a real circuit would have the same behaviour.
    It was added when I noticed that the diodes D1 and D2 weren't contributing equally so I
    decided to try to derive a DC correction signal. This was originally connected to the FET source
    and then to R13. Since this is a DC correction signal I decided to try out the effect of
    connecting it to U1 Vocm and was amazed that this works as well as it does.
    If you disconnect R5, harmonics will not be more than 50dB down because D1 and D2 are no
    longer providing stable and equal contributions to the level control feedback.

    If you need even better performance then the circuit referenced by Bill Sloman can be used.
    https://www.google.com/search?q=AN132+purity
    NSL-32SR3 is not expensive and simulation models exist but LT1468 is expensive.

    Other references

    https://www.google.com/search?&q=The+field+effect+transistor+as+a+voltage+controlled+resistor

    https://www.google.com/search?&q=sine+wave+oscillator&udm=2


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    TEXT -624 272 Left 2 !.tran 0 300s 0s startup
    TEXT -1568 -728 Left 2 ;Edward Rawde's high purity 1kHz sinewave oscillator. 8 Nov 2024\n \nHarmonics are more than 80dB down in
    simulation.\nFFT the last 30 seconds.\nThere is only one harmonic stopping me claiming 90dB but the exact FFT result can depend\non
    exactly how much output is selected for the FFT. You may see different results.\n \nIf a prototype is ever built, pay attention to
    the type and quality of the capacitors used.\nElectrolytics are not intended. Put C1 and C2 near U1 supply pins.\nAlso pay attention
    to the stability of +/- 6V.\nIt would be nice to have a single 12V rail version but so far I can't get it to work.\n \nR1 and R2 and
    probably R7 should be easily changeable.\nR3 should be 220 ohm ten turn. R9 should be 1M ohm ten turn in series with 470k.\n \nI
    don't fully understand why the DC stabilization circuit through U2B achieves what it does\nand this makes me concerned about whether
    a real circuit would have the same behaviour.\nIt was added when I noticed that the diodes D1 and D2 weren't contributing equally so
    I \ndecided to try to derive a DC correction signal. This was originally connected to the FET source\nand then to R13. Since this is
    a DC correction signal I decided to try out the effect of\nconnecting it to U1 Vocm and was amazed that this works as well as it
    does. \nIf you disconnect R5, harmonics will not be more than 50dB down because D1 and D2 are no\nlonger providing stable and equal
    contributions to the level control feedback.\n \nIf you need even better performance then the circuit referenced by Bill Sloman can
    be used.\nhttps://www.google.com/search?q=AN132+purity\nNSL-32SR3 is not expensive and simulation models exist but LT1468 is
    expensive.\n \nOther references\n \nhttps://www.google.com/search?&q=The+field+effect+transistor+as+a+voltage+controlled+resistor\n
    \nhttps://www.google.com/search?&q=sine+wave+oscillator&udm=2

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Sat Nov 9 18:54:46 2024
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.

    If a prototype is ever built, attention to the type and quality of the capacitors used will be needed.
    Electrolytics are not intended. Put C1 and C2 near U1 supply pins.

    If electrolytics are not intended, why are most of the capacitors rated
    at 10V?

    When I cut and pasted the file the capacitors were mostly labelled as
    10?, 1? and - in the case of the wein bridge capacitors 0.015?

    The 15nF capacitors are rated at 16V - the polypropylene parts you can
    actually buy that are offered with a +/-1% tolerance are 63V and 250V parts

    I presume you intended u or the Greek mu symbol, and after I'd done that substitution the simulation did work, if not well.

    The feedback loop doesn't settle well, and I suspect that I know why. R4
    should probably be in series with C3, not in parallel. More later.

    --
    Bill Sloman, Sydney
    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sat Nov 9 03:39:28 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vgn4gm$3lcor$1@dont-email.me...
    On 9/11/2024 7:43 am, Edward Rawde wrote:
    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.

    If a prototype is ever built, attention to the type and quality of the capacitors used will be needed.
    Electrolytics are not intended. Put C1 and C2 near U1 supply pins.

    If electrolytics are not intended, why are most of the capacitors rated at 10V?

    Yes


    When I cut and pasted the file the capacitors were mostly labelled as 10?, 1? and - in the case of the wein bridge capacitors
    0.015?


    When I cut and pasted the file into notepad++ and removed line 391 and subsequent lines (or fixed wraps) and under encoding
    converted to ANSI everything worked fine.

    The 15nF capacitors are rated at 16V - the polypropylene parts you can actually buy that are offered with a +/-1% tolerance are
    63V and 250V parts

    You'd have to take that up with the LTSpice parts library.


    I presume you intended u or the Greek mu symbol, and after I'd done that substitution the simulation did work, if not well.

    No substitution is required if you convert to ANSI in notepad++


    The feedback loop doesn't settle well, and I suspect that I know why. R4 should probably be in series with C3, not in parallel.
    More later.

    --
    Bill Sloman, Sydney
    --
    Bill Sloman, Sydney


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to sunaecoNoChoppedPork@gmail.com on Thu Nov 14 11:14:28 2024
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.

    If a prototype is ever built, attention to the type and quality of the capacitors used will be needed.
    Electrolytics are not intended. Put C1 and C2 near U1 supply pins.
    Also pay attention to the stability of +/- 6V.
    It would be nice to have a single 12V rail version but so far I can't get it to work.

    R1 and R2 and probably R7 should be easily changeable.
    R3 should be 220 ohm ten turn. R9 should be 1M ohm ten turn in series with 470k.

    I don't fully understand why the DC stabilization circuit through U2B achieves what it does
    and this makes me concerned about whether a real circuit would have the same behaviour.
    It was added when I noticed that the diodes D1 and D2 weren't contributing equally so I
    decided to try to derive a DC correction signal. This was originally connected to the FET source
    and then to R13. Since this is a DC correction signal I decided to try out the effect of
    connecting it to U1 Vocm and was amazed that this works as well as it does. >>If you disconnect R5, harmonics will not be more than 50dB down because D1 and D2 are no
    longer providing stable and equal contributions to the level control feedback.

    If you need even better performance then the circuit referenced by Bill Sloman can be used.
    https://www.google.com/search?q=AN132+purity
    NSL-32SR3 is not expensive and simulation models exist but LT1468 is expensive.

    Other references
    https://www.google.com/search?&q=The+field+effect+transistor+as+a+voltage+controlled+resistor

    https://www.google.com/search?&q=sine+wave+oscillator&udm=2


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    TEXT -624 272 Left 2 !.tran 0 300s 0s startup
    TEXT -1568 -728 Left 2 ;Edward Rawde's high purity 1kHz sinewave oscillator. 8 Nov 2024\n \nHarmonics are more than 80dB down in
    simulation.\nFFT the last 30 seconds.\nThere is only one harmonic stopping me claiming 90dB but the exact FFT result can
    depend\non
    exactly how much output is selected for the FFT. You may see different results.\n \nIf a prototype is ever built, pay attention to
    the type and quality of the capacitors used.\nElectrolytics are not intended. Put C1 and C2 near U1 supply pins.\nAlso pay
    attention
    to the stability of +/- 6V.\nIt would be nice to have a single 12V rail version but so far I can't get it to work.\n \nR1 and R2
    and
    probably R7 should be easily changeable.\nR3 should be 220 ohm ten turn. R9 should be 1M ohm ten turn in series with 470k.\n \nI
    don't fully understand why the DC stabilization circuit through U2B achieves what it does\nand this makes me concerned about
    whether
    a real circuit would have the same behaviour.\nIt was added when I noticed that the diodes D1 and D2 weren't contributing equally
    so
    I \ndecided to try to derive a DC correction signal. This was originally connected to the FET source\nand then to R13. Since this
    is
    a DC correction signal I decided to try out the effect of\nconnecting it to U1 Vocm and was amazed that this works as well as it
    does. \nIf you disconnect R5, harmonics will not be more than 50dB down because D1 and D2 are no\nlonger providing stable and
    equal
    contributions to the level control feedback.\n \nIf you need even better performance then the circuit referenced by Bill Sloman
    can
    be used.\nhttps://www.google.com/search?q=AN132+purity\nNSL-32SR3 is not expensive and simulation models exist but LT1468 is
    expensive.\n \nOther references\n >>\nhttps://www.google.com/search?&q=The+field+effect+transistor+as+a+voltage+controlled+resistor\n
    \nhttps://www.google.com/search?&q=sine+wave+oscillator&udm=2


    Using an NSL-32SR3 doesn't really gain you anything over a FET. If
    you keep |vds| much less than |Vt-vgs| in the circuit and compensate
    for the vds/2 variation on the gate drive the distortion levels
    produced will be lower than almost all opamps out there. Here's a
    link to a sim using an LDR.

    https://1drv.ms/f/c/1af24d72a509cd48/EkjNCaVyTfIggBrrAQAAAAABHXNKs52BoVHi7zaxKmdMMQ?e=oVD0JS

    I've added some 3rd harmonic distortion to a linear model to give
    distortion figures roughly in the ballpark of Fig 6 in the attached application note (for small signal swings across the device). In the oscillator o/p the 3rd is about 150dB down. If you use the linear LDR
    model, or a FET, it will be much the same. (The opamps used in the sim actually have distortions specs of about 130dB in reallity.)

    Thanks for that. I left it overnight for 100 seconds of simulation. It looks like it has better harmonic performance than my
    circuit.
    Why use two op amps in the oscillator instead of one like my circuit?
    What happens without the initial conditions? Does it take a long time to settle?
    I'll be away until next week.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Fri Nov 15 19:56:09 2024
    On 15/11/2024 3:14 am, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I finally got around to digging out my AD734 based Wein bridge
    simulation, and created a FET based version.

    It's got a nasty 163kHz generator embedded in it somewhere, and I've put
    in an RL filter to keep that under control.

    The double Sallen and Keys network is a four pole Bessel filter which
    I'm using as a 250usec delay line - the output from the full wave
    rectifier has an appreciable 2kHz component, but the delayed
    contribution coming into the integrator through R9 roughly cancels the
    direct input through R20.

    R10 in the integrator damps the amplitude feedback loop for a dead-beat response.

    The harmonics in the 1kHz output are about 100dB below the fundamental.
    Not great, but respectable, and not worth trying to improve in a simulation.

    The circuit still works with the worst case values for the 1% capacitors
    at C5 and C6.

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    WIRE 1824 -1344 1824 -1520
    WIRE 1952 -1344 1824 -1344
    WIRE 64 -1328 64 -1520
    WIRE 160 -1328 160 -1456
    WIRE 224 -1328 160 -1328
    WIRE 368 -1328 368 -1456
    WIRE 368 -1328 288 -1328
    WIRE 1152 -1328 1152 -1504
    WIRE 1280 -1328 1152 -1328
    WIRE 2128 -1328 2128 -1408
    WIRE 2128 -1328 2016 -1328
    WIRE 1456 -1312 1456 -1504
    WIRE 1456 -1312 1344 -1312
    WIRE 1504 -1312 1456 -1312
    WIRE 1664 -1312 1664 -1552
    WIRE 1664 -1312 1584 -1312
    WIRE 1712 -1312 1664 -1312
    WIRE 1920 -1312 1792 -1312
    WIRE 1952 -1312 1920 -1312
    WIRE 864 -1296 864 -1776
    WIRE 896 -1296 864 -1296
    WIRE 992 -1296 992 -1536
    WIRE 992 -1296 976 -1296
    WIRE 1040 -1296 992 -1296
    WIRE 1248 -1296 1120 -1296
    WIRE 1280 -1296 1248 -1296
    WIRE 368 -1264 368 -1328
    WIRE -832 -1248 -832 -1376
    WIRE -704 -1248 -704 -1552
    WIRE -704 -1248 -832 -1248
    WIRE -608 -1248 -608 -1392
    WIRE -608 -1248 -704 -1248
    WIRE -496 -1248 -496 -1296
    WIRE -496 -1248 -608 -1248
    WIRE -432 -1248 -432 -1536
    WIRE -432 -1248 -496 -1248
    WIRE 2496 -1248 2496 -1376
    WIRE 576 -1232 576 -1488
    WIRE -496 -1216 -496 -1248
    WIRE 208 -1216 208 -1568
    WIRE 432 -1216 432 -1520
    WIRE 496 -1216 496 -1312
    WIRE 496 -1216 432 -1216
    WIRE 544 -1216 496 -1216
    WIRE 1152 -1216 1152 -1328
    WIRE 64 -1200 64 -1248
    WIRE 160 -1200 160 -1328
    WIRE 160 -1200 64 -1200
    WIRE 176 -1200 160 -1200
    WIRE 864 -1200 864 -1296
    WIRE 864 -1200 608 -1200
    WIRE 368 -1184 368 -1200
    WIRE 368 -1184 240 -1184
    WIRE 544 -1184 464 -1184
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    WIRE -80 -1168 -192 -1168
    WIRE 176 -1168 -80 -1168
    WIRE 1248 -1168 1248 -1296
    WIRE 1824 -1168 1824 -1344
    WIRE 368 -1152 368 -1184
    WIRE 464 -1152 464 -1184
    WIRE 2048 -1152 2048 -1456
    WIRE 2080 -1152 2048 -1152
    WIRE 2432 -1152 2368 -1152
    WIRE 2496 -1152 2496 -1248
    WIRE 2496 -1152 2432 -1152
    WIRE -192 -1136 -192 -1168
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    WIRE 1248 -1008 1248 -1104
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    WIRE 1920 -1008 1920 -1056
    WIRE 1920 -1008 1824 -1008
    WIRE 2224 -1008 2224 -1056
    WIRE 2224 -1008 1920 -1008
    WIRE 2240 -1008 2224 -1008
    WIRE 2496 -1008 2496 -1056
    WIRE 2496 -1008 2240 -1008
    WIRE -768 -992 -768 -1008
    WIRE 1504 -976 1504 -1008
    WIRE -656 -960 -656 -1008
    WIRE -288 -960 -288 -1008
    WIRE 2240 -960 2240 -1008
    WIRE 432 -912 432 -1216
    WIRE 480 -912 432 -912
    WIRE 624 -912 560 -912
    WIRE 864 -912 864 -1200
    WIRE 864 -912 704 -912
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    WIRE 128 -896 64 -896
    WIRE 368 -896 368 -1088
    WIRE 368 -896 192 -896
    WIRE 768 -896 768 -1008
    WIRE 64 -848 64 -896
    WIRE -912 -832 -912 -1728
    WIRE -656 -832 -656 -880
    WIRE -656 -832 -912 -832
    WIRE -544 -832 -656 -832
    WIRE -288 -832 -288 -896
    WIRE -288 -832 -544 -832
    WIRE 432 -816 432 -912
    WIRE 640 -816 432 -816
    WIRE 864 -816 864 -912
    WIRE 864 -816 704 -816
    WIRE 64 -752 64 -768
    WIRE 368 -752 368 -896
    WIRE 368 -752 64 -752
    WIRE 576 -752 576 -1168
    WIRE 768 -752 768 -832
    WIRE 768 -752 576 -752
    WIRE 208 -688 208 -1152
    WIRE 416 -688 208 -688
    WIRE 576 -688 416 -688
    WIRE 1312 -688 1312 -1280
    WIRE 1312 -688 576 -688
    WIRE 1984 -688 1984 -1296
    WIRE 1984 -688 1312 -688
    WIRE 2560 -688 2560 -1360
    WIRE 2560 -688 1984 -688
    FLAG 464 -1152 0
    FLAG -80 -1024 0
    FLAG -656 -1104 vcc
    FLAG -768 -992 0
    FLAG 352 -1568 Vcc
    FLAG 416 -688 Vee
    FLAG -496 -1216 0
    FLAG 0 -1872 Vout
    FLAG 2240 -960 0
    FLAG 2496 -1248 vref-1.25
    FLAG -976 -1408 Fet-gate
    FLAG 1296 -1648 filt1
    FLAG 1968 -1664 filt2
    FLAG 1504 -976 0
    FLAG 1584 -1456 Vcc
    FLAG -544 -832 Vee
    FLAG 208 -1696 0
    FLAG 608 -1696 0
    SYMBOL Opamps\\LT1360 208 -1248 R0
    SYMATTR InstName U1
    SYMBOL res 48 -1344 R0
    WINDOW 0 41 37 Left 2
    WINDOW 3 36 71 Left 2
    SYMATTR InstName R1
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res -96 -1152 R0
    WINDOW 3 41 74 Left 2
    WINDOW 0 43 31 Left 2
    SYMATTR Value 4k02
    SYMATTR InstName R2
    SYMATTR SpiceLine tol=1
    SYMBOL cap -208 -1136 R0
    SYMATTR InstName C1
    SYMATTR Value 3.3n
    SYMBOL schottky 352 -1264 R0
    WINDOW 3 -99 -2 Left 2
    SYMATTR Value BAS70L
    SYMATTR InstName D1
    SYMBOL schottky 352 -1152 R0
    WINDOW 3 -94 77 Left 2
    SYMATTR Value BAS70L
    SYMATTR InstName D2
    SYMBOL res 352 -1472 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R1a
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res 208 -1536 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 20k
    SYMATTR SpiceLine tol=1
    SYMBOL res 480 -1408 R0
    WINDOW 0 41 41 Left 2
    WINDOW 3 47 81 Left 2
    SYMATTR InstName R2a
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res 576 -928 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R2b
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res 720 -928 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R2c
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL cap 704 -832 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C2
    SYMATTR Value 220n
    SYMBOL cap 288 -1344 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C3
    SYMATTR Value 3.3p
    SYMBOL cap 192 -912 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C4
    SYMATTR Value 3.3p
    SYMBOL res 48 -864 R0
    WINDOW 0 39 33 Left 2
    WINDOW 3 40 74 Left 2
    SYMATTR InstName R1b
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL OpAmps\\opamp2 -288 -1584 R0
    WINDOW 3 11 165 Left 2
    SYMATTR Value LME49710
    SYMATTR InstName U3
    SYMATTR SpiceModel LME49710
    SYMBOL voltage -656 -1120 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL voltage -656 -976 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL cap -80 -1472 R0
    SYMATTR InstName C5
    SYMATTR Value 15nF
    SYMATTR SpiceLine V=63 Rser=0.04 Lser=12n
    SYMBOL res -128 -1360 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R4
    SYMATTR Value 10.5k
    SYMATTR SpiceLine tol=1
    SYMBOL cap -624 -1456 R0
    SYMATTR InstName C6
    SYMATTR Value 15nF
    SYMATTR SpiceLine V=63 Rser=0.04 Lser=12n
    SYMBOL res -480 -1280 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 10.5k
    SYMATTR SpiceLine tol=1
    SYMBOL njf -880 -1472 R0
    SYMATTR InstName J1
    SYMATTR Value MMBF4391
    SYMBOL res -144 -1760 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R6
    SYMATTR Value 10.0k
    SYMATTR SpiceLine tol=1
    SYMBOL res -496 -1760 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 4.87k
    SYMATTR SpiceLine tol=1
    SYMBOL cap -160 -1888 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C7
    SYMATTR Value 3.3p
    SYMBOL res -688 -1536 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R8
    SYMATTR Value 220
    SYMATTR SpiceLine tol=1
    SYMBOL cap 2672 -1616 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C8
    SYMATTR Value 6.8µ
    SYMBOL res 2416 -1760 R270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R10
    SYMATTR Value 3.9k
    SYMBOL References\\LTC6655-1.25 2224 -1120 R0
    SYMATTR InstName U4
    SYMBOL Opamps\\LT1056A 2560 -1456 R0
    SYMATTR InstName U5
    SYMBOL cap 2480 -1120 R0
    SYMATTR InstName C10
    SYMATTR Value 1µF
    SYMBOL cap 2528 -1552 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C11
    SYMATTR Value 3.3p
    SYMBOL diode -832 -1936 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D3
    SYMATTR Value 1N4148
    SYMBOL res -1152 -1568 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R11
    SYMATTR Value 8.2k
    SYMATTR SpiceLine tol=0.1
    SYMBOL Opamps\\OP27 576 -1264 R0
    SYMATTR InstName U2
    SYMBOL res 1296 -1520 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R12
    SYMATTR Value 14k
    SYMBOL res 1136 -1232 R0
    SYMATTR InstName R13
    SYMATTR Value 62k
    SYMBOL cap 1232 -1168 R0
    SYMATTR InstName C9
    SYMATTR Value 2.2n
    SYMBOL cap 976 -1600 R0
    SYMATTR InstName C12
    SYMATTR Value 2.2n
    SYMBOL res 1136 -1312 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 30k
    SYMBOL Opamps\\LT1013 1312 -1376 R0
    SYMATTR InstName U6
    SYMBOL res 880 -1280 R270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R15
    SYMATTR Value 40.2k
    SYMBOL res 1968 -1536 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R16
    SYMATTR Value 14k
    SYMBOL cap 1648 -1616 R0
    SYMATTR InstName C13
    SYMATTR Value 2.2n
    SYMBOL res 1808 -1328 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R17
    SYMATTR Value 30k
    SYMBOL Opamps\\LT1013 1984 -1392 R0
    WINDOW 3 -98 -2 Left 2
    SYMATTR InstName U7
    SYMBOL res 1488 -1296 R270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R18
    SYMATTR Value 40.2k
    SYMBOL res 1808 -1184 R0
    SYMATTR InstName R19
    SYMATTR Value 62k
    SYMBOL cap 1904 -1120 R0
    SYMATTR InstName C14
    SYMATTR Value 2.2n
    SYMBOL FerriteBead 576 -1536 R0
    SYMATTR InstName L1
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL FerriteBead 576 -720 R0
    SYMATTR InstName L2
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL cap 752 -1408 R0
    SYMATTR InstName C15
    SYMATTR Value 100n
    SYMBOL cap 752 -896 R0
    SYMATTR InstName C16
    SYMATTR Value 100n
    SYMBOL res 2304 -1424 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 82k
    SYMBOL res 2288 -1792 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R20
    SYMATTR Value 150k
    SYMBOL FerriteBead -288 -1648 R0
    SYMATTR InstName L3
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL FerriteBead -288 -928 R0
    SYMATTR InstName L4
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL cap -448 -1600 R0
    WINDOW 0 -60 15 Left 2
    WINDOW 3 -62 54 Left 2
    SYMATTR InstName C17
    SYMATTR Value 100n
    SYMBOL cap -448 -1168 R0
    WINDOW 0 -60 15 Left 2
    WINDOW 3 -62 54 Left 2
    SYMATTR InstName C18
    SYMATTR Value 100n
    SYMBOL Opamps\\LT1013 -912 -1824 M0
    SYMATTR InstName U8
    SYMBOL res -1056 -1648 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R21
    SYMATTR Value 10k
    SYMATTR SpiceLine tol=0.1
    SYMBOL ind 256 -1936 R270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 5 56 VBottom 2
    SYMATTR InstName L5
    SYMATTR Value 1m
    SYMATTR SpiceLine Ipk=40m Rser=40 Cpar=4.1p
    SYMBOL cap 192 -1824 R0
    SYMATTR InstName C19
    SYMATTR Value 1n
    SYMBOL ind 784 -1936 R270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 5 56 VBottom 2
    SYMATTR InstName L6
    SYMATTR Value 1m
    SYMATTR SpiceLine Ipk=40m Rser=40 Cpar=4.1p
    SYMBOL cap 592 -1824 R0
    SYMATTR InstName C20
    SYMATTR Value 1n
    SYMBOL res 512 -1968 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R22
    SYMATTR Value 1k
    SYMATTR SpiceLine tol=1
    SYMBOL res 1072 -1968 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R23
    SYMATTR Value 1k
    SYMATTR SpiceLine tol=1
    TEXT -1176 -904 Left 2 !.MODEL BAS70L D \n+ IS = 3.22E-9 \n+ N = 1.018
    \n+ BV = 77 \n+ IBV = 1.67E-7 \n+ RS = 20.89 \n+ CJO = 1.608E-12 \n+ VJ
    = 0.3891 \n+ M = 0.3683 \n+ FC = 0.5 \n+ EG = 0.69 \n+ XTI = 2 \n.ENDS
    TEXT -336 -528 Left 2 ;R2 a,b,c, Vishay Beschlag ACAS06S0830372P1AT
    precision 10k resistor array \n R1a, R1b Maxim MAX5492LB10000+T 10K
    resistive divider in a SOT-23-5 package
    TEXT -720 -464 Left 2 !.MODEL MMBF4391 NJF VTO=-4.6 BETA=0.02779
    LAMBDA=0.00595 RD=1 RS=1 IS=1e-14 CGD=14p CGS=10.5p PB=1 B=1 KF=1e-18
    AF=1 FC=0.5 mfg=Motorola
    TEXT -432 -408 Left 2 !.tran 0 10s 0 startup
    TEXT -720 -408 Left 2 !.lib LME49710.lib

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Fri Nov 15 08:00:12 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vh72bm$3b6ip$1@dont-email.me...
    On 15/11/2024 3:14 am, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I finally got around to digging out my AD734 based Wein bridge simulation, and created a FET based version.

    It's got a nasty 163kHz generator embedded in it somewhere, and I've put in an RL filter to keep that under control.

    The double Sallen and Keys network is a four pole Bessel filter which I'm using as a 250usec delay line - the output from the full
    wave rectifier has an appreciable 2kHz component, but the delayed contribution coming into the integrator through R9 roughly
    cancels the direct input through R20.

    R10 in the integrator damps the amplitude feedback loop for a dead-beat response.

    The harmonics in the 1kHz output are about 100dB below the fundamental. Not great, but respectable, and not worth trying to
    improve in a simulation.

    The circuit still works with the worst case values for the 1% capacitors at C5 and C6.


    After fixing line wraps and the position of U1 I need LME49710.lib

    I'll be back in a few days.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Sat Nov 16 02:24:35 2024
    On 16/11/2024 12:00 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vh72bm$3b6ip$1@dont-email.me...
    On 15/11/2024 3:14 am, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I finally got around to digging out my AD734 based Wein bridge simulation, and created a FET based version.

    It's got a nasty 163kHz generator embedded in it somewhere, and I've put in an RL filter to keep that under control.

    The double Sallen and Keys network is a four pole Bessel filter which I'm using as a 250usec delay line - the output from the full
    wave rectifier has an appreciable 2kHz component, but the delayed contribution coming into the integrator through R9 roughly
    cancels the direct input through R20.

    R10 in the integrator damps the amplitude feedback loop for a dead-beat response.

    The harmonics in the 1kHz output are about 100dB below the fundamental. Not great, but respectable, and not worth trying to
    improve in a simulation.

    The circuit still works with the worst case values for the 1% capacitors at C5 and C6.


    After fixing line wraps and the position of U1 I need LME49710.lib

    I'll be back in a few days.

    John May posted it it a few weeks ago. Here's the text version I've been
    using.

    * LME49710 *****************************************************************************
    * (C) Copyright 2011 Texas Instruments Incorporated. All rights
    reserved. ***************************************************************************** ** This model is designed as an aid for customers of Texas Instruments.
    ** TI and its licensors and suppliers make no warranties, either expressed
    ** or implied, with respect to this model, including the warranties of
    ** merchantability or fitness for a particular purpose. The model is
    ** provided solely on an "as is" basis. The entire risk as to its quality
    ** and performance is with the customer. *****************************************************************************
    *
    ** Released by: Analog eLab Design Center, Texas Instruments Inc.
    * Date: 2011-11-18
    * Model Type: ALL IN ONE
    * Simulator: PSPICE
    * Simulator Version: 16.2.0.p001
    * Datasheet: March 2007
    * EVM Order Number: N/A
    * EVM Users Guide: N/A
    * Model Version: 1.0
    *
    *****************************************************************************
    *
    * Updates:
    *
    * Version 1.0 :
    * Release to Web
    *
    *****************************************************************************
    * The LME49710 Macro Model represents the following parameters for
    * Vcc=+/-15V:
    * GBWP, input-referred voltage noise, the quiescent current,
    * output swing, input offset voltage, input bias current,
    * PSRR and CMRR, and the slew rate.
    *
    * For any convergence problems, it is suggested to set the following
    simulation
    * options:
    * VNTOL: 10u
    * ABSTOL: 10n
    * ITL1: 1000
    * ITL2: 400
    * ITL4: 400 *****************************************************************************
    *
    *****************************************************************************
    *
    *$
    .SUBCKT LME49710 INP INN VCC VEE OUT
    *X_Ugnd VCC 0 VEE 0 GND_FLOAT 0 EPOLY2 PARAMS:
    COEFF1=0.5 COEFF2=0.5
    Rgn1 0 GND_FLOAT 100MEG
    EVCVSgn1 GND_FLOAT 0 32 0 1
    EVCVSgn2 33 0 VCC 0 1
    EVCVSgn3 31 0 VEE 0 1
    Cgn1 32 0 1
    XRgn2 32 33 RNOISELESS PARAMS: ROHMS=1E6
    XRgnd3 31 32 RNOISELESS PARAMS: ROHMS=1E6
    X_U9 VCC VEE PD VIMON GND_FLOAT INP2 INN1 HPA_PD_I PARAMS: VTH=1.4
    + IMAX=4.8e-3 IMIN=3N IIBP=7n IIBN=7.1n

    V_Vos INP2 INP_CMRR 33.2uVdc
    C_Cinp GND_FLOAT INP1 200f TC=0,0
    C_Cinn GND_FLOAT INN1 200f TC=0,0
    R_Rinp INP INP1 1 TC=0,0
    R_Rinn INN INN1 1 TC=0,0
    X_U12 INP1 INP2 VNSE
    X_UCN INP1 INN1 FEMT

    X_Ug0 INP_CMRR INN3 GND_FLOAT AV1 VCCS_LIMIT PARAMS: GAIN=10e-6
    + IPOS=0.5 INEG=-0.5
    X_Ug4 AV1 GND_FLOAT GND_FLOAT OVER_CLAMP VCCS_LIMIT PARAMS: GAIN=172.8u
    + IPOS=98u INEG=-98u
    X_U1 GND_FLOAT AV1 RNOISELESS PARAMS: R=1e6
    X_U2 GND_FLOAT OVER_CLAMP RNOISELESS PARAMS: R=5.8e9

    C_Ucl_Ccl2 GND_FLOAT Ucl_N01226 1p TC=0,0
    C_Ucl_Ccl1 Ucl_N01131 GND_FLOAT 1p TC=0,0
    V_Ucl_Vclp Ucl_N00774 GND_FLOAT 53Vdc
    V_Ucl_Vcln Ucl_N00760 GND_FLOAT -42Vdc
    X_Ucl_Ucl1 Ucl_N50037 Ucl_N01131 D_ideal
    X_Ucl_Ucl2 Ucl_N01226 Ucl_N50037 D_ideal
    E_Ucl_E1 Ucl_N01131 GND_FLOAT Ucl_N00774 VIMON 100
    E_Ucl_E2 Ucl_N01226 GND_FLOAT Ucl_N00760 VIMON 100
    R_Ucl_Rcl1 Ucl_N01131 N3310462 1 TC=0,0
    R_Ucl_Rcl2 N3310462 Ucl_N01226 1 TC=0,0
    R_Ucl_Rcl3 Ucl_N50037 CL_CLAMP 0.01 TC=0,0

    E_E1 VCC_BUF GND_FLOAT VCC GND_FLOAT 1
    E_E2 VEE_BUF GND_FLOAT VEE GND_FLOAT 1

    C_Cc1 GND_FLOAT OVER_CLAMP 5p TC=0,0
    C_Cc2 P0ZP1 GND_FLOAT 723.4e-18 TC=0,0
    C_Cc3 CLAW_CLAMP GND_FLOAT 144.7f TC=0,0
    C_Cc4 GND_FLOAT GND_FLOAT 4.11f TC=0,0

    V_V1 VCC N3310020 1.89Vdc
    V_V4 N3310060 VEE 1.99Vdc
    X_Ud1 INP_CMRR N3310020 D_ideal
    X_Ud2 INN3 N3310020 D_ideal
    X_Ud3 N3310060 INP_CMRR D_ideal
    X_Ud4 N3310060 INN3 D_ideal

    R_R2 GND_FLOAT N3309562 1G TC=0,0
    R_R3 GND_FLOAT N3310462 1G TC=0,0
    R_R4 VCC PD 1e-3 TC=0,0
    G_G3 GND_FLOAT VSENSE OVER_CLAMP GND_FLOAT 1u
    G_G4 GND_FLOAT P0Z VSENSE GND_FLOAT 1u
    G_G5 GND_FLOAT P0ZP1 P0Z GND_FLOAT 1u
    G_G6 GND_FLOAT CLAW_CLAMP P0ZP1 GND_FLOAT 1m
    G_G7 GND_FLOAT CL_CLAMP CLAW_CLAMP GND_FLOAT 1m
    X_U3 VSENSE GND_FLOAT RNOISELESS PARAMS: R=1e6
    X_U5 GND_FLOAT P0Z RNOISELESS PARAMS: R=1e6
    X_U6 P0ZP1 GND_FLOAT RNOISELESS PARAMS: R=1e6
    X_U7 CLAW_CLAMP GND_FLOAT RNOISELESS PARAMS: R=1e3
    X_U8 CL_CLAMP GND_FLOAT RNOISELESS PARAMS: R=1e3

    G_G1 GND_FLOAT N3309274 INP_CMRR GND_FLOAT 1u
    E_Ecmrr INN2 INN3 N3309274 GND_FLOAT 1
    R_Rcmr N3309274 N33089240 1 TC=0,0
    L_Lcmr N33089240 GND_FLOAT 560nH

    G_G2 GND_FLOAT N3309420 VCC VEE 562.3n
    X_Upsrr N3309420 GND_FLOAT INN1 INN2 VCVS_LIMIT PARAMS: GAIN=-1
    + VPOS=20M VNEG=-20M
    R_Rpsr N3309420 N33093920 1 TC=0,0
    L_Lpsr N33093920 GND_FLOAT 2uH

    V_Uvcl_Vclo1 VCC_BUF Uvcl_N498931 3.95Vdc
    V_Uvcl_Vclo2 Uvcl_N50894 VEE_BUF 3.95Vdc
    X_Uvcl_Uvcl1 OVER_CLAMP Uvcl_N498931 D_ideal
    X_Uvcl_Uvcl2 Uvcl_N50894 OVER_CLAMP D_ideal

    X_Uz_S1 N3309562 GND_FLOAT Uz_N45387 Uz_VZO_3 Zout_Uz_S1
    X_Uz_S2 N3309562 GND_FLOAT Uz_N45507 Uz_VZO_3 Zout_Uz_S2
    R_Uz_Ra Uz_N45387 Uz_VZO_4 10 TC=0,0
    R_Uz_Rb Uz_N45507 Uz_VZO_4 10 TC=0,0
    R_Uz_Rm Uz_VZO_3 Uz_VZO_4 10 TC=0,0
    X_Uz_Uamp1 VCLP Uz_N36964 Uz_VZO_1 GND_FLOAT VCVS_LIMIT PARAMS:
    + GAIN=1e6 VPOS=6e4 VNEG=-6e4
    X_Uz_Uamp2 GND_FLOAT Uz_N37614 Uz_VZO_3 GND_FLOAT VCVS_LIMIT PARAMS:
    + GAIN=1e6 VPOS=6e4 VNEG=-6e4
    E_Uz_E1 Uz_VZO_2 GND_FLOAT Uz_VZO_1 Uz_VZO_4 -1
    X_Uz_Rg1 GND_FLOAT Uz_N36964 RNOISELESS PARAMS: R=10e6
    X_Uz_Rf1 Uz_N36964 Uz_VZO_1 RNOISELESS PARAMS: R=10e6
    X_Uz_Rg2 Uz_VZO_2 Uz_N37614 RNOISELESS PARAMS: R=1e6
    X_Uz_Rf2 Uz_N37614 Uz_VZO_3 RNOISELESS PARAMS: R=1e6
    X_Uz_H1 Uz_VZO_4 OUT VIMON GND_FLOAT Zout_Uz_H1

    X_Uthd N3309236 GND_FLOAT VCLP GND_FLOAT EPOLY1
    *+PARAMS: COEFF1=0.0 COEFF2=0.0

    X_U10 CL_CLAMP GND_FLOAT PD N3309236 GND_FLOAT VCC VEE
    HPA_PD_SGNL
    + PARAMS: GAIN=1
    X_U11 VCC VEE VIMON GND_FLOAT Tran_Iout
    .ENDS LME49710
    *$

    .subckt Zout_Uz_S2 1 2 3 4
    S_Uz_S2 3 4 1 2 _Uz_S2
    RS_Uz_S2 1 2 1G
    .MODEL _Uz_S2 VSWITCH Roff=10e6 Ron=1.0 Voff=0.1V Von=-0.1V
    .ends Zout_Uz_S2

    .subckt Zout_Uz_S1 1 2 3 4
    S_Uz_S1 3 4 1 2 _Uz_S1
    RS_Uz_S1 1 2 1G
    .MODEL _Uz_S1 VSWITCH Roff=10e6 Ron=1.0 Voff=-0.1V Von=0.1V
    .ends Zout_Uz_S1
    *$
    .subckt Zout_Uz_H1 1 2 3 4
    H_Uz_H1 3 4 VH_Uz_H1 1e3
    VH_Uz_H1 1 2 0V
    .ends Zout_Uz_H1
    *$
    *
    .subckt D_ideal A C
    D1 A C DNOM
    .MODEL DNOM D (TT=10p CJO=1e-18 IS=1e-16 RS=1e-4)
    *.MODEL DNOM D (TT=10p CJO=1e-18 IS=1e-16 RS=1e-4 N=1e-3)
    .ENDS D_ideal
    *
    *$
    .SUBCKT VNSE 1 2
    **************************
    * BEGIN SETUP OF NOISE GEN - NANOVOLT/RT-HZ
    * INPUT THREE VARIABLES
    * NLF - NV/RHZ AT (1/F) FREQ
    * FLW - FREQ FOR (1/F) VAL
    * NVR - NV/RHZ FLATBAND
    **************************
    * START CALC VALS
    .PARAM NLF=6.4
    .PARAM FLW=8.5
    .PARAM NVR=2.5
    .PARAM GLF={PWR(FLW,0.25)*NLF/1164}
    .PARAM RNV={1.184*PWR(NVR,2)}
    .MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
    * END CALC VALS
    I1 0 7 10E-3
    I2 0 8 10E-3
    D1 7 0 DVN
    D2 8 0 DVN
    E1 3 6 7 8 {GLF}
    R1 3 0 1E9
    R2 3 0 1E9
    R3 3 6 1E9
    E2 6 4 5 0 10
    R4 5 0 {RNV}
    R5 5 0 {RNV}
    R6 3 4 1E9
    R7 4 0 1E9
    E3 1 2 3 4 1
    C1 1 0 1E-15
    C2 2 0 1E-15
    C3 1 2 1E-15
    .ENDS VNSE
    *$

    .SUBCKT FEMT 1 2
    **************************
    * BEGIN SETUP OF NOISE GEN - FEMPTOAMPS/RT-HZ
    * INPUT THREE VARIABLES
    * NLFF - SET UP INSE 1/F
    * FLWF - FA/RHZ AT 1/F FREQ
    * NVRF - FA/RHZ FLATBAND
    **************************
    * START CALC VALS
    .PARAM NLFF=3.1e3
    .PARAM FLWF=7.5
    .PARAM NVRF=1.6e3
    .PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}
    .PARAM RNVF={1.184*PWR(NVRF,2)}
    .MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16
    * END CALC VALS
    I1 0 7 10E-3
    I2 0 8 10E-3
    D1 7 0 DVNF
    D2 8 0 DVNF
    E1 3 6 7 8 {GLFF}
    R1 3 0 1E9
    R2 3 0 1E9
    R3 3 6 1E9
    E2 6 4 5 0 10
    R4 5 0 {RNVF}
    R5 5 0 {RNVF}
    R6 3 4 1E9
    R7 4 0 1E9
    G1 1 2 3 4 1E-6
    C1 1 0 1E-15
    C2 2 0 1E-15
    C3 1 2 1E-15
    .ENDS FEMT
    *
    *$
    .SUBCKT Tran_Iout VCC VEE VIMON AGND
    X_Siq1 N1 GND_FLOAT VIMON N2 Amp_Dyn_Iout_Siq1
    X_Siq2 N1 GND_FLOAT VIMON N3 Amp_Dyn_Iout_Siq2
    C_Ciq1 N1 GND_FLOAT 10e-12 TC=0,0
    R_Riq1 N1 VIMON 10 TC=0,0
    R_Riq2 N2 GND_FLOAT 10e3 TC=0,0
    R_Riq3 GND_FLOAT N3 10e3 TC=0,0
    G_Gsourcing VCC GND_FLOAT N3 GND_FLOAT 0.001
    G_Gsinking VEE GND_FLOAT N2 GND_FLOAT 0.001
    .ENDS Tran_Iout
    *$
    .subckt Amp_Dyn_Iout_Siq1 1 2 3 4
    S_Siq1 3 4 1 2 _Siq1
    RS_Siq1 1 2 1G
    .MODEL _Siq1 VSWITCH Roff=1e6 Ron=1.0 Voff=0.0V Von=-0.10V
    .ends Amp_Dyn_Iout_Siq1
    *$

    .subckt Amp_Dyn_Iout_Siq2 1 2 3 4
    S_Siq2 3 4 1 2 _Siq2
    RS_Siq2 1 2 1G
    .MODEL _Siq2 VSWITCH Roff=1e6 Ron=1.0 Voff=0.0V Von=0.10V
    .ends Amp_Dyn_Iout_Siq2
    *$
    *
    .subckt VCCS_Limit VCP VCN IOUTP IOUTN PARAMS: Gain = 1.7e-3
    + Ipos = 0.100 Ineg = -0.165
    G1 IOUTP IOUTN VALUE={LIMIT(Gain*V(VCP,VCN),Ipos,Ineg)}
    .ends VCCS_Limit
    *$
    *
    .subckt VCVS_Limit VCP VCN VOUTP VOUTN PARAMS: Gain = -1
    + Vpos = 20m Vneg = -20m
    E1 VOUTP VOUTN VALUE={LIMIT(Gain*V(VCP,VCN),Vpos,Vneg)}
    .ends VCVS_Limit
    *$
    *
    .SUBCKT HPA_PD_I VCC VEE PD Vimon AGND Ninp Ninn PARAMS: Vth = 1.4 Imax
    = 1e-3 Imin = 3n
    + IIBP= 0.55u IIBN= 0.56u
    *GBIAS VCC VEE VALUE = {IF(V(PD) >= (V(VEE)+Vth),Imax,Imin)}
    GBIAS VCC VEE VALUE = {IF(V(PD) >= V(VCC),Imax,Imin)}
    Ebuf VDD 0 VCC 0 1
    Ginp VDD Ninp VALUE = {IF(V(PD) >= V(VCC),IIBP,0)}
    Ginn VDD Ninn VALUE = {IF(V(PD) >= V(VCC),IIBN,0)}
    .ENDS
    *$
    .SUBCKT HPA_PD_Sgnl CP CN DIS VP VN VCC VEE PARAMS: GAIN = 1
    EVCVS VP VN VALUE = {IF(V(DIS,VEE) >= 1.4,V(CP,CN)*GAIN,0)}
    .ENDS HPA_PD_Sgnl
    *$
    *$
    *
    .SUBCKT EPOLY2 1 2 3 4 7 8 PARAMS: Coeff1=0.5 Coeff2=0.5
    *EINT 7 8 POLY(2) (1,2) (3,4) (0 Coeff1 Coeff2)
    EINT 7 8 POLY(2) (1,2) (3,4) (0 0.5 0.5)
    .ENDS EPOLY2
    *$
    *
    .SUBCKT EPOLY1 1 2 3 4 PARAMS: Coeff1=0.0 Coeff2=0.0
    *For distortion purpose
    EINT 3 4 POLY(1) (1,2) (0 1 8.5e-5 14.26e-4)
    *EINT 3 4 POLY(1) (1,2) (0 1 0 0)
    *EINT 3 4 1 2 1
    .ENDS EPOLY1
    *$
    *
    .subckt Rnoiseless a b PARAMS: R=1k
    ERES a 3 VALUE = { I(VSENSE) * R }
    Rdummy 30 3 1
    VSENSE 30 b DC 0V
    .ends Rnoiseless
    *$

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Bill Sloman on Sun Nov 17 01:29:11 2024
    On 15/11/2024 7:56 pm, Bill Sloman wrote:
    On 15/11/2024 3:14 am, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message
    news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I finally got around to digging out my AD734 based Wein bridge
    simulation, and created a FET based version.

    It's got a nasty 163kHz generator embedded in it somewhere, and I've put
    in an RL filter to keep that under control.

    It looks as if the 163kHz might coming from the 1.25V precision
    reference. I'll have to dig into the data sheet to see if I can make
    sense of this.

    It's being sold as a very quiet voltage source, and I had thought that
    I'd read up on what I needed to do to keep it quiet.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Bill Sloman on Sun Nov 17 02:27:23 2024
    On 15/11/2024 7:56 pm, Bill Sloman wrote:
    On 15/11/2024 3:14 am, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message
    news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I finally got around to digging out my AD734 based Wein bridge
    simulation, and created a FET based version.

    It's got a nasty 163kHz generator embedded in it somewhere, and I've put
    in an RL filter to keep that under control.

    It looks as if the 163kHz was coming from the LTC6655-1.25V precision reference.

    Putting in 4.7uF at C10 - rather than the 1.0uF I started off with -
    seems to make the simulation run a lot faster - about 20 times faster -
    and cleaned out the visible hash coming from the voltage reference.

    The data sheet says use something between 2.7uF and 100uF and recommends
    film parts - ESR less than 0.1R. They don't like ceramic parts.

    Pulling out the LCR filter (L5,L6, C19, C20, R22 and R23) may have
    speeded up the simulation too.

    The 2kHz and 3kHz harmonics aren't as good as they were - only about
    65db below the fundamental - so Ill have to do some more digging.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to sunaecoNoChoppedPork@gmail.com on Sun Nov 17 22:58:58 2024
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    This is the simplest circuit I can come up with.
    ...


    Using an NSL-32SR3 doesn't really gain you anything over a FET. If
    you keep |vds| much less than |Vt-vgs| in the circuit and compensate
    for the vds/2 variation on the gate drive the distortion levels
    produced will be lower than almost all opamps out there. Here's a
    link to a sim using an LDR.

    https://1drv.ms/f/c/1af24d72a509cd48/EkjNCaVyTfIggBrrAQAAAAABHXNKs52BoVHi7zaxKmdMMQ?e=oVD0JS

    I've added some 3rd harmonic distortion to a linear model to give
    distortion figures roughly in the ballpark of Fig 6 in the attached
    application note (for small signal swings across the device). In the
    oscillator o/p the 3rd is about 150dB down. If you use the linear LDR
    model, or a FET, it will be much the same. (The opamps used in the sim
    actually have distortions specs of about 130dB in reallity.)

    Thanks for that. I left it overnight for 100 seconds of simulation. It looks like it has better harmonic performance than my
    circuit.
    Why use two op amps in the oscillator instead of one like my circuit?

    Because of common mode (non)linearity. In most op-amps (especially
    older designs) the distortion generated by the common mode signal is typically one to two orders of magnitude larger than the transfer
    distortion. If it is not clear from the data sheet, it is best to
    measure the CM performance or just assume that it's 40dB worse than
    the specified figure.

    Note that it is seldom modeled in a (free) spice model.

    This is a link to an extract discussing it's measurement.

    https://1drv.ms/u/c/1af24d72a509cd48/ESErQT4Elb5FsgcgsOp1J3wBWZSYHvooHblQJPA3DmydbA?e=wwqtSy

    Thank you very much for that information.


    What happens without the initial conditions? Does it take a long time to settle?
    I'll be away until next week.


    No idea. LTSpice is useless for handling large simulation data files
    so I don't bother trying to use it to check for that sort of thing.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Mon Nov 18 15:06:01 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhadl5$2v27$1@dont-email.me...
    On 15/11/2024 7:56 pm, Bill Sloman wrote:
    On 15/11/2024 3:14 am, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I finally got around to digging out my AD734 based Wein bridge simulation, and created a FET based version.

    It's got a nasty 163kHz generator embedded in it somewhere, and I've put in an RL filter to keep that under control.

    It looks as if the 163kHz was coming from the LTC6655-1.25V precision reference.

    Putting in 4.7uF at C10 - rather than the 1.0uF I started off with - seems to make the simulation run a lot faster - about 20
    times faster - and cleaned out the visible hash coming from the voltage reference.

    The data sheet says use something between 2.7uF and 100uF and recommends film parts - ESR less than 0.1R. They don't like ceramic
    parts.

    Pulling out the LCR filter (L5,L6, C19, C20, R22 and R23) may have speeded up the simulation too.

    The 2kHz and 3kHz harmonics aren't as good as they were - only about 65db below the fundamental - so Ill have to do some more
    digging.

    I changed C10 to 4.7uF and ran the simulation to 10 seconds.
    L5 etc are still present.
    FFT from 2s to 10s says 60dB down at 3kHz


    --
    Bill Sloman, Sydney


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Tue Nov 19 23:46:34 2024
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    Here's another variation. This one take's John May's advice and spreads
    the phase shift oscillator over three op amps, all operating with the non-inverting input grounded.

    U1 now has only one 3.3pF frequency compensation capacitor - the
    simulation started slowing down to picoseconds per second from time to
    time, and this made it happen less often. The two compensation capacitor
    scheme would probably be fine in real life.

    The circuit takes a long time to settle down to stable operation - about
    5 seconds,and that after I cut the integrating capacitor from 6.8uF to
    680nF and put in D4 to minimise the initial overshoot on the FET gate
    drive - and the performance isn't wonderful. The second and third
    harmonics are about 75dB below the fundamental and 65dB down
    respectively. I'll play about a bit more but the main charm of the
    circuit is that it is easy to explain what each bit does.

    Version 4
    SHEET 1 3608 920
    WIRE -1376 -2064 -1696 -2064
    WIRE -1040 -2064 -1376 -2064
    WIRE -656 -2064 -1040 -2064
    WIRE -320 -2064 -656 -2064
    WIRE 192 -2064 -320 -2064
    WIRE 336 -2064 192 -2064
    WIRE 576 -2064 336 -2064
    WIRE -656 -2048 -656 -2064
    WIRE -1040 -2032 -1040 -2064
    WIRE -320 -2032 -320 -2064
    WIRE -1616 -1952 -1920 -1952
    WIRE 2816 -1952 -1552 -1952
    WIRE -1040 -1920 -1040 -1968
    WIRE -1040 -1920 -1216 -1920
    WIRE -656 -1920 -656 -1984
    WIRE -656 -1920 -720 -1920
    WIRE -320 -1920 -320 -1968
    WIRE -176 -1920 -320 -1920
    WIRE -640 -1904 -656 -1920
    WIRE -1216 -1888 -1216 -1920
    WIRE -320 -1888 -320 -1920
    WIRE -720 -1872 -720 -1920
    WIRE -1616 -1792 -1824 -1792
    WIRE -128 -1776 -256 -1776
    WIRE -32 -1776 -64 -1776
    WIRE 2304 -1776 864 -1776
    WIRE 2480 -1776 2384 -1776
    WIRE 2544 -1776 2480 -1776
    WIRE 2768 -1776 2624 -1776
    WIRE -1696 -1760 -1696 -2064
    WIRE -1616 -1744 -1616 -1792
    WIRE -1616 -1744 -1664 -1744
    WIRE -1824 -1728 -1824 -1792
    WIRE -1728 -1728 -1824 -1728
    WIRE 2768 -1728 2768 -1776
    WIRE -1616 -1712 -1664 -1712
    WIRE -1440 -1712 -1616 -1712
    WIRE -1168 -1712 -1440 -1712
    WIRE -1008 -1712 -1088 -1712
    WIRE -864 -1712 -928 -1712
    WIRE 112 -1712 64 -1712
    WIRE 432 -1712 192 -1712
    WIRE 1968 -1664 1664 -1664
    WIRE 2240 -1664 1968 -1664
    WIRE -592 -1648 -688 -1648
    WIRE -480 -1648 -528 -1648
    WIRE 1296 -1648 992 -1648
    WIRE 1456 -1648 1296 -1648
    WIRE -1824 -1632 -1824 -1728
    WIRE -1440 -1632 -1440 -1712
    WIRE 1664 -1616 1664 -1664
    WIRE 2480 -1616 2480 -1776
    WIRE 2640 -1616 2480 -1616
    WIRE 2768 -1616 2768 -1664
    WIRE 2768 -1616 2704 -1616
    WIRE 992 -1600 992 -1648
    WIRE -976 -1584 -1152 -1584
    WIRE -864 -1584 -864 -1712
    WIRE -864 -1584 -912 -1584
    WIRE -640 -1568 -640 -1904
    WIRE 576 -1568 576 -2064
    WIRE -1920 -1552 -1920 -1952
    WIRE -864 -1552 -864 -1584
    WIRE -832 -1552 -864 -1552
    WIRE -688 -1552 -688 -1648
    WIRE -688 -1552 -752 -1552
    WIRE -672 -1552 -688 -1552
    WIRE -176 -1552 -176 -1920
    WIRE -1040 -1536 -1040 -1920
    WIRE -480 -1536 -480 -1648
    WIRE -480 -1536 -608 -1536
    WIRE -432 -1536 -480 -1536
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    TEXT -1960 -904 Left 2 !.MODEL BAS70L D \n+ IS = 3.22E-9 \n+ N = 1.018
    \n+ BV = 77 \n+ IBV = 1.67E-7 \n+ RS = 20.89 \n+ CJO = 1.608E-12 \n+ VJ
    = 0.3891 \n+ M = 0.3683 \n+ FC = 0.5 \n+ EG = 0.69 \n+ XTI = 2 \n.ENDS
    TEXT -336 -528 Left 2 ;R2 a,b,c, Vishay Beschlag ACAS06S0830372P1AT
    precision 10k resistor array \n R1a, R1b Maxim MAX5492LB10000+T 10K
    resistive divider in a SOT-23-5 package
    TEXT -720 -464 Left 2 !.MODEL MMBF4391 NJF VTO=-4.6 BETA=0.02779
    LAMBDA=0.00595 RD=1 RS=1 IS=1e-14 CGD=14p CGS=10.5p PB=1 B=1 KF=1e-18
    AF=1 FC=0.5 mfg=Motorola
    TEXT -432 -408 Left 2 !.tran 0 10s 0 startup
    TEXT -720 -408 Left 2 !.lib LME49710.lib


    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Wed Nov 20 02:37:47 2024
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I've taken John May seriously, and reworked my phase shift oscillator to
    use three op amps, all with their non-inverting inputs tied to ground.

    The results aren't all that impressive, the lower harmonics are about
    65dB below the fundamental. Start-up is slow - it takes about five
    seconds of simulation before the circuit settles down into steady state operation, and that after I dropped the integrating capacitor from 6.8uF
    to 680nF. The nice thing about the circuit is that I can explain what
    each bit is doing. I can see a few tweaks that might be worth trying.

    Version 4
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    SYMATTR InstName L6
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL res -912 -1728 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R22
    SYMATTR Value 4.87k
    SYMATTR SpiceLine tol=1
    SYMBOL FerriteBead -320 -2000 R0
    SYMATTR InstName L8
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL cap -912 -1600 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C22
    SYMATTR Value 10p
    SYMBOL OpAmps\\opamp2 -640 -1600 R0
    WINDOW 3 13 108 Left 2
    SYMATTR Value LME49710
    SYMATTR InstName U10
    SYMATTR SpiceModel LME49710
    SYMBOL cap -736 -1872 R0
    WINDOW 0 -60 15 Left 2
    WINDOW 3 -62 54 Left 2
    SYMATTR InstName C7
    SYMATTR Value 100n
    SYMBOL FerriteBead -656 -2016 R0
    SYMATTR InstName L3
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL FerriteBead -640 -896 R0
    SYMATTR InstName L9
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL cap -864 -1152 R0
    WINDOW 0 -60 15 Left 2
    WINDOW 3 -62 54 Left 2
    SYMATTR InstName C23
    SYMATTR Value 100n
    SYMBOL npn -1888 -1152 R0
    SYMATTR InstName Q1
    SYMATTR Value BC547B
    SYMBOL npn -1984 -1152 M0
    SYMATTR InstName Q2
    SYMATTR Value BC547B
    SYMBOL res -1840 -1024 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R23
    SYMATTR Value 1.2k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res -2064 -1024 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R24
    SYMATTR Value 1.2k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res -2064 -1392 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R25
    SYMATTR Value 6.8k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res 2512 -1344 R0
    WINDOW 0 41 41 Left 2
    WINDOW 3 47 81 Left 2
    SYMATTR InstName R26
    SYMATTR Value 100k
    SYMATTR SpiceLine tol=0.1
    SYMBOL res -1072 -1728 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R6
    SYMATTR Value 82
    TEXT -1712 -776 Left 2 !.MODEL BAS70L D \n+ IS = 3.22E-9 \n+ N = 1.018
    \n+ BV = 77 \n+ IBV = 1.67E-7 \n+ RS = 20.89 \n+ CJO = 1.608E-12 \n+ VJ
    = 0.3891 \n+ M = 0.3683 \n+ FC = 0.5 \n+ EG = 0.69 \n+ XTI = 2 \n.ENDS
    TEXT -336 -528 Left 2 ;R2 a,b,c, Vishay Beschlag ACAS06S0830372P1AT
    precision 10k resistor array \n R1a, R1b Maxim MAX5492LB10000+T 10K
    resistive divider in a SOT-23-5 package
    TEXT -720 -464 Left 2 !.MODEL MMBF4391 NJF VTO=-4.6 BETA=0.02779
    LAMBDA=0.00595 RD=1 RS=1 IS=1e-14 CGD=14p CGS=10.5p PB=1 B=1 KF=1e-18
    AF=1 FC=0.5 mfg=Motorola
    TEXT -432 -408 Left 2 !.tran 0 10s 0 startup
    TEXT -720 -408 Left 2 !.lib LME49710.lib

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Tue Nov 19 20:59:04 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I've taken John May seriously, and reworked my phase shift oscillator to use three op amps, all with their non-inverting inputs
    tied to ground.

    The results aren't all that impressive, the lower harmonics are about 65dB below the fundamental. Start-up is slow - it takes
    about five seconds of simulation before the circuit settles down into steady state operation, and that after I dropped the
    integrating capacitor from 6.8uF to 680nF. The nice thing about the circuit is that I can explain what each bit is doing. I can
    see a few tweaks that might be worth trying.


    The simulation died after 3 seconds, as if insufficient gain to sustain oscillation.

    You seem to have a lot of components.
    Are you sure you really need all those ferrites?

    Here's my really definitely final final offering.

    A comfortable 90dB down at 2kHz and > 100 dB elsewhere.
    Also looks clean either side of 1kHz.
    Whether or not this has anything to do with reality I do not know.
    The diode stabilizer string will be temperature dependent,
    requiring readjustment of R4 and a total of three adjustments are needed.
    Only three op amps (two packages) are needed.

    Version 4
    SHEET 1 2196 932
    WIRE -64 -672 -96 -672
    WIRE 48 -672 0 -672
    WIRE -96 -576 -96 -672
    WIRE -64 -576 -96 -576
    WIRE 48 -576 48 -672
    WIRE 48 -576 16 -576
    WIRE 128 -528 112 -528
    WIRE 208 -528 192 -528
    WIRE 288 -528 272 -528
    WIRE 368 -528 352 -528
    WIRE 448 -528 432 -528
    WIRE 528 -528 512 -528
    WIRE 640 -528 592 -528
    WIRE 640 -512 640 -528
    WIRE -32 -464 -32 -480
    WIRE 48 -448 48 -576
    WIRE 48 -448 0 -448
    WIRE -96 -432 -96 -576
    WIRE -64 -432 -96 -432
    WIRE 112 -416 112 -528
    WIRE 112 -416 0 -416
    WIRE 160 -416 112 -416
    WIRE 208 -416 160 -416
    WIRE 336 -416 288 -416
    WIRE 400 -416 336 -416
    WIRE 512 -416 400 -416
    WIRE 624 -416 512 -416
    WIRE -96 -384 -96 -432
    WIRE -32 -384 -32 -400
    WIRE 48 -368 48 -448
    WIRE 336 -368 336 -416
    WIRE 160 -352 160 -416
    WIRE 400 -352 400 -416
    WIRE 512 -288 512 -416
    WIRE 624 -288 624 -416
    WIRE -96 -272 -96 -304
    WIRE -96 -272 -192 -272
    WIRE -96 -240 -96 -272
    WIRE 48 -240 48 -288
    WIRE 160 -240 160 -288
    WIRE 336 -240 336 -288
    WIRE 400 -240 400 -288
    WIRE -192 -176 -192 -272
    WIRE -224 -128 -256 -128
    WIRE -96 -128 -96 -160
    WIRE -96 -128 -128 -128
    WIRE -80 -128 -96 -128
    WIRE 16 -128 -80 -128
    WIRE 176 -128 96 -128
    WIRE 288 -128 176 -128
    WIRE 512 -128 512 -224
    WIRE 512 -128 368 -128
    WIRE -256 -48 -256 -128
    WIRE -208 -48 -256 -48
    WIRE -80 -48 -80 -128
    WIRE -80 -48 -128 -48
    WIRE 176 -16 176 -128
    WIRE 176 -16 64 -16
    WIRE 240 -16 176 -16
    WIRE 368 -16 320 -16
    WIRE 512 -16 512 -128
    WIRE 512 -16 448 -16
    WIRE -256 0 -256 -48
    WIRE 144 48 144 32
    WIRE 64 96 64 -16
    WIRE 112 96 64 96
    WIRE 512 96 512 -16
    WIRE 512 96 272 96
    WIRE -32 128 -96 128
    WIRE 112 128 -32 128
    WIRE 624 144 624 -224
    WIRE 656 144 624 144
    WIRE 752 144 720 144
    WIRE -320 160 -400 160
    WIRE -256 160 -320 160
    WIRE -32 160 -32 128
    WIRE 112 160 64 160
    WIRE 624 160 624 144
    WIRE 624 160 272 160
    WIRE 752 176 752 144
    WIRE -400 208 -400 160
    WIRE -256 224 -256 160
    WIRE 144 224 144 208
    WIRE -32 256 -32 224
    WIRE 64 272 64 160
    WIRE 160 272 64 272
    WIRE 288 272 160 272
    WIRE 400 272 352 272
    WIRE 512 272 512 96
    WIRE 512 272 480 272
    WIRE 64 288 64 272
    WIRE 160 288 160 272
    WIRE 752 288 752 256
    WIRE 880 288 752 288
    WIRE 928 288 880 288
    WIRE 928 320 928 288
    WIRE -96 336 -96 128
    WIRE -400 384 -400 288
    WIRE -400 384 -480 384
    WIRE 64 384 64 368
    WIRE 160 384 160 352
    WIRE 160 384 64 384
    WIRE -480 400 -480 384
    WIRE -400 400 -400 384
    WIRE -256 400 -256 288
    WIRE -256 400 -400 400
    WIRE 64 416 64 384
    WIRE 208 432 128 432
    WIRE 320 432 288 432
    WIRE 432 432 384 432
    WIRE 928 432 928 400
    WIRE 512 448 512 272
    WIRE 624 448 624 160
    WIRE -400 480 -400 400
    WIRE -256 496 -256 400
    WIRE 288 544 288 528
    WIRE 432 560 432 432
    WIRE 432 560 320 560
    WIRE 624 560 624 512
    WIRE 624 560 432 560
    WIRE -96 576 -96 416
    WIRE -48 576 -96 576
    WIRE 0 576 -48 576
    WIRE 128 576 128 432
    WIRE 128 576 80 576
    WIRE 192 576 128 576
    WIRE 256 576 192 576
    WIRE 432 592 320 592
    WIRE 512 592 512 512
    WIRE 512 592 432 592
    WIRE 624 592 624 560
    WIRE 704 592 624 592
    WIRE -96 624 -96 576
    WIRE -48 624 -48 576
    WIRE 288 624 288 608
    WIRE 512 624 512 592
    WIRE 704 624 704 592
    WIRE 432 640 432 592
    WIRE 624 640 624 592
    WIRE -400 656 -400 560
    WIRE -320 656 -400 656
    WIRE -256 656 -256 560
    WIRE -256 656 -320 656
    WIRE -96 736 -96 688
    WIRE -48 736 -48 688
    WIRE -48 736 -96 736
    WIRE 432 736 432 704
    WIRE 512 736 512 704
    WIRE 512 736 432 736
    WIRE 624 736 624 704
    WIRE 624 736 512 736
    WIRE 704 736 704 704
    WIRE 704 736 624 736
    WIRE -96 768 -96 736
    WIRE 432 768 432 736
    FLAG -480 400 0
    FLAG 288 528 V+
    FLAG 144 224 V-
    FLAG -320 160 V+
    FLAG -320 656 V-
    FLAG 880 288 output
    FLAG 144 32 V+
    FLAG 288 624 V-
    FLAG 432 768 0
    FLAG -32 256 0
    FLAG -32 -480 V+
    FLAG -32 -384 V-
    FLAG -256 0 0
    FLAG 400 -240 0
    FLAG 160 -240 0
    FLAG 64 416 0
    FLAG 336 -240 0
    FLAG -96 768 0
    FLAG 192 576 dc-trim
    FLAG 640 -512 0
    FLAG 48 -240 0
    FLAG 928 432 0
    SYMBOL voltage -400 192 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL res 496 256 R90
    WINDOW 0 1 52 VBottom 2
    WINDOW 3 33 45 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 10.5k
    SYMBOL cap 352 256 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 35 30 VTop 2
    SYMATTR InstName C8
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL res 112 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 384 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL njf -128 -176 R90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J113
    SYMBOL voltage -400 464 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.01
    SYMATTR InstName V2
    SYMATTR Value 6
    SYMBOL res 48 272 R0
    WINDOW 3 36 65 Left 2
    SYMATTR Value 10.5k
    SYMATTR InstName R10
    SYMBOL schottky 496 -288 R0
    WINDOW 3 -17 -26 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -112 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 82
    SYMBOL OpAmps\\LT1994 176 128 R0
    WINDOW 3 10 -65 Left 2
    WINDOW 0 11 -95 Left 2
    SYMATTR InstName U1
    SYMBOL schottky 528 448 M0
    WINDOW 3 52 -26 VRight 2
    WINDOW 0 -18 3 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D3
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL schottky 640 448 M0
    WINDOW 3 49 -26 VRight 2
    WINDOW 0 -21 4 Left 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D4
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 528 608 M0
    WINDOW 3 25 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R16
    SYMBOL res 720 608 M0
    WINDOW 3 27 87 Left 2
    SYMATTR Value 220k
    SYMATTR InstName R17
    SYMBOL res -112 -256 R0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 320 -384 R0
    WINDOW 0 -50 69 Left 2
    WINDOW 3 -54 98 Left 2
    SYMATTR InstName R13
    SYMATTR Value 220k
    SYMBOL res 464 -32 R90
    WINDOW 0 -1 60 VBottom 2
    WINDOW 3 32 57 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 600k
    SYMBOL res -80 -288 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL res -80 432 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 33k
    SYMBOL res 192 416 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R15
    SYMATTR Value 220
    SYMBOL res -16 560 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 10k
    SYMBOL cap 176 352 R180
    WINDOW 0 -37 41 Left 2
    WINDOW 3 -50 13 Left 2
    SYMATTR InstName C7
    SYMATTR Value 15n
    SYMATTR SpiceLine V=16 Irms=271m Rser=0.594318 Lser=0 mfg="KEMET" pn="C0603C153K4RAC" type="X7R"
    SYMBOL cap 720 128 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 100000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0.002 Lser=0 mfg="TDK" pn="C575OX5ROJI07M" type="X5R"
    SYMBOL res 736 160 R0
    SYMATTR InstName R18
    SYMATTR Value 600
    SYMBOL res 192 -400 R270
    WINDOW 0 35 55 VTop 2
    WINDOW 3 -6 55 VBottom 2
    SYMATTR InstName R12
    SYMATTR Value 220k
    SYMBOL cap 176 -352 M0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 48 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 -352 M0
    WINDOW 0 -32 51 Left 2
    WINDOW 3 -72 7 Left 2
    SYMATTR InstName C10
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 384 448 M270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C9
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 416 640 R0
    WINDOW 0 -37 6 Left 2
    WINDOW 3 -77 53 Left 2
    SYMATTR InstName C11
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap 608 640 R0
    WINDOW 0 -33 9 Left 2
    WINDOW 3 -72 51 Left 2
    SYMATTR InstName C12
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -272 224 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -79 48 Left 2
    SYMATTR InstName C1
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -272 496 R0
    WINDOW 0 -22 9 Left 2
    WINDOW 3 -75 50 Left 2
    SYMATTR InstName C2
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL cap -16 224 R180
    WINDOW 0 23 78 Left 2
    WINDOW 3 -74 78 Left 2
    SYMATTR InstName C4
    SYMATTR Value 10000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60J106ME15" type="X5R"
    SYMBOL diode -80 688 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D5
    SYMATTR Value 1N4148
    SYMBOL cap -64 688 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMATTR SpiceLine V=6.3 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM032R60J105ME05" type="X5R"
    SYMBOL OpAmps\\LT1678 -32 -432 M0
    WINDOW 0 -56 49 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2A
    SYMBOL diode 192 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D6
    SYMATTR Value 1N4148
    SYMBOL diode 272 -544 R90
    WINDOW 0 58 31 VBottom 2
    WINDOW 3 -28 34 VTop 2
    SYMATTR InstName D7
    SYMATTR Value 1N4148
    SYMBOL diode 352 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D8
    SYMATTR Value 1N4148
    SYMBOL diode 432 -544 R90
    WINDOW 0 58 27 VBottom 2
    WINDOW 3 -27 31 VTop 2
    SYMATTR InstName D9
    SYMATTR Value 1N4148
    SYMBOL diode 512 -544 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D10
    SYMATTR Value 1N4148
    SYMBOL schottky 608 -288 R0
    WINDOW 3 -16 -25 VRight 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D2
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -80 -560 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 3.3k
    SYMBOL res 32 -384 R0
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL diode 592 -544 R90
    WINDOW 0 59 29 VBottom 2
    WINDOW 3 -25 30 VTop 2
    SYMATTR InstName D11
    SYMATTR Value 1N4148
    SYMBOL res 912 304 R0
    SYMATTR InstName R19
    SYMATTR Value 600
    SYMBOL OpAmps\\LT1678 288 576 M0
    WINDOW 0 23 -47 Left 2
    WINDOW 3 19 37 Left 2
    SYMATTR InstName U2B
    SYMBOL cap 0 -688 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C3
    SYMATTR Value 47p
    SYMBOL res 336 -32 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R20
    SYMATTR Value 470k
    TEXT -496 696 Left 2 !.tran 0 350s 50s startup
    TEXT 72 -664 Left 2 ;R4 18k ten turn.
    TEXT 72 -640 Left 2 ;Adjust for correct gate voltage,
    TEXT 72 -616 Left 2 ;minimum distortion and good
    TEXT 72 -592 Left 2 ;settling time at power on.
    TEXT -328 40 Left 2 ;R3 150 ohm ten turn.
    TEXT -328 72 Left 2 ;Adjust for minimum distortion.
    TEXT 296 48 Left 2 ;R9 1Meg ten turn.
    TEXT 952 272 Left 2 ;1kHz, > 90dB harmonic purity
    TEXT 744 504 Left 2 ;Copyright Edward Rawde, Nov 2024.
    TEXT 744 536 Left 2 ;rawde dot edward at the popular email
    TEXT 744 472 Left 2 ;Not for commercial use.
    TEXT -448 -640 Left 2 ;1kHz sinewave oscillator,
    TEXT -448 -616 Left 2 ;> 90dB harmonic purity.
    TEXT 744 568 Left 2 ;service everyone uses for some reason.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Wed Nov 20 13:29:37 2024
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I've taken John May seriously, and reworked my phase shift oscillator to use three op amps, all with their non-inverting inputs
    tied to ground.

    The results aren't all that impressive, the lower harmonics are about 65dB below the fundamental. Start-up is slow - it takes
    about five seconds of simulation before the circuit settles down into steady state operation, and that after I dropped the
    integrating capacitor from 6.8uF to 680nF. The nice thing about the circuit is that I can explain what each bit is doing. I can
    see a few tweaks that might be worth trying.


    The simulation died after 3 seconds, as if insufficient gain to sustain oscillation.

    The circuit starts off by reducing gain. I think I can do something
    about that.

    You seem to have a lot of components.

    But I know what they all do.

    Are you sure you really need all those ferrites?

    No, but they are cheap, and op amps injecting hash into the power rails
    are never a good idea. Power supply rejection drops with frequency, and
    U1 in particular pulls spikes of current from the power rails twice per
    cycle.

    Here's my really definitely final final offering.

    A comfortable 90dB down at 2kHz and > 100 dB elsewhere.
    Also looks clean either side of 1kHz.
    Whether or not this has anything to do with reality I do not know.
    The diode stabilizer string will be temperature dependent,
    requiring readjustment of R4 and a total of three adjustments are needed. Only three op amps (two packages) are needed.

    I'll take a look at it.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Tue Nov 19 22:03:36 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I've taken John May seriously, and reworked my phase shift oscillator to use three op amps, all with their non-inverting inputs
    tied to ground.

    The results aren't all that impressive, the lower harmonics are about 65dB below the fundamental. Start-up is slow - it takes
    about five seconds of simulation before the circuit settles down into steady state operation, and that after I dropped the
    integrating capacitor from 6.8uF to 680nF. The nice thing about the circuit is that I can explain what each bit is doing. I can
    see a few tweaks that might be worth trying.


    The simulation died after 3 seconds, as if insufficient gain to sustain oscillation.

    The circuit starts off by reducing gain. I think I can do something about that.

    You seem to have a lot of components.

    But I know what they all do.

    Are you sure you really need all those ferrites?

    No, but they are cheap, and op amps injecting hash into the power rails are never a good idea. Power supply rejection drops with
    frequency, and U1 in particular pulls spikes of current from the power rails twice per cycle.

    Here's my really definitely final final offering.

    A comfortable 90dB down at 2kHz and > 100 dB elsewhere.
    Also looks clean either side of 1kHz.
    Whether or not this has anything to do with reality I do not know.
    The diode stabilizer string will be temperature dependent,
    requiring readjustment of R4 and a total of three adjustments are needed. >>> Only three op amps (two packages) are needed.

    I'll take a look at it.

    Simulate for 350 seconds? Don't collect data for the first 50 seconds?

    Simulate for 100 seconds will be enough but will still need a few hours.
    It takes at least 20 seconds to fully stabilize.


    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many components?
    My circuit has far fewer components than yours.


    __
    Bill Sloman, Sydney



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Bill Sloman on Wed Nov 20 13:55:22 2024
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message
    news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message
    news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I've taken John May seriously, and reworked my phase shift oscillator
    to use three op amps, all with their non-inverting inputs
    tied to ground.

    The results aren't all that impressive, the lower harmonics are about
    65dB below the fundamental. Start-up is slow - it takes
    about five seconds of simulation before the circuit settles down into
    steady state operation, and that after I dropped the
    integrating capacitor from 6.8uF to 680nF. The nice thing about the
    circuit is that I can explain what each bit is doing. I can
    see a few tweaks that might be worth trying.


    The simulation died after 3 seconds, as if insufficient gain to
    sustain oscillation.

    The circuit starts off by reducing gain. I think I can do something
    about that.

    You seem to have a lot of components.

    But I know what they all do.

    Are you sure you really need all those ferrites?

    No, but they are cheap, and op amps injecting hash into the power rails
    are never a good idea. Power supply rejection drops with frequency, and
    U1 in particular pulls spikes of current from the power rails twice per cycle.

    Here's my really definitely final final offering.

    A comfortable 90dB down at 2kHz and > 100 dB elsewhere.
    Also looks clean either side of 1kHz.
    Whether or not this has anything to do with reality I do not know.
    The diode stabilizer string will be temperature dependent,
    requiring readjustment of R4 and a total of three adjustments are needed.
    Only three op amps (two packages) are needed.

    I'll take a look at it.

    Simulate for 350 seconds? Don't collect data for the first 50 seconds?

    I've no idea why you are using the LT1994. The circuit doesn't have a
    common mode problem, so why are you using an op amp designed to deal
    with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V
    reference voltage there are lots of ways to do it with more precision
    and better temperature stability.

    __
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Thu Nov 21 01:00:57 2024
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development. >>
    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the
    gain around the three-amplifier ring tweaks both amplitude and frequency
    - with more gain a lower frequency signal can still propagate around the
    ring.

    I've got to find a mechanism that will separate amplitude from
    frequency. My copy of Williams and Taylor on electronic filter design
    may get perused again.
    __
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to sunaecoNoChoppedPork@gmail.com on Wed Nov 20 07:46:20 2024
    On Sun, 17 Nov 2024 02:01:25 +0000, JM
    <sunaecoNoChoppedPork@gmail.com> wrote:

    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    This is the simplest circuit I can come up with.
    Harmonics are more than 80dB down in simulation.
    FFT the last 30 seconds.
    There is only one harmonic stopping me claiming 90dB but the exact FFT result can depend
    on exactly how much output is selected for the FFT. You may see different results.

    If a prototype is ever built, attention to the type and quality of the capacitors used will be needed.
    Electrolytics are not intended. Put C1 and C2 near U1 supply pins.
    Also pay attention to the stability of +/- 6V.
    It would be nice to have a single 12V rail version but so far I can't get it to work.

    R1 and R2 and probably R7 should be easily changeable.
    R3 should be 220 ohm ten turn. R9 should be 1M ohm ten turn in series with 470k.

    I don't fully understand why the DC stabilization circuit through U2B achieves what it does
    and this makes me concerned about whether a real circuit would have the same behaviour.
    It was added when I noticed that the diodes D1 and D2 weren't contributing equally so I
    decided to try to derive a DC correction signal. This was originally connected to the FET source
    and then to R13. Since this is a DC correction signal I decided to try out the effect of
    connecting it to U1 Vocm and was amazed that this works as well as it does. >>>>If you disconnect R5, harmonics will not be more than 50dB down because D1 and D2 are no
    longer providing stable and equal contributions to the level control feedback.

    If you need even better performance then the circuit referenced by Bill Sloman can be used.
    https://www.google.com/search?q=AN132+purity
    NSL-32SR3 is not expensive and simulation models exist but LT1468 is expensive.

    Other references
    https://www.google.com/search?&q=The+field+effect+transistor+as+a+voltage+controlled+resistor

    https://www.google.com/search?&q=sine+wave+oscillator&udm=2


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    TEXT -624 272 Left 2 !.tran 0 300s 0s startup
    TEXT -1568 -728 Left 2 ;Edward Rawde's high purity 1kHz sinewave oscillator. 8 Nov 2024\n \nHarmonics are more than 80dB down in
    simulation.\nFFT the last 30 seconds.\nThere is only one harmonic stopping me claiming 90dB but the exact FFT result can
    depend\non
    exactly how much output is selected for the FFT. You may see different results.\n \nIf a prototype is ever built, pay attention to
    the type and quality of the capacitors used.\nElectrolytics are not intended. Put C1 and C2 near U1 supply pins.\nAlso pay
    attention
    to the stability of +/- 6V.\nIt would be nice to have a single 12V rail version but so far I can't get it to work.\n \nR1 and R2
    and
    probably R7 should be easily changeable.\nR3 should be 220 ohm ten turn. R9 should be 1M ohm ten turn in series with 470k.\n \nI
    don't fully understand why the DC stabilization circuit through U2B achieves what it does\nand this makes me concerned about
    whether
    a real circuit would have the same behaviour.\nIt was added when I noticed that the diodes D1 and D2 weren't contributing equally
    so
    I \ndecided to try to derive a DC correction signal. This was originally connected to the FET source\nand then to R13. Since this
    is
    a DC correction signal I decided to try out the effect of\nconnecting it to U1 Vocm and was amazed that this works as well as it
    does. \nIf you disconnect R5, harmonics will not be more than 50dB down because D1 and D2 are no\nlonger providing stable and
    equal
    contributions to the level control feedback.\n \nIf you need even better performance then the circuit referenced by Bill Sloman
    can
    be used.\nhttps://www.google.com/search?q=AN132+purity\nNSL-32SR3 is not expensive and simulation models exist but LT1468 is
    expensive.\n \nOther references\n >>>>\nhttps://www.google.com/search?&q=The+field+effect+transistor+as+a+voltage+controlled+resistor\n
    \nhttps://www.google.com/search?&q=sine+wave+oscillator&udm=2


    Using an NSL-32SR3 doesn't really gain you anything over a FET. If
    you keep |vds| much less than |Vt-vgs| in the circuit and compensate
    for the vds/2 variation on the gate drive the distortion levels
    produced will be lower than almost all opamps out there. Here's a
    link to a sim using an LDR.

    https://1drv.ms/f/c/1af24d72a509cd48/EkjNCaVyTfIggBrrAQAAAAABHXNKs52BoVHi7zaxKmdMMQ?e=oVD0JS

    I've added some 3rd harmonic distortion to a linear model to give
    distortion figures roughly in the ballpark of Fig 6 in the attached
    application note (for small signal swings across the device). In the
    oscillator o/p the 3rd is about 150dB down. If you use the linear LDR
    model, or a FET, it will be much the same. (The opamps used in the sim
    actually have distortions specs of about 130dB in reallity.)

    Thanks for that. I left it overnight for 100 seconds of simulation. It looks like it has better harmonic performance than my
    circuit.
    Why use two op amps in the oscillator instead of one like my circuit?

    Because of common mode (non)linearity. In most op-amps (especially
    older designs) the distortion generated by the common mode signal is >typically one to two orders of magnitude larger than the transfer
    distortion. If it is not clear from the data sheet, it is best to
    measure the CM performance or just assume that it's 40dB worse than
    the specified figure.

    To quote Jim Williams, "always invert."

    Just the ESD diodes are a distortion hazard. I've seen people
    bootstrap the power supplies to improve CMRR.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to john larkin on Wed Nov 20 17:36:18 2024
    john larkin <JL@gct.com> wrote:
    On Sun, 17 Nov 2024 02:01:25 +0000, JM
    <sunaecoNoChoppedPork@gmail.com> wrote:

    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snnnniiiiiipppp>

    Because of common mode (non)linearity. In most op-amps (especially
    older designs) the distortion generated by the common mode signal is
    typically one to two orders of magnitude larger than the transfer
    distortion. If it is not clear from the data sheet, it is best to
    measure the CM performance or just assume that it's 40dB worse than
    the specified figure.

    To quote Jim Williams, "always invert."

    “Except when you can’t.”

    Just the ESD diodes are a distortion hazard. I've seen people
    bootstrap the power supplies to improve CMRR.


    Pease has an article somewhere about how to measure CMR and PSR
    correctly—as he says, most of the obvious methods actually measure
    open-loop gain.

    Cheers

    Phil Hobbs



    --
    Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to sunaecoNoChoppedPork@gmail.com on Wed Nov 20 20:55:41 2024
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:rdtqjj9cbj8od0a7p4e99jfa2nsgf663r0@4ax.com...
    On Tue, 19 Nov 2024 20:59:04 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    I've taken John May seriously, and reworked my phase shift oscillator to use three op amps, all with their non-inverting inputs
    tied to ground.

    The results aren't all that impressive, the lower harmonics are about 65dB below the fundamental. Start-up is slow - it takes
    about five seconds of simulation before the circuit settles down into steady state operation, and that after I dropped the
    integrating capacitor from 6.8uF to 680nF. The nice thing about the circuit is that I can explain what each bit is doing. I can
    see a few tweaks that might be worth trying.


    The simulation died after 3 seconds, as if insufficient gain to sustain oscillation.

    You seem to have a lot of components.
    Are you sure you really need all those ferrites?

    Here's my really definitely final final offering.

    A comfortable 90dB down at 2kHz and > 100 dB elsewhere.
    Also looks clean either side of 1kHz.
    Whether or not this has anything to do with reality I do not know.
    The diode stabilizer string will be temperature dependent,
    requiring readjustment of R4 and a total of three adjustments are needed. >>Only three op amps (two packages) are needed.

    ..


    Thats a pretty unusual circuit. Was the original intent to create a
    balanced output?

    Actually it was so that the diodes feeding the level control circuit made equal contribution.
    Also I wanted to reduce component count if possible so I went looking for differential output op amps
    and found the LT1994. I wasn't very happy with the +/- 6V rail limitation but decided I could live with it.


    If you're trying to measure harmonics at a low level with ltspice you
    need to set it up correctly. You need to turn off the raw file
    compression (plotwinsize=0 option) and make sure the data is not
    stored as single precision (the default) by setting option numdgt > 6.
    Your also need to set the maximum timestep to something in the region
    of 1/1000 (or 1/2000) of the fundamental period. If there's
    convergence issues you might try setting vntol=1e-12 and reltol=1e-6,
    and possibly setting itl2-4 to about 1000.

    Thank you very much for this information. I learn something new about LTSpice every day.


    I tried your circuit with the dc servo removed (it was just
    complicating things) and changed the fet control a little. The fet
    your using isn't a great choice - look for something with a large
    pinchoff voltage and a large idss, and jig things so that it operates
    with vgs close to zero and with very little voltage swing across it.
    As it was you were operating it pretty much at pinchoff.

    I chose the J113 to be sure of sufficient gate control range since the output of the driving op amp isn't going to go below 6V in an
    LT1994 circuit.


    You dont need to run your sims for long as some others have said. A
    few cycles is all you need.

    That makes sense. If it's a continuous repeating signal then why would you need more than a few cycles as long as you wait for the
    circuit to settle?

    See if the attached runs for you. When
    doing the fft use a blackman-harris window, H2,H3 should be about -120,-150dBc.

    It runs fine and has the best performance I've seen so far in a simulation.

    You should test the LT1944 in isolation as it may not
    model distortion at all (most LT spice models are works of fiction).

    This is certainly a big concern.
    I likely won't get to build this circuit in reality but it wouldn't be a surprise to me if a real circuit has very different
    behaviour, particularly from a distortion point of view.


    There is an option in ltspice to stop it turning U's into mu.

    Where is it?

    Thank you very much for your contribution, it is much appreciated.

    My goal was to find out whether a very low distortion sinewave oscillator could be made without using lamps, thermistors or opto
    devices.

    Based on the circuit you posted and in an attempt to get rid of the LT1994 I used the two op amp oscillator from one of your
    previous posts and came up with the following circuit. It works but shows an issue at 2kHz not even 80dB down. What's causing that
    harmonic?

    You may want to shorten the simulation time and put initial conditions in.

    Version 4
    SHEET 1 2196 932
    WIRE 352 -592 256 -592
    WIRE 480 -592 416 -592
    WIRE 784 -592 672 -592
    WIRE 1072 -592 864 -592
    WIRE 1072 -560 1072 -592
    WIRE 256 -544 256 -592
    WIRE 256 -496 256 -544
    WIRE 352 -496 256 -496
    WIRE 480 -496 480 -592
    WIRE 480 -496 432 -496
    WIRE 1072 -464 1072 -480
    WIRE -192 -432 -192 -480
    WIRE 384 -384 384 -400
    WIRE 480 -368 480 -496
    WIRE 480 -368 416 -368
    WIRE 672 -368 672 -592
    WIRE 672 -368 480 -368
    WIRE 784 -368 672 -368
    WIRE 944 -368 864 -368
    WIRE 1168 -368 1008 -368
    WIRE 256 -352 256 -496
    WIRE 352 -352 256 -352
    WIRE 480 -336 416 -336
    WIRE 256 -304 256 -352
    WIRE 384 -304 384 -320
    WIRE 480 -304 480 -336
    WIRE -192 -256 -192 -352
    WIRE -192 -256 -272 -256
    WIRE -272 -240 -272 -256
    WIRE 448 -192 368 -192
    WIRE 560 -192 512 -192
    WIRE 960 -192 880 -192
    WIRE 1072 -192 1024 -192
    WIRE 256 -176 256 -224
    WIRE 256 -176 160 -176
    WIRE -192 -160 -192 -256
    WIRE 160 -112 160 -176
    WIRE 368 -96 368 -192
    WIRE 432 -96 368 -96
    WIRE 560 -96 560 -192
    WIRE 560 -96 512 -96
    WIRE 880 -96 880 -192
    WIRE 944 -96 880 -96
    WIRE 1072 -96 1072 -192
    WIRE 1072 -96 1024 -96
    WIRE 256 -32 256 -176
    WIRE 448 0 448 -16
    WIRE -192 16 -192 -80
    WIRE 160 16 160 -32
    WIRE 160 16 112 16
    WIRE 192 16 160 16
    WIRE 320 16 288 16
    WIRE 368 16 368 -96
    WIRE 368 16 320 16
    WIRE 416 16 368 16
    WIRE 960 16 960 0
    WIRE 560 32 560 -96
    WIRE 560 32 480 32
    WIRE 624 32 560 32
    WIRE 672 32 624 32
    WIRE 752 32 736 32
    WIRE 880 32 880 -96
    WIRE 880 32 832 32
    WIRE 928 32 880 32
    WIRE 416 48 368 48
    WIRE 1072 48 1072 -96
    WIRE 1072 48 992 48
    WIRE 1168 48 1168 -368
    WIRE 1168 48 1072 48
    WIRE 928 64 880 64
    WIRE 448 80 448 64
    WIRE 112 96 112 16
    WIRE 192 96 112 96
    WIRE 320 96 320 16
    WIRE 320 96 272 96
    WIRE 960 96 960 80
    WIRE 368 112 368 48
    WIRE 880 112 880 64
    WIRE 112 192 112 96
    WIRE 640 192 112 192
    WIRE 1168 192 1168 48
    WIRE 1168 192 720 192
    FLAG -272 -240 0
    FLAG -192 -480 V+
    FLAG -192 16 V-
    FLAG 384 -400 V+
    FLAG 384 -304 V-
    FLAG 480 -304 0
    FLAG 1072 -464 0
    FLAG 256 -544 vg
    FLAG 880 112 0
    FLAG 368 112 0
    FLAG 624 32 vout2
    FLAG 448 -16 V+
    FLAG 448 80 V-
    FLAG 960 0 V+
    FLAG 960 96 V-
    SYMBOL voltage -192 -448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR InstName V1
    SYMATTR Value 6
    SYMBOL njf 192 -32 M90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J113
    SYMBOL voltage -192 -176 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR InstName V2
    SYMATTR Value 6
    SYMBOL schottky 1008 -384 R90
    WINDOW 3 32 32 VTop 2
    WINDOW 0 0 32 VBottom 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 176 80 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 50
    SYMBOL res 176 -128 M0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL res 272 -208 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 1k
    SYMBOL OpAmps\\LT1678 384 -352 M0
    WINDOW 0 -56 49 Left 2
    WINDOW 3 -47 89 Left 2
    SYMATTR InstName U2A
    SYMBOL res 336 -480 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 880 -384 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL cap 416 -608 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C3
    SYMATTR Value 100
    SYMBOL res 880 -608 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R5
    SYMATTR Value 10K
    SYMBOL voltage 1072 -576 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V3
    SYMATTR Value -0.2
    SYMBOL res 1040 -112 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 16K
    SYMBOL res 848 16 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R12
    SYMATTR Value 8K
    SYMBOL cap 1024 -208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C2
    SYMATTR Value 10n
    SYMBOL cap 736 16 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C4
    SYMATTR Value 20n
    SYMBOL res 528 -112 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R13
    SYMATTR Value 10.02K
    SYMBOL cap 512 -208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C5
    SYMATTR Value 10p
    SYMBOL res 736 176 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 9870
    SYMBOL OpAmps\\LT1679 448 32 R0
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1679 960 48 R0
    SYMATTR InstName U4
    TEXT -496 136 Left 2 !.tran 0 200 0 1u uic
    TEXT -496 88 Left 2 !.options plotwinsize=0 numdgt=7 method=trap
    TEXT -248 -584 Left 2 ;1kHz sinewave oscillator. 20 Nov 2024.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Edward Rawde on Wed Nov 20 23:11:42 2024
    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vhm3uu$2214$1@nnrp.usenet.blueworldhosting.com...
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:rdtqjj9cbj8od0a7p4e99jfa2nsgf663r0@4ax.com...
    On Tue, 19 Nov 2024 20:59:04 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    Increasing R1 and R2 to 100k seems to fix the 2kHz harmonic problem.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Bill Sloman on Fri Nov 22 17:06:17 2024
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message
    news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message
    news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a
    common mode problem, so why are you using an op amp designed
    to deal with one?

    This is sci.electronics.design not
    sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V
    reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so
    then why are you using a circuit with so many components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the
    gain around the three-amplifier ring tweaks both amplitude and frequency
    - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from
    frequency. My copy of Williams and Taylor on electronic filter design
    may get perused again.

    I found a simpler solution - copy the relevant arrangement in John May's circuit. It did work - after a fashion - but as I got closer to getting
    it to a state where it could do what I wanted, the circuit got less and
    less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try to go
    the through the schematic to find and purge them. But the last few
    passes haven't shown up anything. Frustrating. My father's advice in
    similar situautions was to "drop it in drawer for six months, then take
    another look". It has worked in the past.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Fri Nov 22 11:32:13 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp
    designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the gain around the three-amplifier ring tweaks both amplitude
    and frequency - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from frequency. My copy of Williams and Taylor on electronic filter
    design may get perused again.

    I found a simpler solution - copy the relevant arrangement in John May's circuit. It did work - after a fashion - but as I got
    closer to getting it to a state where it could do what I wanted, the circuit got less and less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try to go the through the schematic to find and purge them. But the
    last few passes haven't shown up anything. Frustrating. My father's advice in similar situautions was to "drop it in drawer for
    six months, then take another look". It has worked in the past.


    I also found a simpler solution. Taking on board advice from JM and others.

    The circuit below does 0dB into 600 ohms and it only takes about 20 minutes to complete the simulation on my computer.

    When it's done, select a sample of about 1 second near the end and FFT.
    Select Use current zoom extent and Blackman-Harris window.

    It will say all harmonics are more than 120dB down.

    I'm not saying this level of performance is achievable or measurable in reality so I don't see any point simulating further.

    The actual distortion in reality will likely be that of the op amps so choose the lowest distortion op amp you can find.

    Oh and if you need to know the exact function of any of the 21 components in this circuit just ask.
    I'd feel embarrassed to have produced a circuit using over 70 components which only claims 65dB down on harmonics.

    Does anyone know how to change the default trace in LTSpice?
    When I click Run/pause it shows the wrong node so then I have to Delete This Trace and click output.
    How do I make it default to output?

    Version 4
    SHEET 1 2196 932
    WIRE 912 -816 912 -848
    WIRE 864 -800 704 -800
    WIRE 800 -720 800 -736
    WIRE 864 -704 864 -800
    WIRE 864 -704 832 -704
    WIRE 704 -688 704 -800
    WIRE 704 -688 640 -688
    WIRE 768 -688 704 -688
    WIRE 912 -672 912 -736
    WIRE 912 -672 832 -672
    WIRE 336 -640 256 -640
    WIRE 480 -640 400 -640
    WIRE 800 -640 800 -656
    WIRE 912 -624 912 -672
    WIRE 640 -592 640 -688
    WIRE 256 -544 256 -640
    WIRE 336 -544 256 -544
    WIRE 480 -544 480 -640
    WIRE 480 -544 416 -544
    WIRE 912 -528 912 -544
    WIRE -192 -432 -192 -480
    WIRE 384 -432 384 -448
    WIRE 480 -416 480 -544
    WIRE 480 -416 416 -416
    WIRE 640 -416 640 -512
    WIRE 640 -416 480 -416
    WIRE 848 -416 640 -416
    WIRE 992 -416 928 -416
    WIRE 1136 -416 1056 -416
    WIRE 256 -400 256 -544
    WIRE 288 -400 256 -400
    WIRE 352 -400 288 -400
    WIRE 464 -384 416 -384
    WIRE 464 -368 464 -384
    WIRE 384 -352 384 -368
    WIRE 256 -336 256 -400
    WIRE -192 -256 -192 -352
    WIRE -192 -256 -272 -256
    WIRE -272 -240 -272 -256
    WIRE 480 -192 416 -192
    WIRE 608 -192 544 -192
    WIRE 912 -192 848 -192
    WIRE 1040 -192 976 -192
    WIRE 208 -176 160 -176
    WIRE 256 -176 256 -256
    WIRE 256 -176 208 -176
    WIRE -192 -160 -192 -256
    WIRE 160 -128 160 -176
    WIRE 416 -96 416 -192
    WIRE 480 -96 416 -96
    WIRE 608 -96 608 -192
    WIRE 608 -96 560 -96
    WIRE 848 -96 848 -192
    WIRE 912 -96 848 -96
    WIRE 1040 -96 1040 -192
    WIRE 1040 -96 992 -96
    WIRE 256 -32 256 -176
    WIRE 496 0 496 -16
    WIRE -192 16 -192 -80
    WIRE 128 16 112 16
    WIRE 160 16 160 -48
    WIRE 160 16 128 16
    WIRE 192 16 160 16
    WIRE 320 16 288 16
    WIRE 416 16 416 -96
    WIRE 416 16 320 16
    WIRE 464 16 416 16
    WIRE 928 16 928 0
    WIRE 1136 16 1136 -416
    WIRE 1184 16 1136 16
    WIRE 1360 16 1264 16
    WIRE 1424 16 1360 16
    WIRE 608 32 608 -96
    WIRE 608 32 528 32
    WIRE 640 32 608 32
    WIRE 720 32 704 32
    WIRE 848 32 848 -96
    WIRE 848 32 800 32
    WIRE 896 32 848 32
    WIRE 464 48 416 48
    WIRE 1040 48 1040 -96
    WIRE 1040 48 960 48
    WIRE 1088 48 1040 48
    WIRE 1136 48 1136 16
    WIRE 1136 48 1088 48
    WIRE 416 64 416 48
    WIRE 896 64 848 64
    WIRE 496 80 496 64
    WIRE 848 80 848 64
    WIRE 1424 80 1424 16
    WIRE 112 96 112 16
    WIRE 192 96 112 96
    WIRE 320 96 320 16
    WIRE 320 96 272 96
    WIRE 928 96 928 80
    WIRE 1424 176 1424 160
    WIRE 112 224 112 96
    WIRE 640 224 112 224
    WIRE 1136 224 1136 48
    WIRE 1136 224 720 224
    FLAG -272 -240 0
    FLAG -192 -480 V+
    FLAG -192 16 V-
    FLAG 384 -448 V+
    FLAG 384 -352 V-
    FLAG 496 -16 V+
    FLAG 496 80 V-
    FLAG 928 0 V+
    FLAG 928 96 V-
    FLAG 208 -176 gate
    FLAG 128 16 fb
    FLAG 1088 48 out
    FLAG 848 80 0
    FLAG 800 -736 V+
    FLAG 800 -640 V-
    FLAG 912 -848 V+
    FLAG 912 -528 V-
    FLAG 416 64 0
    FLAG 464 -368 0
    FLAG 288 -400 gdrv
    FLAG 1424 176 0
    FLAG 1360 16 output
    SYMBOL voltage -192 -448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL njf 192 -32 M90
    WINDOW 0 -37 23 VRight 2
    WINDOW 3 -9 -3 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J113
    SYMBOL voltage -192 -176 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 10 0 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL schottky 1056 -432 R90
    WINDOW 3 32 32 VTop 2
    WINDOW 0 0 32 VBottom 2
    SYMATTR Value BAS40HY
    SYMATTR InstName D1
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 176 80 M90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 47
    SYMBOL res 176 -144 M0
    WINDOW 0 38 42 Left 2
    WINDOW 3 36 66 Left 2
    SYMATTR InstName R2
    SYMATTR Value 100k
    SYMBOL res 272 -240 R180
    WINDOW 0 40 70 Left 2
    WINDOW 3 45 42 Left 2
    SYMATTR InstName R1
    SYMATTR Value 100k
    SYMBOL res 320 -528 R270
    WINDOW 0 33 55 VTop 2
    WINDOW 3 -3 55 VBottom 2
    SYMATTR InstName R4
    SYMATTR Value 10k
    SYMBOL res 944 -432 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R6
    SYMATTR Value 10k
    SYMBOL cap 400 -656 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C3
    SYMATTR Value 100
    SYMATTR SpiceLine V=4 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM31CR60G107ME39" type="X5R"
    SYMBOL res 656 -496 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 10K
    SYMBOL res 1008 -112 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 16K
    SYMBOL res 816 16 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R12
    SYMATTR Value 8K
    SYMBOL cap 976 -208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C2
    SYMATTR Value 10n
    SYMBOL cap 704 16 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C4
    SYMATTR Value 20n
    SYMBOL res 576 -112 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R13
    SYMATTR Value 10.02K
    SYMBOL cap 544 -208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C5
    SYMATTR Value 10p
    SYMBOL res 736 208 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R14
    SYMATTR Value 9985
    SYMBOL OpAmps\\LT1679 496 32 R0
    SYMATTR InstName U1
    SYMBOL OpAmps\\LT1679 928 48 R0
    SYMATTR InstName U2
    SYMBOL OpAmps\\LT1679 384 -400 M0
    SYMATTR InstName U3
    SYMBOL OpAmps\\LT1679 800 -688 M0
    SYMATTR InstName U4
    SYMBOL res 896 -832 R0
    SYMATTR InstName R17
    SYMATTR Value 10k
    SYMBOL res 896 -640 R0
    SYMATTR InstName R18
    SYMATTR Value 12k
    SYMBOL res 1280 0 R90
    WINDOW 0 -4 57 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 600
    SYMBOL res 1440 176 R180
    WINDOW 0 47 75 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R8
    SYMATTR Value 600
    TEXT -496 136 Left 2 !.tran 0 30 0 1u uic
    TEXT -496 88 Left 2 !.options plotwinsize=0 numdgt=7 method=trap
    TEXT -296 -648 Left 2 ;1kHz low distortion sinewave oscillator.
    TEXT -288 -616 Left 2 ;21 Nov 2024.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Sat Nov 23 15:39:24 2024
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp
    designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the gain around the three-amplifier ring tweaks both amplitude
    and frequency - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from frequency. My copy of Williams and Taylor on electronic filter
    design may get perused again.

    I found a simpler solution - copy the relevant arrangement in John May's circuit. It did work - after a fashion - but as I got
    closer to getting it to a state where it could do what I wanted, the circuit got less and less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try to go the through the schematic to find and purge them. But the
    last few passes haven't shown up anything. Frustrating. My father's advice in similar situautions was to "drop it in drawer for
    six months, then take another look". It has worked in the past.

    I found that adding a couple of 14nmH ferrite beads around the
    transistors and the FETs stopped the simulation dropping out after
    getting stuck on a too-short time step.

    The current version isn't simulating all that fast - I let it run
    over-night and the amplitude control feed back loop turned out to have
    been underdamped to the point of instability - it kept on hitting the
    rails and overshooting back into them. The current version - with more
    damping - is now on it's second millisecond.

    I also found a simpler solution. Taking on board advice from JM and others.

    The circuit below does 0dB into 600 ohms and it only takes about 20 minutes to complete the simulation on my computer.

    When it's done, select a sample of about 1 second near the end and FFT. Select Use current zoom extent and Blackman-Harris window.

    It will say all harmonics are more than 120dB down.

    I'm not saying this level of performance is achievable or measurable in reality so I don't see any point simulating further.

    The actual distortion in reality will likely be that of the op amps so choose the lowest distortion op amp you can find.

    Oh and if you need to know the exact function of any of the 21 components in this circuit just ask.

    I'd feel embarrassed to have produced a circuit using over 70 components which only claims 65dB down on harmonics.

    Of course you would. The point of producing the circuit is to find out
    what it can do, and change it to make it work better. That way you get
    to understand what the circuit is doing and why it is doing it, which
    isn't your strong point.

    Does anyone know how to change the default trace in LTSpice?

    There isn't one in the version I downloaded. When I start a simulation I
    get offered a blank display, and have to select a trace to be displayed
    before I can see anything.

    When I click Run/pause it shows the wrong node so then I have to Delete This Trace and click output.
    How do I make it default to output?

    Beats me.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Sat Nov 23 15:52:28 2024
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't
    have a common mode problem, so why are you using an op amp
    designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if
    so then why are you using a circuit with so many components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking
    the gain around the three-amplifier ring tweaks both amplitude
    and frequency - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from
    frequency. My copy of Williams and Taylor on electronic filter
    design may get perused again.

    I found a simpler solution - copy the relevant arrangement in John
    May's circuit. It did work - after a fashion - but as I got
    closer to getting it to a state where it could do what I wanted, the circuit got less and less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try
    to go the through the schematic to find and purge them. But the
    last few passes haven't shown up anything. Frustrating. My father's
    advice in similar situautions was to "drop it in drawer for
    six months, then take another look". It has worked in the past.

    I found that adding a couple of 14uH ferrite beads around the
    transistors and the FET stopped the simulation dropping out after
    getting stuck on a too-short time step.

    The current version isn't simulating all that fast - I let it run
    over-night and the amplitude control feed-back loop turned out to have
    been underdamped to the point of instability - it kept on hitting the
    rails, recovering and overshooting back into them. The current version -
    with more damping - is now on it's second millisecond.

    I also found a simpler solution. Taking on board advice from JM and
    others.

    The circuit below does 0dB into 600 ohms and it only takes about 20
    minutes to complete the simulation on my computer.

    When it's done, select a sample of about 1 second near the end and FFT. Select Use current zoom extent and Blackman-Harris window.

    It will say all harmonics are more than 120dB down.

    I'm not saying this level of performance is achievable or measurable
    in reality so I don't see any point simulating further.

    The actual distortion in reality will likely be that of the op amps
    so choose the lowest distortion op amp you can find.

    Oh and if you need to know the exact function of any of the 21
    components in this circuit just ask.

    I'd feel embarrassed to have produced a circuit using over 70
    components which only claims 65dB down on harmonics.

    Of course you would. The point of producing the circuit is to find out
    what it can do, and change it to make it work better. That way you get
    to understand what the circuit is doing and why it is doing it, which
    isn't your strong point.

    Does anyone know how to change the default trace in LTSpice?

    There isn't one in the version I downloaded. When I start a simulation I
    get offered a blank display, and have to select a trace to be displayed
    before I can see anything.

    When I click Run/pause it shows the wrong node so then I have to
    Delete This Trace and click output.
    How do I make it default to output?

    Beats me.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sat Nov 23 00:12:07 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp
    designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many
    components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the gain around the three-amplifier ring tweaks both
    amplitude
    and frequency - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from frequency. My copy of Williams and Taylor on electronic filter
    design may get perused again.

    I found a simpler solution - copy the relevant arrangement in John May's circuit. It did work - after a fashion - but as I got
    closer to getting it to a state where it could do what I wanted, the circuit got less and less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try to go the through the schematic to find and purge them. But
    the
    last few passes haven't shown up anything. Frustrating. My father's advice in similar situautions was to "drop it in drawer for
    six months, then take another look". It has worked in the past.

    I found that adding a couple of 14nmH ferrite beads around the transistors and the FETs stopped the simulation dropping out after
    getting stuck on a too-short time step.

    The current version isn't simulating all that fast - I let it run over-night and the amplitude control feed back loop turned out
    to have been underdamped to the point of instability - it kept on hitting the rails and overshooting back into them. The current
    version - with more damping - is now on it's second millisecond.

    Ok well when you've got a circuit which rivals the one I posted for harmonic distortion and component count let me know.


    I also found a simpler solution. Taking on board advice from JM and others. >>
    The circuit below does 0dB into 600 ohms and it only takes about 20 minutes to complete the simulation on my computer.

    When it's done, select a sample of about 1 second near the end and FFT.
    Select Use current zoom extent and Blackman-Harris window.

    It will say all harmonics are more than 120dB down.

    I'm not saying this level of performance is achievable or measurable in reality so I don't see any point simulating further.

    The actual distortion in reality will likely be that of the op amps so choose the lowest distortion op amp you can find.

    Oh and if you need to know the exact function of any of the 21 components in this circuit just ask.

    I'd feel embarrassed to have produced a circuit using over 70 components which only claims 65dB down on harmonics.

    Of course you would. The point of producing the circuit is to find out what it can do, and change it to make it work better. That
    way you get to understand what the circuit is doing and why it is doing it, which isn't your strong point.

    Silly me. I thought that's what I'd been doing all along.


    Does anyone know how to change the default trace in LTSpice?

    There isn't one in the version I downloaded. When I start a simulation I get offered a blank display, and have to select a trace
    to be displayed before I can see anything.

    Same here. Therefore it has to be storing alternative behaviour in one of that files it creates.
    I have since found that this is a plt file.


    When I click Run/pause it shows the wrong node so then I have to Delete This Trace and click output.
    How do I make it default to output?

    Beats me.

    It turns out that the solution to this problem is to delete the plt file. However I don't know exactly what the circumstances are for this file to be created.



    --
    Bill Sloman, Sydney



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sat Nov 23 01:03:15 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp
    designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many
    components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the gain around the three-amplifier ring tweaks both
    amplitude
    and frequency - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from frequency. My copy of Williams and Taylor on electronic filter
    design may get perused again.

    I found a simpler solution - copy the relevant arrangement in John May's circuit. It did work - after a fashion - but as I got
    closer to getting it to a state where it could do what I wanted, the circuit got less and less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try to go the through the schematic to find and purge them. But
    the
    last few passes haven't shown up anything. Frustrating. My father's advice in similar situautions was to "drop it in drawer for
    six months, then take another look". It has worked in the past.

    I found that adding a couple of 14nmH ferrite beads around the transistors and the FETs stopped the simulation dropping out after
    getting stuck on a too-short time step.

    The current version isn't simulating all that fast - I let it run over-night and the amplitude control feed back loop turned out
    to have been underdamped to the point of instability - it kept on hitting the rails and overshooting back into them. The current
    version - with more damping - is now on it's second millisecond.

    I also found a simpler solution. Taking on board advice from JM and others. >>
    The circuit below does 0dB into 600 ohms and it only takes about 20 minutes to complete the simulation on my computer.

    When it's done, select a sample of about 1 second near the end and FFT.
    Select Use current zoom extent and Blackman-Harris window.

    It will say all harmonics are more than 120dB down.

    I'm not saying this level of performance is achievable or measurable in reality so I don't see any point simulating further.

    The actual distortion in reality will likely be that of the op amps so choose the lowest distortion op amp you can find.

    Oh and if you need to know the exact function of any of the 21 components in this circuit just ask.

    I'd feel embarrassed to have produced a circuit using over 70 components which only claims 65dB down on harmonics.

    Of course you would. The point of producing the circuit is to find out what it can do, and change it to make it work better. That
    way you get to understand what the circuit is doing and why it is doing it, which isn't your strong point.

    Does anyone know how to change the default trace in LTSpice?

    There isn't one in the version I downloaded. When I start a simulation I get offered a blank display, and have to select a trace
    to be displayed before I can see anything.

    When I click Run/pause it shows the wrong node so then I have to Delete This Trace and click output.
    How do I make it default to output?

    Beats me.

    Aha I must have accidentally saved the plot settings somehow.
    Right click the plot and choose file.
    If you save plot settings it does just that.


    --
    Bill Sloman, Sydney



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Sat Nov 23 18:49:18 2024
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp
    designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many
    components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the gain around the three-amplifier ring tweaks both
    amplitude
    and frequency - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from frequency. My copy of Williams and Taylor on electronic filter
    design may get perused again.

    I found a simpler solution - copy the relevant arrangement in John May's circuit. It did work - after a fashion - but as I got
    closer to getting it to a state where it could do what I wanted, the circuit got less and less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try to go the through the schematic to find and purge them. But
    the
    last few passes haven't shown up anything. Frustrating. My father's advice in similar situautions was to "drop it in drawer for
    six months, then take another look". It has worked in the past.

    I found that adding a couple of 14nmH ferrite beads around the transistors and the FETs stopped the simulation dropping out after
    getting stuck on a too-short time step.

    The current version isn't simulating all that fast - I let it run over-night and the amplitude control feed back loop turned out
    to have been underdamped to the point of instability - it kept on hitting the rails and overshooting back into them. The current
    version - with more damping - is now on it's second millisecond.

    Ok well when you've got a circuit which rivals the one I posted for harmonic distortion and component count let me know.

    Component count isn't all that important. If you can replace an
    expensive or hard to get component with a couple of cheap ones, that's a
    win.

    Alternative ways of doing much the same job are also interesting -
    patent evasion used to be a popular sport. Once the patentable details
    are buried inside a programmable device it's less worthwhile.

    Lawyers don't like going into technical detail - RCA won a colour TV
    patent case against EMI in a US Court because the judges couldn't be
    persuaded that quadrature modulation was exactly the same thing as
    sine/cosine modulation.

    I also found a simpler solution. Taking on board advice from JM and others. >>>
    The circuit below does 0dB into 600 ohms and it only takes about 20 minutes to complete the simulation on my computer.

    When it's done, select a sample of about 1 second near the end and FFT.
    Select Use current zoom extent and Blackman-Harris window.

    It will say all harmonics are more than 120dB down.

    I'm not saying this level of performance is achievable or measurable in reality so I don't see any point simulating further.

    The actual distortion in reality will likely be that of the op amps so choose the lowest distortion op amp you can find.

    Oh and if you need to know the exact function of any of the 21 components in this circuit just ask.

    I'd feel embarrassed to have produced a circuit using over 70 components which only claims 65dB down on harmonics.

    Of course you would. The point of producing the circuit is to find out what it can do, and change it to make it work better. That
    way you get to understand what the circuit is doing and why it is doing it, which isn't your strong point.

    Silly me. I thought that's what I'd been doing all along.

    Perhaps.

    Does anyone know how to change the default trace in LTSpice?

    There isn't one in the version I downloaded. When I start a simulation I get offered a blank display, and have to select a trace
    to be displayed before I can see anything.

    Same here. Therefore it has to be storing alternative behaviour in one of that files it creates.
    I have since found that this is a plt file.


    When I click Run/pause it shows the wrong node so then I have to Delete This Trace and click output.
    How do I make it default to output?

    Beats me.

    It turns out that the solution to this problem is to delete the plt file. However I don't know exactly what the circumstances are for this file to be created.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sat Nov 23 13:11:15 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhs1ea$1kbt4$1@dont-email.me...
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp
    designed
    to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with
    more
    precision and better temperature stability.

    In that case please show a circuit with better performance.
    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many
    components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the gain around the three-amplifier ring tweaks both
    amplitude
    and frequency - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from frequency. My copy of Williams and Taylor on electronic filter
    design may get perused again.

    I found a simpler solution - copy the relevant arrangement in John May's circuit. It did work - after a fashion - but as I got
    closer to getting it to a state where it could do what I wanted, the circuit got less and less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try to go the through the schematic to find and purge them. But
    the
    last few passes haven't shown up anything. Frustrating. My father's advice in similar situautions was to "drop it in drawer
    for
    six months, then take another look". It has worked in the past.

    I found that adding a couple of 14nmH ferrite beads around the transistors and the FETs stopped the simulation dropping out
    after
    getting stuck on a too-short time step.

    The current version isn't simulating all that fast - I let it run over-night and the amplitude control feed back loop turned out
    to have been underdamped to the point of instability - it kept on hitting the rails and overshooting back into them. The current
    version - with more damping - is now on it's second millisecond.

    Ok well when you've got a circuit which rivals the one I posted for harmonic distortion and component count let me know.

    Component count isn't all that important. If you can replace an expensive or hard to get component with a couple of cheap ones,
    that's a win.

    I've worked in plenty of places where using four times as many components as you could have used (and hence four times the cost)
    would not be seen as a win.


    Alternative ways of doing much the same job are also interesting -

    Sure. There are plenty of examples of that, such as make it a beam tetrode instead of a pentode.

    patent evasion used to be a popular sport. Once the patentable details are buried inside a programmable device it's less
    worthwhile.

    Lawyers don't like going into technical detail - RCA won a colour TV patent case against EMI in a US Court because the judges
    couldn't be persuaded that quadrature modulation was exactly the same thing as sine/cosine modulation.

    Sony didn't care about the PAL patents. They just put a hue control on their early sets.


    I also found a simpler solution. Taking on board advice from JM and others.

    The circuit below does 0dB into 600 ohms and it only takes about 20 minutes to complete the simulation on my computer.

    When it's done, select a sample of about 1 second near the end and FFT. >>>> Select Use current zoom extent and Blackman-Harris window.

    It will say all harmonics are more than 120dB down.

    I'm not saying this level of performance is achievable or measurable in reality so I don't see any point simulating further.

    The actual distortion in reality will likely be that of the op amps so choose the lowest distortion op amp you can find.

    Oh and if you need to know the exact function of any of the 21 components in this circuit just ask.

    I'd feel embarrassed to have produced a circuit using over 70 components which only claims 65dB down on harmonics.

    Of course you would. The point of producing the circuit is to find out what it can do, and change it to make it work better.
    That
    way you get to understand what the circuit is doing and why it is doing it, which isn't your strong point.

    Silly me. I thought that's what I'd been doing all along.

    Perhaps.

    Does anyone know how to change the default trace in LTSpice?

    There isn't one in the version I downloaded. When I start a simulation I get offered a blank display, and have to select a trace
    to be displayed before I can see anything.

    Same here. Therefore it has to be storing alternative behaviour in one of that files it creates.
    I have since found that this is a plt file.


    When I click Run/pause it shows the wrong node so then I have to Delete This Trace and click output.
    How do I make it default to output?

    Beats me.

    It turns out that the solution to this problem is to delete the plt file.
    However I don't know exactly what the circumstances are for this file to be created.

    --
    Bill Sloman, Sydney



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From ehsjr@21:1/5 to Edward Rawde on Sat Nov 23 18:13:43 2024
    On 11/23/2024 1:11 PM, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhs1ea$1kbt4$1@dont-email.me...

    <snip>
    Component count isn't all that important. If you can replace an expensive or hard to get component with a couple of cheap ones,
    that's a win.

    I've worked in plenty of places where using four times as many components as you could have used (and hence four times the cost)
    would not be seen as a win.

    Right. And sometimes saving space/weight trumps saving cost,
    so fewer components at increased $ expense is a win.

    Ed

    <snip>

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sun Nov 24 01:10:39 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhue9h$243sl$1@dont-email.me...
    On 24/11/2024 5:11 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhs1ea$1kbt4$1@dont-email.me...
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde" >>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    ...

    I found that adding a couple of 14nmH ferrite beads around the transistors and the FETs stopped the simulation dropping out
    after getting stuck on a too-short time step.

    Additional components in the simulation that you could probably leave out of a real circuit. I've found another place to put a
    ferrite bead which speeds up the simulation ever more, but it is till not all that quick.

    The current version isn't simulating all that fast - I let it run over-night and the amplitude control feed back loop turned
    out
    to have been underdamped to the point of instability - it kept on hitting the rails and overshooting back into them. The
    current
    version - with more damping - is now on it's second millisecond.

    Ok well when you've got a circuit which rivals the one I posted for harmonic distortion and component count let me know.

    I'm not going to be constrained by that.

    Ok I'll settle for matching the harmonic distortion level, even if you need 1000 components.


    Component count isn't all that important. If you can replace an expensive or hard to get component with a couple of cheap ones,
    that's a win.

    I've worked in plenty of places where using four times as many components as you could have used (and hence four times the cost)
    would not be seen as a win.

    Four times the number of components isn't four times the cost, as I did point out. I got brownie points once for replacing a fifty
    pence 25-turn trimming potentiometer with a more settable trimmer with the same footprint at five times the cost.

    What we lost on the cost of the part we more than won back in a half-hour drop in setting up time. The original designer should
    have put in coarse and fine pots, which would have been more parts, but still cheaper than my quick and dirty fix.
    Alternative ways of doing much the same job are also interesting -

    Sure. There are plenty of examples of that, such as make it a beam tetrode instead of a pentode.

    patent evasion used to be a popular sport. Once the patentable details are buried inside a programmable device it's less
    worthwhile.

    Lawyers don't like going into technical detail - RCA won a colour TV patent case against EMI in a US Court because the judges
    couldn't be persuaded that quadrature modulation was exactly the same thing as sine/cosine modulation.

    Sony didn't care about the PAL patents. They just put a hue control on their early sets.

    The EMI-RCA court battle preceded PAL versus NTSC. It was about how you added colour information on top of the original black and
    white brightness signal.

    We all know that Bill.
    In any case NTSC (which uses quadrature) and PAL (which also uses quadrature along with an additional trick or two) and probably
    also SECAM (which uses FM) are all history now unless you need to generate a signal locally for an existing set.


    ...

    <snip>

    --
    Bill Sloman, Sydney



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Sun Nov 24 16:41:04 2024
    On 24/11/2024 5:11 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhs1ea$1kbt4$1@dont-email.me...
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde" >>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    <snip>

    I've no idea why you are using the LT1994. The circuit doesn't have a common mode problem, so why are you using an op amp
    designed to deal with one?

    This is sci.electronics.design not sci.electronics.incremental-development.

    And the six diode "stabiliser string" is nuts. If you need a 3.6V reference voltage there are lots of ways to do it with
    more precision and better temperature stability.

    In that case please show a circuit with better performance.

    I'm working on it. Since we don't trust the spice models to get the
    distortion exactly right, it's not a particularly well-chosen target.

    It may be that some of the circuits JM posted can do better but if so then why are you using a circuit with so many
    components?
    My circuit has far fewer components than yours.

    But you don't seem to be able to tell us what they do.

    I think I've found my conceptual problem with my circuit. Tweaking the gain around the three-amplifier ring tweaks both
    amplitude
    and frequency - with more gain a lower frequency signal can still propagate around the ring.

    I've got to find a mechanism that will separate amplitude from frequency. My copy of Williams and Taylor on electronic filter
    design may get perused again.

    I found a simpler solution - copy the relevant arrangement in John May's circuit. It did work - after a fashion - but as I got
    closer to getting it to a state where it could do what I wanted, the circuit got less and less willing to simulate.

    I suspect an accumulation of typo's in component values - I do try to go the through the schematic to find and purge them. But
    the last few passes haven't shown up anything. Frustrating. My father's advice in similar situautions was to "drop it in drawer
    for six months, then take another look". It has worked in the past.

    I found that adding a couple of 14nmH ferrite beads around the transistors and the FETs stopped the simulation dropping out
    after getting stuck on a too-short time step.

    Additional components in the simulation that you could probably leave
    out of a real circuit. I've found another place to put a ferrite bead
    which speeds up the simulation ever more, but it is till not all that quick.

    The current version isn't simulating all that fast - I let it run over-night and the amplitude control feed back loop turned out
    to have been underdamped to the point of instability - it kept on hitting the rails and overshooting back into them. The current
    version - with more damping - is now on it's second millisecond.

    Ok well when you've got a circuit which rivals the one I posted for harmonic distortion and component count let me know.

    I'm not going to be constrained by that.

    Component count isn't all that important. If you can replace an expensive or hard to get component with a couple of cheap ones,
    that's a win.

    I've worked in plenty of places where using four times as many components as you could have used (and hence four times the cost)
    would not be seen as a win.

    Four times the number of components isn't four times the cost, as I did
    point out. I got brownie points once for replacing a fifty pence 25-turn trimming potentiometer with a more settable trimmer with the same
    footprint at five times the cost.

    What we lost on the cost of the part we more than won back in a
    half-hour drop in setting up time. The original designer should have put
    in coarse and fine pots, which would have been more parts, but still
    cheaper than my quick and dirty fix.
    Alternative ways of doing much the same job are also interesting -

    Sure. There are plenty of examples of that, such as make it a beam tetrode instead of a pentode.

    patent evasion used to be a popular sport. Once the patentable details are buried inside a programmable device it's less
    worthwhile.

    Lawyers don't like going into technical detail - RCA won a colour TV patent case against EMI in a US Court because the judges
    couldn't be persuaded that quadrature modulation was exactly the same thing as sine/cosine modulation.

    Sony didn't care about the PAL patents. They just put a hue control on their early sets.

    The EMI-RCA court battle preceded PAL versus NTSC. It was about how you
    added colour information on top of the original black and white
    brightness signal.

    I also found a simpler solution. Taking on board advice from JM and others.

    The circuit below does 0dB into 600 ohms and it only takes about 20 minutes to complete the simulation on my computer.

    When it's done, select a sample of about 1 second near the end and FFT. >>>>> Select Use current zoom extent and Blackman-Harris window.

    It will say all harmonics are more than 120dB down.

    I'm not saying this level of performance is achievable or measurable in reality so I don't see any point simulating further.

    John May claims to have observed it in reality. I trust him on that.

    The actual distortion in reality will likely be that of the op amps so choose the lowest distortion op amp you can find.

    Oh and if you need to know the exact function of any of the 21 components in this circuit just ask.

    But you haven't actually answered when I have.

    I'd feel embarrassed to have produced a circuit using over 70 components which only claims 65dB down on harmonics.

    Of course you would. The point of producing the circuit is to find out what it can do, and change it to make it work better.
    That way you get to understand what the circuit is doing and why it is doing it, which isn't your strong point.

    Silly me. I thought that's what I'd been doing all along.

    Perhaps.

    <snip>

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Mon Nov 25 13:02:12 2024
    On 24/11/2024 5:10 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhue9h$243sl$1@dont-email.me...
    On 24/11/2024 5:11 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhs1ea$1kbt4$1@dont-email.me...
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde" >>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    ...

    I found that adding a couple of 14nmH ferrite beads around the transistors and the FETs stopped the simulation dropping out
    after getting stuck on a too-short time step.

    Additional components in the simulation that you could probably leave out of a real circuit. I've found another place to put a
    ferrite bead which speeds up the simulation ever more, but it is till not all that quick.

    The current version isn't simulating all that fast - I let it run over-night and the amplitude control feed back loop turned
    out
    to have been underdamped to the point of instability - it kept on hitting the rails and overshooting back into them. The
    current
    version - with more damping - is now on it's second millisecond.

    Ok well when you've got a circuit which rivals the one I posted for harmonic distortion and component count let me know.

    I'm not going to be constrained by that.

    Ok I'll settle for matching the harmonic distortion level, even if you need 1000 components.

    The current version has the second harmonic 103dB below the fundamental,
    the third harmonic 80dB down. I had to run it over-nigh to get a couple
    of seconds of operation - the second second looked good.

    A couple of millivolts of second harmonic makes it through to the FET
    gate from the full-wave rectifier. If I can lag it by another 156usec it
    may reduce the harmonic content, rather than increasing it.
    So far the revised circuit has only clocked up 4msec of operation. Maybe
    I'll have more tomorrow.

    I haven't bothered counting the components. Some of them could be
    ditched when the design gets closer to a definitive version. The three transistors get around a potential output swing limitation which
    probably won't be a problem.

    --
    Bill Sloman, Sydney



    --
    Bill Sloman, Sydney





    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Bill Sloman on Tue Nov 26 15:32:38 2024
    On 25/11/2024 1:02 pm, Bill Sloman wrote:
    On 24/11/2024 5:10 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhue9h$243sl$1@dont-email.me...
    On 24/11/2024 5:11 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhs1ea$1kbt4$1@dont-email.me...
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message >>>>>>>>>>>>>> news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message >>>>>>>>>>>>>>>> news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com... >>>>>>>>>>>>>>>>> On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message >>>>>>>>>>>>>>>>>> news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com... >>>>>>>>>>>>>>>>>>> On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    <snip>

    The current version has been running overnight and has got to three
    seconds, and the DFT from 2.8 to three seconds shows third harmonic
    about 90db below the fundamental. The noise floor is about 100dB down
    and the other harmonics are barely visible above it.

    Here's the .asc file. There are extra components put in to make it
    simulate faster - L1 and L14 are the obvious examples, but L10, L11 and
    L12 got put in for the same reason. I suspect that if I had put in
    equivalent series resistance and inductance for C22 as well as for C6
    and C15 I might not have needed some of them.

    There is some other tidying up I could do, and that should get get the simulation speed up. I got a new circuit from John May last night, and
    it not only spits out a very clean sine wave but also simulated very
    fast. I forgot to put it on solid state disk before I ran it, and it
    took as long to get one of the waveforms off the spinning hard disk as
    it had done to run the simulation.

    Ny tidying up is going to wait until I've got ten seconds worth of
    simulation out of the current circuit, and can look at the details of
    what's going on deep in the circuit

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    SYMBOL res -1776 -1744 R0
    WINDOW 0 43 37 Left 2
    WINDOW 3 47 73 Left 2
    SYMATTR InstName R25
    SYMATTR Value 6.8k
    SYMATTR SpiceLine tol=0.1
    SYMBOL pnp -1824 -1440 M180
    SYMATTR InstName Q3
    SYMATTR Value BC557B
    SYMBOL res -1888 -1664 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R27
    SYMATTR Value 18k
    SYMATTR SpiceLine tol=1
    SYMBOL res -1888 -1024 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R28
    SYMATTR Value 6.8k
    SYMATTR SpiceLine tol=1
    SYMBOL cap -1856 -1456 R0
    WINDOW 0 28 4 Left 2
    WINDOW 3 21 62 Left 2
    SYMATTR InstName C3
    SYMATTR Value 100n
    SYMBOL OpAmps\\opamp2 -1408 -1792 M0
    WINDOW 3 10 108 Left 2
    SYMATTR Value LME49710
    SYMATTR InstName U8
    SYMATTR SpiceModel LME49710
    SYMBOL res -160 -1600 R270
    WINDOW 0 27 56 VTop 2
    WINDOW 3 5 56 VBottom 2
    SYMATTR InstName R26
    SYMATTR Value 10.7k
    SYMATTR SpiceLine tol=1
    SYMBOL res -768 -1728 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R5
    SYMATTR Value 4.87k
    SYMATTR SpiceLine tol=1
    SYMBOL cap -784 -1584 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C19
    SYMATTR Value 10p
    SYMBOL FerriteBead 208 -672 R0
    SYMATTR InstName L5
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL FerriteBead 208 -2128 R0
    SYMATTR InstName L6
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL cap 320 -1968 R0
    WINDOW 0 -60 15 Left 2
    WINDOW 3 -62 54 Left 2
    SYMATTR InstName C20
    SYMATTR Value 100n
    SYMBOL cap -96 -816 R0
    WINDOW 0 -60 15 Left 2
    WINDOW 3 -62 54 Left 2
    SYMATTR InstName C22
    SYMATTR Value 100n
    SYMBOL njf -1376 -1584 R0
    SYMATTR InstName J1
    SYMATTR Value MMBF4391
    SYMBOL References\\LTC6655-1.25 1232 -1120 R0
    SYMATTR InstName U4
    SYMBOL OpAmps\\opamp2 -656 -1504 R0
    WINDOW 3 13 108 Left 2
    SYMATTR Value LME49710
    SYMATTR InstName U9
    SYMATTR SpiceModel LME49710
    SYMBOL FerriteBead -1760 -880 R0
    SYMATTR InstName L10
    SYMATTR Value 14µ
    SYMATTR SpiceLine Ipk=3 Rser=0.0122 Rpar=870 Cpar=1000f mfg="Würth
    Elektronik" pn="7427503 WE-UKW 40060"
    SYMBOL FerriteBead -1568 -880 R0
    SYMATTR InstName L11
    SYMATTR Value 14µ
    SYMATTR SpiceLine Ipk=3 Rser=0.0122 Rpar=870 Cpar=1000f mfg="Würth
    Elektronik" pn="7427503 WE-UKW 40060"
    SYMBOL FerriteBead -1760 -1600 R0
    SYMATTR InstName L12
    SYMATTR Value 14µ
    SYMATTR SpiceLine Ipk=3 Rser=0.0122 Rpar=870 Cpar=1000f mfg="Würth
    Elektronik" pn="7427503 WE-UKW 40060"
    SYMBOL res -1200 -1664 R0
    WINDOW 0 41 37 Left 2
    WINDOW 3 36 71 Left 2
    SYMATTR InstName R7
    SYMATTR Value 390
    SYMATTR SpiceLine tol=0.1
    SYMBOL cap -64 -1824 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C9
    SYMATTR Value 10p
    SYMBOL FerriteBead 576 -1936 R0
    SYMATTR InstName L13
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL res -944 -1728 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R6
    SYMATTR Value 82
    SYMATTR SpiceLine tol=1
    SYMBOL res 1120 -1792 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 51k
    SYMBOL cap 1184 -1728 R0
    SYMATTR InstName C12
    SYMATTR Value 15n
    SYMBOL FerriteBead 496 -816 R90
    WINDOW 0 -16 0 VBottom 2
    SYMATTR InstName L14
    SYMATTR Value 1000n
    SYMATTR SpiceLine Ipk=0.2 Rser=0.562 Rpar=750 Cpar=350f mfg="Würth
    Elektronik" pn="782422601 WE-CBA 0402"
    SYMBOL cap 704 -1088 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C13
    SYMATTR Value 10p
    TEXT -1424 -776 Left 2 !.MODEL BAS70L D \n+ IS = 3.22E-9 \n+ N = 1.018
    \n+ BV = 77 \n+ IBV = 1.67E-7 \n+ RS = 20.89 \n+ CJO = 1.608E-12 \n+ VJ
    = 0.3891 \n+ M = 0.3683 \n+ FC = 0.5 \n+ EG = 0.69 \n+ XTI = 2 \n.ENDS
    TEXT -336 -528 Left 2 ;R2 a,b,c, Vishay Beschlag ACAS06S0830372P1AT
    precision 10k resistor array \n R1a, R1b Maxim MAX5492LB10000+T 10K
    resistive divider in a SOT-23-5 package
    TEXT -720 -464 Left 2 !.MODEL MMBF4391 NJF VTO=-4.6 BETA=0.02779
    LAMBDA=0.00595 RD=1 RS=1 IS=1e-14 CGD=14p CGS=10.5p PB=1 B=1 KF=1e-18
    AF=1 FC=0.5 mfg=Motorola
    TEXT -720 -408 Left 2 !.lib LME49710.lib
    TEXT -2000 -392 Left 2 !.tran 0 10s 0s startup

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Tue Nov 26 21:52:13 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vi3j1k$3aiv6$1@dont-email.me...
    On 25/11/2024 1:02 pm, Bill Sloman wrote:
    On 24/11/2024 5:10 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhue9h$243sl$1@dont-email.me...
    On 24/11/2024 5:11 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhs1ea$1kbt4$1@dont-email.me...
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com...
    On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com...
    On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    <snip>

    The current version has been running overnight and has got to three seconds, and the DFT from 2.8 to three seconds shows third
    harmonic about 90db below the fundamental. The noise floor is about 100dB down and the other harmonics are barely visible above
    it.

    Here's the .asc file. There are extra components put in to make it simulate faster - L1 and L14 are the obvious examples, but L10,
    L11 and L12 got put in for the same reason. I suspect that if I had put in equivalent series resistance and inductance for C22 as
    well as for C6 and C15 I might not have needed some of them.

    There is some other tidying up I could do, and that should get get the simulation speed up. I got a new circuit from John May last
    night, and it not only spits out a very clean sine wave but also simulated very fast. I forgot to put it on solid state disk
    before I ran it, and it took as long to get one of the waveforms off the spinning hard disk as it had done to run the simulation.

    Ny tidying up is going to wait until I've got ten seconds worth of simulation out of the current circuit, and can look at the
    details of what's going on deep in the circuit


    After running the simulation to 10 seconds I get 80dB down at 3kHz with an FFT on a sample of the last second and a Blackman-Harris
    window.
    Looks like the noise level either side of 1kHz may be higher than that.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to All on Thu Nov 28 02:08:03 2024
    On 27/11/2024 7:48 pm, JM wrote:
    On Tue, 26 Nov 2024 15:32:38 +1100, Bill Sloman <bill.sloman@ieee.org>
    wrote:

    On 25/11/2024 1:02 pm, Bill Sloman wrote:
    On 24/11/2024 5:10 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhue9h$243sl$1@dont-email.me...
    On 24/11/2024 5:11 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhs1ea$1kbt4$1@dont-email.me...
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message >>>>>>>>>>>>> news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message >>>>>>>>>>>>>>>> news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote:
    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message >>>>>>>>>>>>>>>>>> news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com... >>>>>>>>>>>>>>>>>>> On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message >>>>>>>>>>>>>>>>>>>> news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com... >>>>>>>>>>>>>>>>>>>>> On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    <snip>

    The current version has been running overnight and has got to three
    seconds, and the DFT from 2.8 to three seconds shows third harmonic
    about 90db below the fundamental. The noise floor is about 100dB down
    and the other harmonics are barely visible above it.

    Here's the .asc file. There are extra components put in to make it
    simulate faster - L1 and L14 are the obvious examples, but L10, L11 and
    L12 got put in for the same reason. I suspect that if I had put in
    equivalent series resistance and inductance for C22 as well as for C6
    and C15 I might not have needed some of them.

    There is some other tidying up I could do, and that should get get the
    simulation speed up. I got a new circuit from John May last night, and
    it not only spits out a very clean sine wave but also simulated very
    fast. I forgot to put it on solid state disk before I ran it, and it
    took as long to get one of the waveforms off the spinning hard disk as
    it had done to run the simulation.

    <snipped LTSpice .asc file.>

    When evaluating architecture there's little to be gained by using a complicated opamp model. Use a simple 1 or 2 pole model to begin
    with.

    Try the attached file, I've used a simple model to speed up the
    simulation, and made a slight circuit change. This shows the
    harmonics due to the control loop to be sub 130dBc. Of course the
    amplifier harmonic distortion is not simulated, but neither was it in
    the simulation by Mr Rawde.

    Thanks for that. I've got it into a form that my copy of LTSpice
    recognises as a .asc file, so I have looked at it.

    I haven't run it yet because I'm running yet another variant of the
    circuit, which has got to 2.4 seconds, and I'll leave it running overnight.

    I'm currently curious about the effect of the phase of the 2kHz
    component in the control signal (coming from my full-wave rectifier),
    and a fast simulating version of the circuit is just what I need to get
    that sorted out. I had thought that that it would be trivial to get the
    phase right, but my first attempt didn't get close.

    I could go mad and put a version of the circuit into KiCad and create a
    printed circuit layout and get some Chinese firm to make and load the board.

    It would be an extravagance, but nothing dramatic.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Wed Nov 27 21:25:55 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vi7cks$26f3$1@dont-email.me...
    On 27/11/2024 7:48 pm, JM wrote:
    On Tue, 26 Nov 2024 15:32:38 +1100, Bill Sloman <bill.sloman@ieee.org>
    wrote:

    On 25/11/2024 1:02 pm, Bill Sloman wrote:
    On 24/11/2024 5:10 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhue9h$243sl$1@dont-email.me...
    On 24/11/2024 5:11 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhs1ea$1kbt4$1@dont-email.me...
    On 23/11/2024 4:12 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhrma8$1io30$2@dont-email.me...
    On 23/11/2024 3:32 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message
    news:vhp713$12bnt$2@dont-email.me...
    On 21/11/2024 1:00 am, Bill Sloman wrote:
    On 20/11/2024 2:03 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message >>>>>>>>>>>>>> news:vhjj2v$24eu4$3@dont-email.me...
    On 20/11/2024 1:29 pm, Bill Sloman wrote:
    On 20/11/2024 12:59 pm, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message >>>>>>>>>>>>>>>>> news:vhibce$1t7v2$1@dont-email.me...
    On 18/11/2024 2:58 pm, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>> "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message >>>>>>>>>>>>>>>>>>> news:n7iijjdeqecl0kmub0bq5in0dbm60m7qam@4ax.com... >>>>>>>>>>>>>>>>>>>> On Thu, 14 Nov 2024 11:14:28 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    "JM" <sunaecoNoChoppedPork@gmail.com> wrote in message >>>>>>>>>>>>>>>>>>>>> news:t5fajjdteskfftvkf84iqsp2vc4b9ta5kj@4ax.com... >>>>>>>>>>>>>>>>>>>>>> On Fri, 8 Nov 2024 15:43:41 -0500, "Edward Rawde" >>>>>>>>>>>>>>>>>>>>>> <invalid@invalid.invalid> wrote:

    ...

    When evaluating architecture there's little to be gained by using a
    complicated opamp model. Use a simple 1 or 2 pole model to begin
    with.

    Try the attached file, I've used a simple model to speed up the
    simulation, and made a slight circuit change. This shows the
    harmonics due to the control loop to be sub 130dBc. Of course the
    amplifier harmonic distortion is not simulated, but neither was it in
    the simulation by Mr Rawde.

    Thanks for that. I've got it into a form that my copy of LTSpice recognises as a .asc file, so I have looked at it.

    I get 140dB down at 2kHz, 130dB down at 3kHz


    I haven't run it yet because I'm running yet another variant of the circuit, which has got to 2.4 seconds, and I'll leave it
    running overnight.

    I'm currently curious about the effect of the phase of the 2kHz component in the control signal (coming from my full-wave
    rectifier), and a fast simulating version of the circuit is just what I need to get that sorted out. I had thought that that it
    would be trivial to get the phase right, but my first attempt didn't get close.

    I could go mad and put a version of the circuit into KiCad and create a printed circuit layout and get some Chinese firm to make
    and load the board.

    I could too but I already know what 1kHz sounds like and I doubt that my ears can tell the difference between harmonics 120 and
    130dB down.


    It would be an extravagance, but nothing dramatic.

    --
    Bill Sloman, Sydney


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)