• 38 Mb/mm^2 SRAM

    From Jan Panteltje@21:1/5 to All on Thu Oct 31 12:46:48 2024
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements
    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
    38 Mb/mm^2

    --- SoupGate-Win32 v1.05
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  • From john larkin@21:1/5 to All on Thu Oct 31 08:07:19 2024
    On Thu, 31 Oct 2024 23:01:30 +0800, Sylvia Else <sylvia@email.invalid>
    wrote:

    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements
    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
    38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic >nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The cell structure would be interesting. Six transistors?

    I'd love it if our uPs had a lot more SRAM.

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  • From Sylvia Else@21:1/5 to Jan Panteltje on Thu Oct 31 23:01:30 2024
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims major improvements
    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
    38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic nanometre. Surely we're approaching the limits of this.

    Sylvia.

    --- SoupGate-Win32 v1.05
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  • From Jeroen Belleman@21:1/5 to Sylvia Else on Thu Oct 31 17:36:23 2024
    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims
    major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    Jeroen Belleman

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to Jeroen Belleman on Thu Oct 31 16:37:18 2024
    Jeroen Belleman <jeroen@nospam.please> wrote:
    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims
    major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic
    nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    Jeroen Belleman


    It’s the 21st century, man. What matters is that the _names_ follow Moore’s Law. Excelsior!

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to jeroen@nospam.please on Thu Oct 31 09:55:13 2024
    On Thu, 31 Oct 2024 17:36:23 +0100, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims
    major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic
    nanometre. Surely we're approaching the limits of this.

    Sylvia.

    Some day we'll hit the limit. That won't be a disaster.


    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    Jeroen Belleman

    But two is still better than 50. Probably.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jeroen@nospam.please on Thu Oct 31 15:42:22 2024
    On Thu, 31 Oct 2024 17:36:23 +0100, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims
    major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic
    nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    If I recall, it actually has a fairly precise definition, that it's
    the smallest feature size that can be manufactured. So, it's roughly equivalent to a pixel, and it takes many pixels to make a legible
    letter or number.

    Joe Gwinn

    --- SoupGate-Win32 v1.05
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  • From Jeroen Belleman@21:1/5 to Joe Gwinn on Thu Oct 31 21:13:57 2024
    On 10/31/24 20:42, Joe Gwinn wrote:
    On Thu, 31 Oct 2024 17:36:23 +0100, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims
    major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic >>> nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    If I recall, it actually has a fairly precise definition, that it's
    the smallest feature size that can be manufactured. So, it's roughly equivalent to a pixel, and it takes many pixels to make a legible
    letter or number.

    Joe Gwinn

    It used to, to be sure, but no more. You can't image 2nm details
    with 13nm EUV.

    Jeroen Belleman

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to All on Thu Oct 31 13:52:21 2024
    On Thu, 31 Oct 2024 15:42:22 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Thu, 31 Oct 2024 17:36:23 +0100, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims
    major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic >>> nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    If I recall, it actually has a fairly precise definition, that it's
    the smallest feature size that can be manufactured. So, it's roughly >equivalent to a pixel, and it takes many pixels to make a legible
    letter or number.

    Joe Gwinn

    I've heard that the EUV mask sets can cost a billion dollars.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to Jeroen Belleman on Thu Oct 31 20:47:36 2024
    Jeroen Belleman <jeroen@nospam.please> wrote:
    On 10/31/24 20:42, Joe Gwinn wrote:
    On Thu, 31 Oct 2024 17:36:23 +0100, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims >>>>> major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic >>>> nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    If I recall, it actually has a fairly precise definition, that it's
    the smallest feature size that can be manufactured. So, it's roughly
    equivalent to a pixel, and it takes many pixels to make a legible
    letter or number.

    Joe Gwinn

    It used to, to be sure, but no more. You can't image 2nm details
    with 13nm EUV.

    Jeroen Belleman


    You can, actually, because of the high contrast of photoresist. You do have
    to use multiple patterning steps per level.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to All on Thu Oct 31 17:18:42 2024
    On Thu, 31 Oct 2024 13:52:21 -0700, john larkin <jl@glen--canyon.com>
    wrote:

    On Thu, 31 Oct 2024 15:42:22 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Thu, 31 Oct 2024 17:36:23 +0100, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims
    major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic >>>> nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    If I recall, it actually has a fairly precise definition, that it's
    the smallest feature size that can be manufactured. So, it's roughly >>equivalent to a pixel, and it takes many pixels to make a legible
    letter or number.


    I've heard that the EUV mask sets can cost a billion dollars.

    Don't know; wouldn't be surprised though.

    Joe

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jeroen Belleman@21:1/5 to Phil Hobbs on Fri Nov 1 10:21:30 2024
    On 10/31/24 21:47, Phil Hobbs wrote:
    Jeroen Belleman <jeroen@nospam.please> wrote:
    On 10/31/24 20:42, Joe Gwinn wrote:
    On Thu, 31 Oct 2024 17:36:23 +0100, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/31/24 16:01, Sylvia Else wrote:
    On 31-Oct-24 8:46 pm, Jan Panteltje wrote:
    SRAM scaling isn't dead after all — TSMC's 2nm process tech claims >>>>>> major improvements

    https://www.tomshardware.com/tech-industry/sram-scaling-isnt-dead-after-all-tsmcs-2nm-process-tech-claims-major-improvements#main

    gate all around tech...
      38 Mb/mm^2

    If my arithmetic is right, there are about 50 atoms of silicon per cubic >>>>> nanometre. Surely we're approaching the limits of this.

    Sylvia.

    The stated '2nm process' has little to do with the actual size
    of features on the chip. It has become a sales argument rather
    than the true size of something.

    If I recall, it actually has a fairly precise definition, that it's
    the smallest feature size that can be manufactured. So, it's roughly
    equivalent to a pixel, and it takes many pixels to make a legible
    letter or number.

    Joe Gwinn

    It used to, to be sure, but no more. You can't image 2nm details
    with 13nm EUV.

    Jeroen Belleman


    You can, actually, because of the high contrast of photoresist. You do have to use multiple patterning steps per level.

    Cheers

    Phil Hobbs


    To some extent, yes, OK.

    Talking of photoresists, these are usually polymers, that is, large
    molecules. At some point, that will also set a limit on the minimum
    size of features.

    Jeroen Belleman

    --- SoupGate-Win32 v1.05
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