• Random thoughts on sinewave oscillators

    From Edward Rawde@21:1/5 to All on Wed Oct 16 16:55:24 2024
    Is the reason why this doesn't produce a better looking sinewave because the amplifier slew rate is faster going down than it is
    going up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept to work at all.

    I'm aware that a single package containing two op amps could probably do a much better job.

    Open the file in notepad++ (which you do use don't you?) and under encoding select Convert to ANSI. Save the file.
    That will fix issues with u symbols.

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    TEXT -424 800 Left 2 !.tran 100
    TEXT 632 -200 Left 3 ;Edward Rawde's weird sinewave oscillator. October 2024

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From piglet@21:1/5 to Edward Rawde on Thu Oct 17 12:32:03 2024
    On 16/10/2024 9:55 pm, Edward Rawde wrote:
    Is the reason why this doesn't produce a better looking sinewave because the amplifier slew rate is faster going down than it is
    going up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept to work at all.

    I'm aware that a single package containing two op amps could probably do a much better job.

    Open the file in notepad++ (which you do use don't you?) and under encoding select Convert to ANSI. Save the file.
    That will fix issues with u symbols.

    Version 4
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    SYMATTR InstName R22
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    WINDOW 0 0 32 VBottom 2
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    SYMATTR InstName C16
    SYMATTR Value 0.1ľ
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    SYMATTR InstName D1
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    SYMBOL diode 1120 304 R90
    WINDOW 0 0 32 VBottom 2
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    SYMBOL res 1616 576 R0
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    SYMBOL res 1872 576 R0
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    SYMBOL cap 2176 544 R0
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    SYMBOL cap 1376 240 R180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C21
    SYMATTR Value 10ľ
    TEXT -424 800 Left 2 !.tran 100
    TEXT 632 -200 Left 3 ;Edward Rawde's weird sinewave oscillator. October 2024



    I assume this is an intellectual challenge and not a real project? I
    suspect the jfet gate-channel is forward biased so the amplitude control section is my first place to look?

    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From piglet@21:1/5 to piglet on Thu Oct 17 15:01:04 2024
    On 17/10/2024 12:32 pm, piglet wrote:
    On 16/10/2024 9:55 pm, Edward Rawde wrote:
    Is the reason why this doesn't produce a better looking sinewave
    because the amplifier slew rate is faster going down than it is
    going up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept
    to work at all.

    I'm aware that a single package containing two op amps could probably
    do a much better job.

    Open the file in notepad++ (which you do use don't you?) and under
    encoding select Convert to ANSI. Save the file.
    That will fix issues with u symbols.

    Version 4
    SHEET 1 2772 1280
    WIRE 112 -144 -304 -144
    WIRE 352 -144 112 -144
    WIRE 640 -144 352 -144
    WIRE 1456 -144 640 -144
    WIRE 1728 -144 1456 -144
    WIRE 2064 -144 1728 -144
    WIRE 352 -128 352 -144
    WIRE 112 -112 112 -144
    WIRE 640 -112 640 -144
    WIRE 2064 -96 2064 -144
    WIRE 1728 -80 1728 -144
    WIRE 1456 -64 1456 -144
    WIRE 352 -16 352 -48
    WIRE 352 -16 256 -16
    WIRE 112 0 112 -32
    WIRE 112 0 0 0
    WIRE 352 0 352 -16
    WIRE 640 16 640 -32
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    WIRE 2176 16 2064 16
    WIRE 112 32 112 0
    WIRE 256 32 256 -16
    WIRE 1728 32 1728 0
    WIRE 1728 32 1632 32
    WIRE 1888 32 1728 32
    WIRE 0 48 0 0
    WIRE 768 64 768 16
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    WIRE 640 80 640 16
    WIRE 1632 80 1632 32
    WIRE 1888 80 1888 32
    WIRE 352 128 352 80
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    WIRE 1456 128 1456 64
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    WIRE 640 208 640 176
    WIRE 640 208 464 208
    WIRE -304 256 -304 -144
    WIRE 352 256 352 128
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    WIRE 1888 352 1888 176
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    WIRE -32 832 -32 784
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    FLAG 768 176 0
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    FLAG 0 160 0
    FLAG 256 144 0
    FLAG 32 400 In+
    FLAG 144 496 In-
    FLAG 2176 176 0
    FLAG 1408 896 amplitude-control
    FLAG 1296 320 vdet
    DATAFLAG 592 208 "round(($)*100)/100"
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    DATAFLAG 256 384 "round(($)*100)/100"
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    DATAFLAG 1520 128 "round(($)*100)/100"
    DATAFLAG 2128 432 "round(($)*100)/100"
    DATAFLAG 1824 352 "round(($)*100)/100"
    DATAFLAG 1584 544 "round(($)*100)/100"
    DATAFLAG 1408 320 "round(($)*100)/100"
    DATAFLAG 1824 32 "round(($)*100)/100"
    SYMBOL res 96 -128 R0
    WINDOW 3 36 73 Left 2
    SYMATTR Value 15k
    SYMATTR InstName R1
    SYMBOL voltage -304 240 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 -151 71 Left 2
    WINDOW 3 -79 36 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR Value 12
    SYMATTR InstName V1
    SYMBOL npn 48 352 R0
    SYMATTR InstName Q1
    SYMATTR Value BC847C
    SYMBOL res 96 176 R0
    WINDOW 0 -46 26 Left 2
    WINDOW 3 -68 68 Left 2
    SYMATTR InstName R2
    SYMATTR Value 150k
    SYMBOL npn 576 80 R0
    SYMATTR InstName Q3
    SYMATTR Value BC847C
    SYMBOL res 336 -144 R0
    WINDOW 3 35 73 Left 2
    SYMATTR Value 1k
    SYMATTR InstName R3
    SYMBOL npn 288 256 R0
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    SYMATTR Value BC847C
    SYMBOL res 96 528 R0
    WINDOW 3 -47 71 Left 2
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    SYMATTR Value 470
    SYMATTR InstName R4
    SYMBOL res 96 704 R0
    WINDOW 3 37 67 Left 2
    SYMATTR Value 39k
    SYMATTR InstName R5
    SYMBOL res -48 512 R0
    WINDOW 0 -41 40 Left 2
    WINDOW 3 -66 68 Left 2
    SYMATTR InstName R6
    SYMATTR Value 270k
    SYMBOL cap 80 496 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 470p
    SYMBOL polcap -48 720 R0
    SYMATTR InstName C3
    SYMATTR Value 220ľ
    SYMBOL cap 464 192 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C5
    SYMATTR Value 10p
    SYMBOL res 336 528 R0
    WINDOW 0 35 32 Left 2
    WINDOW 3 37 62 Left 2
    SYMATTR InstName R10
    SYMATTR Value 5.6k
    SYMBOL res 336 704 R0
    WINDOW 0 -53 28 Left 2
    WINDOW 3 -50 58 Left 2
    SYMATTR InstName R11
    SYMATTR Value 10k
    SYMBOL res 336 384 R0
    WINDOW 0 -59 43 Left 2
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    SYMATTR InstName R12
    SYMATTR Value 2.2k
    SYMBOL res -32 864 R0
    SYMATTR InstName R15
    SYMATTR Value 470k
    SYMBOL cap 80 896 R0
    SYMATTR InstName C6
    SYMATTR Value 270pf
    SYMBOL cap 208 1024 R270
    WINDOW 0 32 32 VTop 2
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    SYMATTR Value 1ľ
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    SYMATTR Value 100ľ
    SYMBOL polcap 752 64 R0
    SYMATTR InstName C10
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    SYMBOL polcap 656 496 R270
    WINDOW 0 32 32 VTop 2
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    SYMATTR InstName C11
    SYMATTR Value 1ľ
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    WINDOW 0 0 56 VBottom 2
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    SYMATTR InstName R16
    SYMATTR Value 100
    SYMBOL res 832 592 R0
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    WINDOW 3 36 73 Left 2
    SYMATTR Value 33k
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    WINDOW 0 -40 9 Left 2
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    WINDOW 3 35 73 Left 2
    SYMATTR Value 22k
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    SYMATTR Value 22ľ
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    WINDOW 0 32 56 VTop 2
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    WINDOW 0 0 32 VBottom 2
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    WINDOW 0 0 56 VBottom 2
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    SYMATTR Value 1.5k
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    SYMATTR Value J175
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    SYMATTR Value 470
    SYMBOL res 800 304 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
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    SYMATTR Value 100
    SYMBOL cap 944 304 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C16
    SYMATTR Value 0.1ľ
    SYMBOL diode 1008 560 R0
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL diode 1120 304 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D2
    SYMATTR Value 1N4148
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    SYMATTR Value 10ľ
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    SYMATTR Value 220k
    SYMBOL res 1264 304 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R24
    SYMATTR Value 22k
    SYMBOL pnp 1568 176 M180
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    SYMATTR Value BC857C
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    SYMATTR Value 10k
    SYMBOL pnp 1952 176 R180
    SYMATTR InstName Q5
    SYMATTR Value BC857C
    SYMBOL res 2048 112 R0
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    SYMATTR Value 22k
    SYMBOL res 2048 512 R0
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    SYMATTR Value 22k
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    SYMATTR Value 22k
    SYMBOL polcap 2160 64 R0
    SYMATTR InstName C18
    SYMATTR Value 220ľ
    SYMBOL res 1616 576 R0
    SYMATTR InstName R29
    SYMATTR Value 22k
    SYMBOL res 1872 576 R0
    SYMATTR InstName R30
    SYMATTR Value 22k
    SYMBOL cap 2176 544 R0
    SYMATTR InstName C19
    SYMATTR Value 1ľ
    SYMBOL res 1440 -80 R0
    SYMATTR InstName R31
    SYMATTR Value 220k
    SYMBOL cap 1376 240 R180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C21
    SYMATTR Value 10ľ
    TEXT -424 800 Left 2 !.tran 100
    TEXT 632 -200 Left 3 ;Edward Rawde's weird sinewave oscillator.
    October 2024



    I assume this is an intellectual challenge and not a real project? I
    suspect the jfet gate-channel is forward biased so the amplitude control section is my first place to look?

    piglet


    Hmm, that forward biased gate only happens during startup. Some other ideas:

    The amp input bias R6 loads the Wien network too much - try lowering the
    Wien network impedance?

    Replace R7 with constant current sink if you think slew rate is the issue?

    Rectifier load is too heavy on the follower - increase R22?

    Q5 base reference is not stiff enough - lower R26-27-28?

    Q4 base current flows through rectifier - reference D1 instead to +12 rail?

    Maybe later I will find time to explore...

    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to piglet on Thu Oct 17 21:29:51 2024
    "piglet" <erichpwagner@hotmail.com> wrote in message news:ver5b2$2p6tm$1@dont-email.me...
    On 17/10/2024 12:32 pm, piglet wrote:
    On 16/10/2024 9:55 pm, Edward Rawde wrote:
    Is the reason why this doesn't produce a better looking sinewave because the amplifier slew rate is faster going down than it is
    going up or some other reason?

    ...




    Thank you for taking the time to look at this piglet.

    I assume this is an intellectual challenge and not a real project?

    Yes I'm not likely to be building it any time soon.
    There was talk of sinewave oscillators here recently so I decided to see how easy or difficult it would be to make a sinewave
    oscillator without using lamps or thermistors.
    I think it might be easier if I used standard op amps.

    I suspect the jfet gate-channel is forward biased so the amplitude control section is my first place to look?

    piglet


    Hmm, that forward biased gate only happens during startup. Some other ideas:

    The amp input bias R6 loads the Wien network too much - try lowering the Wien network impedance?

    It has been lowered in the circuit below.


    Replace R7 with constant current sink if you think slew rate is the issue?

    Done


    Rectifier load is too heavy on the follower - increase R22?

    Added separate follower.

    When trying other suggestions, it's hard to get a stable amplitude control loop.

    The circuit below produces a reasonable looking sinewave but the rise time still seems to be slower than the fall time.
    It may be that the amplifier in use is not ideal for this.


    Q5 base reference is not stiff enough - lower R26-27-28?

    Q4 base current flows through rectifier - reference D1 instead to +12 rail?

    Maybe later I will find time to explore...

    piglet


    Circuit version 2 follows.

    Version 4
    SHEET 1 2888 1280
    WIRE 112 -144 -304 -144
    WIRE 352 -144 112 -144
    WIRE 640 -144 352 -144
    WIRE 880 -144 640 -144
    WIRE 1008 -144 880 -144
    WIRE 1808 -144 1008 -144
    WIRE 2080 -144 1808 -144
    WIRE 2416 -144 2080 -144
    WIRE 352 -128 352 -144
    WIRE 112 -112 112 -144
    WIRE 640 -112 640 -144
    WIRE 2416 -96 2416 -144
    WIRE 1008 -80 1008 -144
    WIRE 2080 -80 2080 -144
    WIRE 1808 -64 1808 -144
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    WIRE 352 -16 256 -16
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    WIRE 208 640 208 624
    WIRE 208 640 112 640
    WIRE 880 640 880 624
    WIRE -32 656 -32 608
    WIRE 352 656 352 624
    WIRE 352 656 -32 656
    WIRE 1008 656 1008 320
    WIRE 112 688 112 640
    WIRE 112 688 -32 688
    WIRE 640 704 640 672
    WIRE -32 720 -32 688
    WIRE 112 720 112 688
    WIRE 352 720 352 656
    WIRE 432 720 432 528
    WIRE 880 736 880 704
    WIRE -304 832 -304 336
    WIRE -32 832 -32 784
    WIRE -32 832 -304 832
    WIRE -16 832 -32 832
    WIRE 96 832 -16 832
    WIRE 112 832 112 800
    WIRE 112 832 96 832
    WIRE 352 832 352 800
    WIRE 352 832 112 832
    WIRE 432 832 432 784
    WIRE 432 832 352 832
    WIRE 640 832 640 784
    WIRE 640 832 432 832
    WIRE 880 832 880 800
    WIRE 880 832 640 832
    WIRE 1008 832 1008 736
    WIRE 1008 832 880 832
    WIRE 1200 832 1200 688
    WIRE 1200 832 1008 832
    WIRE 1376 832 1376 624
    WIRE 1376 832 1200 832
    WIRE 1504 832 1504 544
    WIRE 1504 832 1376 832
    WIRE 1808 832 1808 624
    WIRE 1808 832 1504 832
    WIRE 1984 832 1984 672
    WIRE 1984 832 1808 832
    WIRE 2240 832 2240 672
    WIRE 2240 832 1984 832
    WIRE 2416 832 2416 608
    WIRE 2416 832 2240 832
    WIRE 2544 832 2544 608
    WIRE 2544 832 2416 832
    WIRE -304 864 -304 832
    WIRE -16 880 -16 832
    WIRE 96 896 96 832
    WIRE 272 896 272 592
    WIRE 1760 896 272 896
    WIRE 1888 896 1888 544
    WIRE 1888 896 1760 896
    WIRE -144 1008 -144 512
    WIRE -16 1008 -16 960
    WIRE -16 1008 -144 1008
    WIRE 96 1008 96 960
    WIRE 96 1008 -16 1008
    WIRE 208 1008 96 1008
    WIRE 320 1008 272 1008
    WIRE 544 1008 544 544
    WIRE 544 1008 400 1008
    WIRE 1312 1008 1312 480
    WIRE 1520 1008 1312 1008
    WIRE 1584 1008 1520 1008
    FLAG 768 176 0
    FLAG 1520 1008 sine-out
    FLAG -304 864 0
    FLAG 0 160 0
    FLAG 256 144 0
    FLAG 32 400 In+
    FLAG 144 496 In-
    FLAG 2528 176 0
    FLAG 1760 896 amplitude-control
    FLAG 1664 320 vdet
    FLAG 1136 176 0
    DATAFLAG 592 208 "round(($)*100)/100"
    DATAFLAG 400 528 "round(($)*100)/100"
    DATAFLAG 160 640 "round(($)*100)/100"
    DATAFLAG -80 400 "round(($)*100)/100"
    DATAFLAG 224 496 "round(($)*100)/100"
    DATAFLAG 64 688 "round(($)*100)/100"
    DATAFLAG 160 160 "round(($)*100)/100"
    DATAFLAG 160 304 "round(($)*100)/100"
    DATAFLAG 256 384 "round(($)*100)/100"
    DATAFLAG 400 128 "round(($)*100)/100"
    DATAFLAG -192 -144 "round(($)*100)/100"
    DATAFLAG 688 16 "round(($)*100)/100"
    DATAFLAG 1856 128 "round(($)*100)/100"
    DATAFLAG 2480 432 "round(($)*100)/100"
    DATAFLAG 2176 352 "round(($)*100)/100"
    DATAFLAG 1936 544 "round(($)*100)/100"
    DATAFLAG 1760 320 "round(($)*100)/100"
    DATAFLAG 2176 32 "round(($)*100)/100"
    DATAFLAG 1056 320 "round(($)*100)/100"
    DATAFLAG 1056 64 "round(($)*100)/100"
    SYMBOL res 96 -128 R0
    WINDOW 3 36 73 Left 2
    SYMATTR Value 15k
    SYMATTR InstName R1
    SYMBOL voltage -304 240 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 -151 71 Left 2
    WINDOW 3 -79 36 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR Value 12
    SYMATTR InstName V1
    SYMBOL npn 48 352 R0
    SYMATTR InstName Q1
    SYMATTR Value BC847C
    SYMBOL res 96 176 R0
    WINDOW 0 -46 26 Left 2
    WINDOW 3 -68 68 Left 2
    SYMATTR InstName R2
    SYMATTR Value 150k
    SYMBOL npn 576 80 R0
    SYMATTR InstName Q3
    SYMATTR Value BC847C
    SYMBOL npn 288 256 R0
    SYMATTR InstName Q2
    SYMATTR Value BC847C
    SYMBOL res 96 528 R0
    WINDOW 3 -47 71 Left 2
    WINDOW 0 -37 45 Left 2
    SYMATTR Value 470
    SYMATTR InstName R4
    SYMBOL res 96 704 R0
    WINDOW 3 37 67 Left 2
    SYMATTR Value 39k
    SYMATTR InstName R5
    SYMBOL res -48 512 R0
    WINDOW 0 -41 40 Left 2
    WINDOW 3 -66 68 Left 2
    SYMATTR InstName R6
    SYMATTR Value 270k
    SYMBOL cap 80 496 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 470p
    SYMBOL polcap -48 720 R0
    SYMATTR InstName C3
    SYMATTR Value 220µ
    SYMBOL cap 464 192 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C5
    SYMATTR Value 10p
    SYMBOL res 336 528 R0
    WINDOW 0 35 32 Left 2
    WINDOW 3 37 62 Left 2
    SYMATTR InstName R10
    SYMATTR Value 5.6k
    SYMBOL res 336 704 R0
    WINDOW 0 -53 28 Left 2
    WINDOW 3 -50 58 Left 2
    SYMATTR InstName R11
    SYMATTR Value 10k
    SYMBOL res 336 384 R0
    WINDOW 0 -59 43 Left 2
    WINDOW 3 -59 70 Left 2
    SYMATTR InstName R12
    SYMATTR Value 2.2k
    SYMBOL res -32 864 R0
    SYMATTR InstName R15
    SYMATTR Value 47k
    SYMBOL cap 80 896 R0
    SYMATTR InstName C6
    SYMATTR Value 2.7n
    SYMBOL cap 208 1024 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C7
    SYMATTR Value 2.7n
    SYMBOL polcap -160 448 R0
    SYMATTR InstName C8
    SYMATTR Value 1µ
    SYMBOL polcap 416 720 R0
    SYMATTR InstName C9
    SYMATTR Value 100µ
    SYMBOL polcap 752 64 R0
    SYMATTR InstName C10
    SYMATTR Value 220µ
    SYMBOL polcap 656 496 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C11
    SYMATTR Value 1µ
    SYMBOL res 832 464 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R16
    SYMATTR Value 100
    SYMBOL res 1184 592 R0
    SYMATTR InstName R17
    SYMATTR Value 1Meg
    SYMBOL res 96 16 R0
    WINDOW 3 36 73 Left 2
    SYMATTR Value 33k
    SYMATTR InstName R18
    SYMBOL polcap -16 48 R0
    SYMATTR InstName C12
    SYMATTR Value 22µ
    SYMBOL polcap 192 192 R0
    WINDOW 0 -40 9 Left 2
    WINDOW 3 -47 54 Left 2
    SYMATTR InstName C2
    SYMATTR Value 22µ
    SYMBOL res 336 -16 R0
    WINDOW 3 35 73 Left 2
    SYMATTR Value 22k
    SYMATTR InstName R19
    SYMBOL polcap 240 32 R0
    SYMATTR InstName C13
    SYMATTR Value 22µ
    SYMBOL res 304 1024 R270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R8
    SYMATTR Value 47k
    SYMBOL polcap 512 480 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C4
    SYMATTR Value 10µ
    SYMBOL res 624 688 R0
    SYMATTR InstName R7
    SYMATTR Value 270
    SYMBOL res 640 480 R90
    WINDOW 0 -37 54 VBottom 2
    WINDOW 3 -34 54 VTop 2
    SYMATTR InstName R13
    SYMATTR Value 470
    SYMBOL pjf 256 528 M0
    WINDOW 0 -24 6 Left 2
    WINDOW 3 -49 37 Left 2
    SYMATTR InstName J1
    SYMATTR Value J175
    SYMBOL res 624 -128 R0
    SYMATTR InstName R20
    SYMATTR Value 470
    SYMBOL res 800 224 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R22
    SYMATTR Value 10k
    SYMBOL cap 1312 304 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C16
    SYMATTR Value 0.1µ
    SYMBOL diode 1360 560 R0
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL diode 1472 304 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D2
    SYMATTR Value 1N4148
    SYMBOL cap 1792 560 R0
    SYMATTR InstName C17
    SYMATTR Value 10µ
    SYMBOL res 1792 160 R0
    SYMATTR InstName R23
    SYMATTR Value 220k
    SYMBOL res 1632 304 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R24
    SYMATTR Value 22k
    SYMBOL pnp 1920 176 M180
    SYMATTR InstName Q4
    SYMATTR Value BC857C
    SYMBOL res 2064 -96 R0
    SYMATTR InstName R25
    SYMATTR Value 10k
    SYMBOL pnp 2304 176 R180
    SYMATTR InstName Q5
    SYMATTR Value BC857C
    SYMBOL res 2400 112 R0
    SYMATTR InstName R26
    SYMATTR Value 22k
    SYMBOL res 2400 512 R0
    SYMATTR InstName R27
    SYMATTR Value 22k
    SYMBOL res 2400 -112 R0
    SYMATTR InstName R28
    SYMATTR Value 22k
    SYMBOL polcap 2512 64 R0
    SYMATTR InstName C18
    SYMATTR Value 220µ
    SYMBOL res 1968 576 R0
    SYMATTR InstName R29
    SYMATTR Value 22k
    SYMBOL res 2224 576 R0
    SYMATTR InstName R30
    SYMATTR Value 22k
    SYMBOL cap 2528 544 R0
    SYMATTR InstName C19
    SYMATTR Value 1µ
    SYMBOL res 1792 -80 R0
    SYMATTR InstName R31
    SYMATTR Value 220k
    SYMBOL cap 1728 240 R180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C21
    SYMATTR Value 10µ
    SYMBOL npn 704 576 M0
    SYMATTR InstName Q6
    SYMATTR Value BC847C
    SYMBOL diode 896 736 M0
    WINDOW 0 46 -1 Left 2
    WINDOW 3 44 30 Left 2
    SYMATTR InstName D3
    SYMATTR Value 1N4148
    SYMBOL diode 896 640 M0
    WINDOW 0 44 2 Left 2
    WINDOW 3 42 32 Left 2
    SYMATTR InstName D4
    SYMATTR Value 1N4148
    SYMBOL res 336 -144 R0
    WINDOW 3 35 73 Left 2
    SYMATTR Value 1k
    SYMATTR InstName R3
    SYMBOL res 864 0 R0
    SYMATTR InstName R9
    SYMATTR Value 10k
    SYMBOL npn 944 192 R0
    SYMATTR InstName Q7
    SYMATTR Value BC847C
    SYMBOL polcap 1120 80 R0
    SYMATTR InstName C14
    SYMATTR Value 220µ
    SYMBOL res 992 -96 R0
    SYMATTR InstName R14
    SYMATTR Value 100
    SYMBOL res 992 640 R0
    SYMATTR InstName R21
    SYMATTR Value 3.3k
    SYMBOL res 1200 304 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R32
    SYMATTR Value 100
    SYMBOL cap 1488 544 M180
    WINDOW 0 24 56 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C20
    SYMATTR Value 0.1µ
    TEXT -424 800 Left 2 !.tran 0 100 0 0.0001
    TEXT 632 -200 Left 3 ;Edward Rawde's weird sinewave oscillator. V2. October 2024

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Fri Oct 18 16:29:14 2024
    On 17/10/2024 7:55 am, Edward Rawde wrote:
    Is the reason why this doesn't produce a better looking sinewave because the amplifier slew rate is faster going down than it is
    going up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept to work at all.

    I'm aware that a single package containing two op amps could probably do a much better job.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    has a pretty good example of a sine wave oscillator. I've speculated
    that a four quadrant analogue multiplier could offer a better gain
    control mechanism.

    https://www.analog.com/media/en/technical-documentation/data-sheets/AD734.pdf

    though it is hideously expensive. The simulation I worked up used two
    with the second one controlling a quadrature input to give you smooth
    control of the frequency of oscillation in addition to its amplitude.

    I thought about building one, but there's no obvious application.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Fri Oct 18 02:23:38 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vesrnm$35jgr$1@dont-email.me...
    On 17/10/2024 7:55 am, Edward Rawde wrote:
    Is the reason why this doesn't produce a better looking sinewave because the amplifier slew rate is faster going down than it is
    going up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept to work at all.

    I'm aware that a single package containing two op amps could probably do a much better job.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    has a pretty good example of a sine wave oscillator. I've speculated that a four quadrant analogue multiplier could offer a better
    gain control mechanism.

    https://www.analog.com/media/en/technical-documentation/data-sheets/AD734.pdf

    though it is hideously expensive. The simulation I worked up used two with the second one controlling a quadrature input to give
    you smooth control of the frequency of oscillation in addition to its amplitude.

    I thought about building one, but there's no obvious application.

    --
    Bill Sloman, Sydney


    Thanks Bill.

    It may be that there's something wrong with the concept I'm trying to use because the circuit below can't find a control point which
    produces sine waves.
    It just produces all or nothing at a repetition rate of about 80 Hz.
    I saw similar issues while simulating the discrete circuit.

    Version 4
    SHEET 1 2164 680
    WIRE -384 -48 -560 -48
    WIRE -240 -48 -384 -48
    WIRE -80 -48 -240 -48
    WIRE 144 -48 -80 -48
    WIRE 864 -48 144 -48
    WIRE 992 -48 864 -48
    WIRE 1104 -48 992 -48
    WIRE 864 -16 864 -48
    WIRE 992 -16 992 -48
    WIRE -240 32 -240 -48
    WIRE -80 32 -80 -48
    WIRE 64 64 -16 64
    WIRE 192 64 64 64
    WIRE 304 64 272 64
    WIRE -560 80 -560 -48
    WIRE -16 80 -16 64
    WIRE 304 96 304 64
    WIRE 336 96 304 96
    WIRE 448 96 416 96
    WIRE 544 96 512 96
    WIRE 592 96 544 96
    WIRE 688 96 656 96
    WIRE 736 96 688 96
    WIRE 864 96 864 64
    WIRE 864 96 816 96
    WIRE -384 112 -384 -48
    WIRE 144 112 144 -48
    WIRE 1104 112 1104 -48
    WIRE 64 128 64 64
    WIRE 112 128 64 128
    WIRE 864 128 864 96
    WIRE 1072 128 864 128
    WIRE 304 144 304 96
    WIRE 304 144 176 144
    WIRE 1216 144 1136 144
    WIRE -240 160 -240 112
    WIRE -176 160 -240 160
    WIRE 112 160 -176 160
    WIRE 544 160 544 96
    WIRE 688 160 688 96
    WIRE 992 160 992 64
    WIRE 1072 160 992 160
    WIRE 864 176 864 128
    WIRE -240 192 -240 160
    WIRE -80 208 -80 112
    WIRE -16 208 -16 144
    WIRE -16 208 -80 208
    WIRE -80 224 -80 208
    WIRE -16 224 -16 208
    WIRE 992 224 992 160
    WIRE 96 288 32 288
    WIRE -560 336 -560 160
    WIRE -384 336 -384 176
    WIRE -384 336 -560 336
    WIRE -240 336 -240 272
    WIRE -240 336 -384 336
    WIRE -80 336 -80 304
    WIRE -80 336 -240 336
    WIRE -48 336 -80 336
    WIRE -16 336 -16 320
    WIRE -16 336 -48 336
    WIRE 144 336 144 176
    WIRE 144 336 -16 336
    WIRE 544 336 544 224
    WIRE 544 336 144 336
    WIRE 688 336 688 224
    WIRE 688 336 544 336
    WIRE 864 336 864 240
    WIRE 864 336 688 336
    WIRE 992 336 992 304
    WIRE 992 336 864 336
    WIRE 1104 336 1104 176
    WIRE 1104 336 992 336
    WIRE -48 352 -48 336
    WIRE -560 384 -560 336
    WIRE 96 384 96 288
    WIRE 1216 384 1216 144
    WIRE 1216 384 96 384
    WIRE -176 448 -176 160
    WIRE -48 448 -48 416
    WIRE -48 448 -176 448
    WIRE 16 448 -48 448
    WIRE 96 448 80 448
    WIRE 304 448 304 144
    WIRE 304 448 176 448
    WIRE 432 448 304 448
    WIRE 480 448 432 448
    FLAG -560 384 0
    FLAG 432 448 output
    SYMBOL OpAmps\\OP07 144 80 R0
    SYMATTR InstName U1
    SYMBOL voltage -560 64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 24 124 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 192 432 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 12k
    SYMBOL cap 80 432 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 15n
    SYMBOL cap -32 416 R180
    WINDOW 0 -33 54 Left 2
    WINDOW 3 -49 18 Left 2
    SYMATTR InstName C2
    SYMATTR Value 15n
    SYMBOL res 288 48 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 1700
    SYMBOL res -224 128 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R4
    SYMATTR Value 24k
    SYMBOL polcap -32 80 R0
    SYMATTR InstName C3
    SYMATTR Value 10µ
    SYMBOL res -224 288 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R5
    SYMATTR Value 24k
    SYMBOL polcap -400 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100µ
    SYMBOL pjf 32 224 M0
    WINDOW 0 -28 43 Left 2
    WINDOW 3 -53 90 Left 2
    SYMATTR InstName J1
    SYMATTR Value J175
    SYMBOL res -96 208 R0
    WINDOW 0 -39 37 Left 2
    WINDOW 3 -48 70 Left 2
    SYMATTR InstName R6
    SYMATTR Value 1k
    SYMBOL res -96 16 R0
    WINDOW 0 -48 37 Left 2
    WINDOW 3 -69 66 Left 2
    SYMATTR InstName R8
    SYMATTR Value 220k
    SYMBOL res 432 80 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R9
    SYMATTR Value 1k
    SYMBOL cap 512 80 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C5
    SYMATTR Value 0.1µ
    SYMBOL diode 528 160 R0
    WINDOW 0 39 34 Left 2
    WINDOW 3 31 68 Left 2
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL diode 656 80 R90
    WINDOW 0 64 31 VBottom 2
    WINDOW 3 -30 29 VTop 2
    SYMATTR InstName D2
    SYMATTR Value 1N4148
    SYMBOL cap 672 160 R0
    SYMATTR InstName C6
    SYMATTR Value 0.1µ
    SYMBOL res 832 80 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R11
    SYMATTR Value 22k
    SYMBOL cap 848 176 R0
    SYMATTR InstName C7
    SYMATTR Value 1µ
    SYMBOL res 848 -32 R0
    WINDOW 0 41 43 Left 2
    WINDOW 3 37 73 Left 2
    SYMATTR InstName R12
    SYMATTR Value 100k
    SYMBOL OpAmps\\OP07 1104 80 R0
    SYMATTR InstName U2
    SYMBOL res 1008 80 R180
    WINDOW 0 -53 70 Left 2
    WINDOW 3 -49 43 Left 2
    SYMATTR InstName R10
    SYMATTR Value 10k
    SYMBOL res 1008 320 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R13
    SYMATTR Value 2k
    TEXT -544 360 Left 2 !.tran 10

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Liz Tuddenham@21:1/5 to Edward Rawde on Fri Oct 18 09:48:17 2024
    Edward Rawde <invalid@invalid.invalid> wrote:

    Is the reason why this doesn't produce a better looking sinewave because
    the amplifier slew rate is faster going down than it is going up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept to
    work at all.

    I'm aware that a single package containing two op amps could probably do a much better job.

    if noise is more important than waveform, I found amplitude control by
    clipping gave the lowest noise. The oscillators in this...

    <http://www.poppyrecords.co.uk/other/DistortionMeter/intermodmeter.htm>

    ...are amplitude stabilised by clipping.

    --
    ~ Liz Tuddenham ~
    (Remove the ".invalid"s and add ".co.uk" to reply)
    www.poppyrecords.co.uk

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jan Panteltje@21:1/5 to invalid@invalid.invalid on Fri Oct 18 09:42:17 2024
    On a sunny day (Wed, 16 Oct 2024 16:55:24 -0400) it happened "Edward Rawde" <invalid@invalid.invalid> wrote in <vep97r$2cpo$1@nnrp.usenet.blueworldhosting.com>:

    Is the reason why this doesn't produce a better looking sinewave because the amplifier slew rate is faster going down than it is

    going up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept to work at all.

    I'm aware that a single package containing two op amps could probably do a much better job.

    Open the file in notepad++ (which you do use don't you?) and under encoding select Convert to ANSI. Save the file.
    That will fix issues with u symbols.

    Cannot use your funny numbers
    but as you ask for oscillators and thoughts about those, here some of mine
    Long ago in the early IBM PC days, (19 eighties?) I needed some audio sweep sine generator
    programmed a sine wave table in an EPROM, 8 bits, added a DAC chip
    used a 4046 as variable oscillator, added a 4040 binary counter, used that to drive the EPROM. resulted in a nice audio range sweep.
    Of course with a decent sound card and Linux these days use 'sox' for the audio range to generate tones and sweeps etc:
    https://www.audiosciencereview.com/forum/index.php?threads/howto-sox-audio-tool-as-a-signal-generator.4242/
    I use sox in Linux on a Raspberry Pi... to make nice test tones.
    Good sound card helps.
    Sine tables you can of course use in a micro, using that in a Microchip PIC micro here for Fourier transform
    https://panteltje.nl/panteltje/pic/scope_pic/
    or is a FPGA, ever higher frequencies, video DAC on FPGA I have here,
    https://panteltje.nl/pub/FPGA_board_with_25MHz_VCXO_locked_to_rubidium_10MHz_reference_IMG_3724.GIF
    But for RF the good old LC Jfet makes a nice sinewave too, up to hundreds of MHz
    There are many more oscillator types, crystal, ceramic to several GHz, that come close to a sinewave
    for example as local oscillator in satellite LNBs, 2 ceramic resonator oscillators here:
    https://panteltje.nl/pub/5_dollar_LNB_PCB_IMG_3582.GIF
    Some chips even output a sine wave, old modem chips

    Not to mention my Fazley keyboard... press a key for a note,
    you can select 'distortion' by selecting an instrument.

    more:
    https://panteltje.nl/pub/44kHz_xmtr_circuit_diagram_IMG_4079.JPG

    more:
    https://panteltje.nl/pub/44kHz_xmtr_circuit_diagram_IMG_4079.JPG
    https://panteltje.nl/pub/musical_gui.gif
    https://panteltje.online/pub/6MHz_xtal_oscillator.gif
    https://panteltje.online/pub/2.4GHz_twisted_oscillator_IMG_3629.GIF
    40_mV_oscillator_IMG_3597.GIF
    that is a JFET

    There are many more....

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From piglet@21:1/5 to Edward Rawde on Fri Oct 18 10:31:33 2024
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise
    time still seems to be slower than the fall time. It may be that the amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due to
    too much gain.


    --
    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to piglet on Fri Oct 18 11:25:19 2024
    "piglet" <erichpwagner@hotmail.com> wrote in message news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise
    time still seems to be slower than the fall time. It may be that the
    amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the amplifier by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to Liz Tuddenham on Fri Oct 18 08:36:15 2024
    On Fri, 18 Oct 2024 09:48:17 +0100, liz@poppyrecords.invalid.invalid
    (Liz Tuddenham) wrote:

    Edward Rawde <invalid@invalid.invalid> wrote:

    Is the reason why this doesn't produce a better looking sinewave because
    the amplifier slew rate is faster going down than it is going up or some
    other reason?

    Ignore the wild decoupling, it took me long enough to get the concept to
    work at all.

    I'm aware that a single package containing two op amps could probably do a >> much better job.

    if noise is more important than waveform, I found amplitude control by >clipping gave the lowest noise. The oscillators in this...

    <http://www.poppyrecords.co.uk/other/DistortionMeter/intermodmeter.htm>

    ...are amplitude stabilised by clipping.

    If the gain of an oscillator loop is close to 1.00, say 0.98 to 1.02,
    one can add in a small tweak, a crude multiplier or even a clipper, to
    make up the difference.

    Of course, with many-bit DACs being cheap nowadays, it's easier to do
    a DDS sine wave generator, and get super-precise frequency and
    amplitude. A 70 cent uP can do that, and even use PWM to eliminate the
    DAC.

    All sorts of elegant analog circuits are blown away by cheap digital
    junk. Sigh.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to invalid@invalid.invalid on Fri Oct 18 08:46:41 2024
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise
    time still seems to be slower than the fall time. It may be that the
    amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the amplifier >> by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize
    amplitude.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to Edward Rawde on Fri Oct 18 16:59:41 2024
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise
    time still seems to be slower than the fall time. It may be that the
    amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due
    to too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in response to Bill to produce a sine wave no matter what I do with the
    control loop gain.
    It either grows to clipping or dies.

    That's the main purpose behind having a thermistor or filament bulb in the
    f/b path.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to john larkin on Fri Oct 18 17:04:15 2024
    On Fri, 18 Oct 2024 08:36:15 -0700, john larkin wrote:

    On Fri, 18 Oct 2024 09:48:17 +0100, liz@poppyrecords.invalid.invalid
    (Liz Tuddenham) wrote:

    Edward Rawde <invalid@invalid.invalid> wrote:

    Is the reason why this doesn't produce a better looking sinewave
    because the amplifier slew rate is faster going down than it is going
    up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept
    to work at all.

    I'm aware that a single package containing two op amps could probably
    do a much better job.

    if noise is more important than waveform, I found amplitude control by >>clipping gave the lowest noise. The oscillators in this...

    <http://www.poppyrecords.co.uk/other/DistortionMeter/intermodmeter.htm>

    ...are amplitude stabilised by clipping.

    If the gain of an oscillator loop is close to 1.00, say 0.98 to 1.02,
    one can add in a small tweak, a crude multiplier or even a clipper, to
    make up the difference.

    Of course, with many-bit DACs being cheap nowadays, it's easier to do a
    DDS sine wave generator, and get super-precise frequency and amplitude.
    A 70 cent uP can do that, and even use PWM to eliminate the DAC.

    All sorts of elegant analog circuits are blown away by cheap digital
    junk. Sigh.

    Put the output you get from that through a spectrum analyzer and it won't
    look quite so super-duper.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to cd999666@notformail.com on Fri Oct 18 10:15:25 2024
    On Fri, 18 Oct 2024 17:04:15 -0000 (UTC), Cursitor Doom <cd999666@notformail.com> wrote:

    On Fri, 18 Oct 2024 08:36:15 -0700, john larkin wrote:

    On Fri, 18 Oct 2024 09:48:17 +0100, liz@poppyrecords.invalid.invalid
    (Liz Tuddenham) wrote:

    Edward Rawde <invalid@invalid.invalid> wrote:

    Is the reason why this doesn't produce a better looking sinewave
    because the amplifier slew rate is faster going down than it is going
    up or some other reason?

    Ignore the wild decoupling, it took me long enough to get the concept
    to work at all.

    I'm aware that a single package containing two op amps could probably
    do a much better job.

    if noise is more important than waveform, I found amplitude control by >>>clipping gave the lowest noise. The oscillators in this...

    <http://www.poppyrecords.co.uk/other/DistortionMeter/intermodmeter.htm>

    ...are amplitude stabilised by clipping.

    If the gain of an oscillator loop is close to 1.00, say 0.98 to 1.02,
    one can add in a small tweak, a crude multiplier or even a clipper, to
    make up the difference.

    Of course, with many-bit DACs being cheap nowadays, it's easier to do a
    DDS sine wave generator, and get super-precise frequency and amplitude.
    A 70 cent uP can do that, and even use PWM to eliminate the DAC.

    All sorts of elegant analog circuits are blown away by cheap digital
    junk. Sigh.

    Put the output you get from that through a spectrum analyzer and it won't >look quite so super-duper.

    Of course a DDS needs a post-DAC lowpass filter, but a 16 or 20 bit
    DAC can make extremely good sine waves.

    Just don't push the Nyquist rate.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Cursitor Doom on Fri Oct 18 13:47:02 2024
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise
    time still seems to be slower than the fall time. It may be that the
    amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due
    to too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in
    response to Bill to produce a sine wave no matter what I do with the
    control loop gain.
    It either grows to clipping or dies.

    That's the main purpose behind having a thermistor or filament bulb in the f/b path.

    Sure, but why use thermistors or filaments if you don't have to?
    Filaments don't last forever, particularly not if you drop your equipment, and filaments make me think of something like a 5U4.
    I forget when I last saw a filament. House lamps don't even have them now.

    I'm trying to make a low cost oscillator which produces the cleanest 1K Hz sinewave I can get, using only resistors, capacitors and
    semiconductors.

    There are plenty of examples online, but some of them don't seem to simulate. Whether that's because they do work in reality but not in simulation is hard to say.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to Edward Rawde on Fri Oct 18 17:58:53 2024
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the
    rise time still seems to be slower than the fall time. It may be
    that the amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due
    to too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in
    response to Bill to produce a sine wave no matter what I do with the
    control loop gain.
    It either grows to clipping or dies.

    That's the main purpose behind having a thermistor or filament bulb in
    the f/b path.

    Sure, but why use thermistors or filaments if you don't have to?
    Filaments don't last forever, particularly not if you drop your
    equipment, and filaments make me think of something like a 5U4.
    I forget when I last saw a filament. House lamps don't even have them
    now.

    I'm trying to make a low cost oscillator which produces the cleanest 1K
    Hz sinewave I can get, using only resistors, capacitors and
    semiconductors.

    There are plenty of examples online, but some of them don't seem to
    simulate.
    Whether that's because they do work in reality but not in simulation is
    hard to say.

    A real-world oscillator needs some kind of stimulus to start up. This
    could be a voltage 'shock' at switch-on or just inherent noise in the circuitry. JL informs me LTSpice doesn't have such a stimulus unless you provide it yourself. I suspect that's the main reason you will find
    oscillators difficult to get started in simulation.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Cursitor Doom on Fri Oct 18 14:20:48 2024
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the
    rise time still seems to be slower than the fall time. It may be
    that the amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due >>>>> to too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in
    response to Bill to produce a sine wave no matter what I do with the
    control loop gain.
    It either grows to clipping or dies.

    That's the main purpose behind having a thermistor or filament bulb in
    the f/b path.

    Sure, but why use thermistors or filaments if you don't have to?
    Filaments don't last forever, particularly not if you drop your
    equipment, and filaments make me think of something like a 5U4.
    I forget when I last saw a filament. House lamps don't even have them
    now.

    I'm trying to make a low cost oscillator which produces the cleanest 1K
    Hz sinewave I can get, using only resistors, capacitors and
    semiconductors.

    There are plenty of examples online, but some of them don't seem to
    simulate.
    Whether that's because they do work in reality but not in simulation is
    hard to say.

    A real-world oscillator needs some kind of stimulus to start up.

    I don't seem to be having startup problems, startup is fine but then it goes up to clipping or dies to nothing.
    I don't find this surprising and I'm wondering whether a real circuit would do the same.

    This could be a voltage 'shock' at switch-on or just inherent noise in the circuitry. JL informs me LTSpice doesn't have such a stimulus unless you provide it yourself. I suspect that's the main reason you will find oscillators difficult to get started in simulation.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to Edward Rawde on Fri Oct 18 19:28:02 2024
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the >>>>>>> rise time still seems to be slower than the fall time. It may be >>>>>>> that the amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier by uncoupling the Wien network and injecting test inputs. >>>>>>
    Elsewhere I think your amplitude control problems could be simply
    due to too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted
    in response to Bill to produce a sine wave no matter what I do with
    the control loop gain.
    It either grows to clipping or dies.

    That's the main purpose behind having a thermistor or filament bulb
    in the f/b path.

    Sure, but why use thermistors or filaments if you don't have to?
    Filaments don't last forever, particularly not if you drop your
    equipment, and filaments make me think of something like a 5U4.
    I forget when I last saw a filament. House lamps don't even have them
    now.

    I'm trying to make a low cost oscillator which produces the cleanest
    1K Hz sinewave I can get, using only resistors, capacitors and
    semiconductors.

    There are plenty of examples online, but some of them don't seem to
    simulate.
    Whether that's because they do work in reality but not in simulation
    is hard to say.

    A real-world oscillator needs some kind of stimulus to start up.

    I don't seem to be having startup problems, startup is fine but then it
    goes up to clipping or dies to nothing.
    I don't find this surprising and I'm wondering whether a real circuit
    would do the same.

    Yes, it's just what they do without some kind of dynamic gain control. The overall loop gain needs to be 1. Fixed resistors might give you that for a
    few seconds, but when something warms up, you're either damped or through
    the rails.


    This could be a voltage 'shock' at switch-on or just inherent noise in
    the circuitry. JL informs me LTSpice doesn't have such a stimulus
    unless you provide it yourself. I suspect that's the main reason you
    will find oscillators difficult to get started in simulation.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Cursitor Doom on Fri Oct 18 15:59:09 2024
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the >>>>>>>> rise time still seems to be slower than the fall time. It may be >>>>>>>> that the amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the >>>>>>> amplifier by uncoupling the Wien network and injecting test inputs. >>>>>>>
    Elsewhere I think your amplitude control problems could be simply >>>>>>> due to too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted >>>>>> in response to Bill to produce a sine wave no matter what I do with >>>>>> the control loop gain.
    It either grows to clipping or dies.

    That's the main purpose behind having a thermistor or filament bulb
    in the f/b path.

    Sure, but why use thermistors or filaments if you don't have to?
    Filaments don't last forever, particularly not if you drop your
    equipment, and filaments make me think of something like a 5U4.
    I forget when I last saw a filament. House lamps don't even have them
    now.

    I'm trying to make a low cost oscillator which produces the cleanest
    1K Hz sinewave I can get, using only resistors, capacitors and
    semiconductors.

    There are plenty of examples online, but some of them don't seem to
    simulate.
    Whether that's because they do work in reality but not in simulation
    is hard to say.

    A real-world oscillator needs some kind of stimulus to start up.

    I don't seem to be having startup problems, startup is fine but then it
    goes up to clipping or dies to nothing.
    I don't find this surprising and I'm wondering whether a real circuit
    would do the same.

    Yes, it's just what they do without some kind of dynamic gain control. The overall loop gain needs to be 1.

    Yes. That's why I have a control loop which in theory should do that.

    Any calculator will show that repeated multiplication of a number slightly greater than 1 increases without limit.
    In practice an amplifier will limit at or near the supply rail.
    And if the number it slightly less than 1 it will reduce to 0.

    A Wien bridge has an overall voltage gain of 1/3 so the circuit needs to be held at a gain of 3.

    As long as it starts up then the gain control loop should be able to hold the gain at whatever is needed for a specific output
    level.
    I'm still working on that.

    Fixed resistors might give you that for a
    few seconds, but when something warms up, you're either damped or through
    the rails.


    This could be a voltage 'shock' at switch-on or just inherent noise in
    the circuitry. JL informs me LTSpice doesn't have such a stimulus
    unless you provide it yourself. I suspect that's the main reason you
    will find oscillators difficult to get started in simulation.


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to Edward Rawde on Fri Oct 18 21:10:23 2024
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the >>>>>>>>> rise time still seems to be slower than the fall time. It may be >>>>>>>>> that the amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the >>>>>>>> amplifier by uncoupling the Wien network and injecting test
    inputs.

    Elsewhere I think your amplitude control problems could be simply >>>>>>>> due to too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted >>>>>>> in response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.

    That's the main purpose behind having a thermistor or filament bulb >>>>>> in the f/b path.

    Sure, but why use thermistors or filaments if you don't have to?
    Filaments don't last forever, particularly not if you drop your
    equipment, and filaments make me think of something like a 5U4.
    I forget when I last saw a filament. House lamps don't even have
    them now.

    I'm trying to make a low cost oscillator which produces the cleanest >>>>> 1K Hz sinewave I can get, using only resistors, capacitors and
    semiconductors.

    There are plenty of examples online, but some of them don't seem to
    simulate.
    Whether that's because they do work in reality but not in simulation >>>>> is hard to say.

    A real-world oscillator needs some kind of stimulus to start up.

    I don't seem to be having startup problems, startup is fine but then
    it goes up to clipping or dies to nothing.
    I don't find this surprising and I'm wondering whether a real circuit
    would do the same.

    Yes, it's just what they do without some kind of dynamic gain control.
    The overall loop gain needs to be 1.

    Yes. That's why I have a control loop which in theory should do that.

    Any calculator will show that repeated multiplication of a number
    slightly greater than 1 increases without limit.
    In practice an amplifier will limit at or near the supply rail.
    And if the number it slightly less than 1 it will reduce to 0.

    A Wien bridge has an overall voltage gain of 1/3 so the circuit needs to
    be held at a gain of 3.

    As long as it starts up then the gain control loop should be able to
    hold the gain at whatever is needed for a specific output level.
    I'm still working on that.

    Without doubt, it's the trickiest aspect of the design. Definitely do-able though. Let us know how you get on.


    Fixed resistors might give you that for a
    few seconds, but when something warms up, you're either damped or
    through the rails.


    This could be a voltage 'shock' at switch-on or just inherent noise
    in the circuitry. JL informs me LTSpice doesn't have such a stimulus
    unless you provide it yourself. I suspect that's the main reason you
    will find oscillators difficult to get started in simulation.


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Cursitor Doom on Fri Oct 18 17:19:35 2024
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    SHEET 1 2196 916
    WIRE -160 -160 -256 -160
    WIRE -16 -160 -160 -160
    WIRE 160 -160 -16 -160
    WIRE 400 -160 224 -160
    WIRE -160 -144 -160 -160
    WIRE -256 -128 -256 -160
    WIRE 400 -128 400 -160
    WIRE -16 -80 -16 -160
    WIRE -256 -32 -256 -64
    WIRE -160 -32 -160 -64
    WIRE -160 -32 -256 -32
    WIRE -48 -32 -160 -32
    WIRE 112 -32 48 -32
    WIRE 208 -32 192 -32
    WIRE 272 -32 208 -32
    WIRE 400 -32 400 -48
    WIRE 400 -32 352 -32
    WIRE -352 32 -480 32
    WIRE 128 32 -352 32
    WIRE 208 64 208 -32
    WIRE 208 64 48 64
    WIRE -480 80 -480 32
    WIRE 128 96 128 32
    WIRE -352 112 -352 32
    WIRE 48 112 48 64
    WIRE 96 112 48 112
    WIRE 384 128 160 128
    WIRE 400 128 400 -32
    WIRE 400 128 384 128
    WIRE 480 128 400 128
    WIRE 544 128 480 128
    WIRE 96 144 -80 144
    WIRE -80 224 -80 144
    WIRE 16 224 -80 224
    WIRE 176 224 16 224
    WIRE 256 224 240 224
    WIRE 384 224 384 128
    WIRE 384 224 336 224
    WIRE -80 240 -80 224
    WIRE 16 240 16 224
    WIRE -480 320 -480 160
    WIRE -480 320 -560 320
    WIRE -560 336 -560 320
    WIRE -480 336 -480 320
    WIRE -352 336 -352 176
    WIRE -352 336 -480 336
    WIRE -336 336 -352 336
    WIRE -256 336 -256 -32
    WIRE -256 336 -336 336
    WIRE -80 336 -80 320
    WIRE -80 336 -256 336
    WIRE 16 336 16 304
    WIRE 16 336 -80 336
    WIRE -480 464 -480 336
    WIRE -336 496 -336 336
    WIRE -480 656 -480 544
    WIRE -336 656 -336 560
    WIRE -336 656 -480 656
    WIRE 128 656 128 160
    WIRE 128 656 -336 656
    FLAG 480 128 output
    FLAG -560 336 0
    DATAFLAG -432 32 "round(($)*100)/100"
    DATAFLAG 64 -32 "round(($)*100)/100"
    DATAFLAG 240 -32 "round(($)*100)/100"
    DATAFLAG 64 -160 "round(($)*100)/100"
    DATAFLAG 288 -160 "round(($)*100)/100"
    SYMBOL voltage -480 64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 352 208 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 12k
    SYMBOL cap 240 208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 15n
    SYMBOL cap 32 304 R180
    WINDOW 0 -33 54 Left 2
    WINDOW 3 -49 18 Left 2
    SYMATTR InstName C2
    SYMATTR Value 15n
    SYMBOL polcap -368 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100µ
    SYMBOL OpAmps\\LT1057 128 64 R0
    SYMATTR InstName U2
    SYMBOL res -176 -160 R0
    SYMATTR InstName R6
    SYMATTR Value 47k
    SYMBOL res 208 -48 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 4.7k
    SYMBOL res 368 -48 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL diode 160 -144 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL res 384 -144 R0
    SYMATTR InstName R9
    SYMATTR Value 4.7k
    SYMBOL njf 48 -80 R90
    WINDOW 0 -38 17 VRight 2
    WINDOW 3 -7 -47 VRight 2
    SYMATTR InstName J1
    SYMATTR Value 2N3819
    SYMBOL voltage -480 448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL polcap -352 496 R0
    SYMATTR InstName C5
    SYMATTR Value 100µ
    SYMBOL res -96 224 R0
    SYMATTR InstName R2
    SYMATTR Value 12k
    SYMBOL polcap -240 -64 R180
    WINDOW 0 -35 53 Left 2
    WINDOW 3 -47 17 Left 2
    SYMATTR InstName C3
    SYMATTR Value 10µ
    TEXT -464 352 Left 2 !.tran 10

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Cursitor Doom@21:1/5 to Edward Rawde on Fri Oct 18 22:15:48 2024
    On Fri, 18 Oct 2024 17:19:35 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely
    do-able though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-
    the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4 SHEET 1 2196 916 WIRE -160 -160 -256 -160 WIRE -16 -160 -160

    In your simulation? I can't tell, I'm afraid. I don't have LTspice (or
    even Wine which Linux needs) installed on this laptop and I won't have
    access to anything that does have it until Monday. Sorry about that.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jeroen Belleman@21:1/5 to Edward Rawde on Sat Oct 19 00:19:35 2024
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able >> though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Jeroen Belleman

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jeroen@nospam.please on Fri Oct 18 18:28:09 2024
    On Sat, 19 Oct 2024 00:19:35 +0200, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able >>> though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Yes. The key was that they are thermal in principle, and yield a pure resistance that responds too slowly to follow the 1 KHz signal being
    generated, and so cause no parametric waveform distortion.

    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to jeroen@nospam.please on Fri Oct 18 15:44:26 2024
    On Sat, 19 Oct 2024 00:19:35 +0200, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able >>> though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Jeroen Belleman

    But tricky to Spice.

    And a thermal device of course makes the amplitude temperature
    sensitive, especially when the heating goes directly as the square of
    the sine amplitude.

    It would be better to have the native loop gain very close to 1.00 and
    give the AGC mechanism a small influence, like +- a few per cent
    maybe.

    A mosfet would make a decent voltage-controlled gain element, with
    that small influence.

    There are still analog multiplier chips around. Barely.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Jeroen Belleman on Fri Oct 18 18:58:43 2024
    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able >>> though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Ok thanks Jeroen.

    It looks like the best approach for the gain control is either a filament or something like that used in the document Bill Sloman
    posted.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    Either that or an analog multiplier of some sort.



    Jeroen Belleman


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to john larkin on Fri Oct 18 19:24:34 2024
    "john larkin" <jl@glen--canyon.com> wrote in message news:qfo5hj5vqpi357bsads868ska3ap7k16rc@4ax.com...
    On Sat, 19 Oct 2024 00:19:35 +0200, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able >>>> though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Jeroen Belleman

    But tricky to Spice.

    And a thermal device of course makes the amplitude temperature
    sensitive, especially when the heating goes directly as the square of
    the sine amplitude.

    It would be better to have the native loop gain very close to 1.00 and
    give the AGC mechanism a small influence, like +- a few per cent
    maybe.

    Attempting to reduce the gain control range of the FET seems to run into other issues which I've seen in other simulations.
    The lower amplitue parts of the signal produced by this ciruit look nice and clean.
    Now I just need a way to stop it generating an AM radio signal.
    Manual adjustment of R8 is likely to be needed in any real circuit.

    Version 4
    SHEET 1 2196 916
    WIRE -160 -224 -256 -224
    WIRE -16 -224 -160 -224
    WIRE 160 -224 -16 -224
    WIRE 400 -224 224 -224
    WIRE -160 -208 -160 -224
    WIRE -256 -192 -256 -224
    WIRE 400 -192 400 -224
    WIRE -16 -144 -16 -224
    WIRE -256 -96 -256 -128
    WIRE -160 -96 -160 -128
    WIRE -160 -96 -256 -96
    WIRE -80 -96 -160 -96
    WIRE -48 -96 -80 -96
    WIRE 80 -96 48 -96
    WIRE 112 -96 80 -96
    WIRE 208 -96 192 -96
    WIRE 272 -96 208 -96
    WIRE 400 -96 400 -112
    WIRE 400 -96 352 -96
    WIRE -80 -32 -80 -96
    WIRE -48 -32 -80 -32
    WIRE 80 -32 80 -96
    WIRE 80 -32 32 -32
    WIRE -352 32 -480 32
    WIRE 128 32 -352 32
    WIRE 208 64 208 -96
    WIRE 208 64 48 64
    WIRE -480 80 -480 32
    WIRE 128 96 128 32
    WIRE -352 112 -352 32
    WIRE 48 112 48 64
    WIRE 96 112 48 112
    WIRE 384 128 160 128
    WIRE 400 128 400 -96
    WIRE 400 128 384 128
    WIRE 528 128 400 128
    WIRE 560 128 528 128
    WIRE 96 144 -80 144
    WIRE -80 224 -80 144
    WIRE 16 224 -80 224
    WIRE 176 224 16 224
    WIRE 256 224 240 224
    WIRE 384 224 384 128
    WIRE 384 224 336 224
    WIRE -80 240 -80 224
    WIRE 16 240 16 224
    WIRE -480 320 -480 160
    WIRE -480 320 -560 320
    WIRE -560 336 -560 320
    WIRE -480 336 -480 320
    WIRE -352 336 -352 176
    WIRE -352 336 -480 336
    WIRE -336 336 -352 336
    WIRE -256 336 -256 -96
    WIRE -256 336 -336 336
    WIRE -80 336 -80 320
    WIRE -80 336 -256 336
    WIRE 16 336 16 304
    WIRE 16 336 -80 336
    WIRE -480 464 -480 336
    WIRE -336 496 -336 336
    WIRE -480 656 -480 544
    WIRE -336 656 -336 560
    WIRE -336 656 -480 656
    WIRE 128 656 128 160
    WIRE 128 656 -336 656
    FLAG 528 128 output
    FLAG -560 336 0
    DATAFLAG -432 32 "round(($)*100)/100"
    DATAFLAG 64 -96 "round(($)*100)/100"
    DATAFLAG 240 -96 "round(($)*100)/100"
    DATAFLAG 64 -224 "round(($)*100)/100"
    DATAFLAG 288 -224 "round(($)*100)/100"
    SYMBOL voltage -480 64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 352 208 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 12k
    SYMBOL cap 240 208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 15n
    SYMBOL cap 32 304 R180
    WINDOW 0 -33 54 Left 2
    WINDOW 3 -49 18 Left 2
    SYMATTR InstName C2
    SYMATTR Value 15n
    SYMBOL polcap -368 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100µ
    SYMBOL OpAmps\\LT1057 128 64 R0
    SYMATTR InstName U2
    SYMBOL res -176 -224 R0
    SYMATTR InstName R6
    SYMATTR Value 47k
    SYMBOL res 208 -112 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 4.7k
    SYMBOL res 368 -112 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 11500
    SYMBOL diode 160 -208 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL res 384 -208 R0
    SYMATTR InstName R9
    SYMATTR Value 10k
    SYMBOL njf 48 -144 R90
    WINDOW 0 -38 17 VRight 2
    WINDOW 3 -7 -47 VRight 2
    SYMATTR InstName J1
    SYMATTR Value 2N3819
    SYMBOL voltage -480 448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL polcap -352 496 R0
    SYMATTR InstName C5
    SYMATTR Value 100µ
    SYMBOL res -96 224 R0
    SYMATTR InstName R2
    SYMATTR Value 12k
    SYMBOL polcap -240 -128 R180
    WINDOW 0 -35 53 Left 2
    WINDOW 3 -47 17 Left 2
    SYMATTR InstName C3
    SYMATTR Value 10µ
    SYMBOL res 48 -48 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 1.5K
    TEXT -464 352 Left 2 !.tran 5

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to invalid@invalid.invalid on Fri Oct 18 19:12:00 2024
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able >>>> though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Ok thanks Jeroen.

    It looks like the best approach for the gain control is either a filament or something like that used in the document Bill Sloman
    posted.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    Note that the LDR has a very small influence range on the loop gain.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to john larkin on Fri Oct 18 23:03:20 2024
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able
    though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Ok thanks Jeroen.

    It looks like the best approach for the gain control is either a filament or something like that used in the document Bill Sloman
    posted.
    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    Note that the LDR has a very small influence range on the loop gain.


    That's why I added R3 in this circuit.
    It does not seem to be safe to reduce R3 below 1k.

    R4 helps a lot too for reasons I don't fully understand.
    It may be moving the FET to a better part of its operating characteristics.

    A single rail version also works with another op amp producing 6V for R4 and two 20k resistors for R2 between 12V and 0V.
    As expected, this produces twice the output voltage and I've not found a way to reduce it.

    This will probably be my final offering for a 1KHz sinewave oscillator unless anyone can suggest improvements without using light
    dependent resistors.
    From the LTSpice plot, I can't discern any impurity in the signal this circuit produces.
    It would be interesting to see what a real circuit and a spectrum analyzer says but I probably won't be building it.

    I haven't used an LDR since playing with an ORP12 around age 10.
    I seem to remember that they can degrade over time but maybe that only happens in sunlight.

    Version 4
    SHEET 1 2196 916
    WIRE -160 -304 -256 -304
    WIRE -16 -304 -160 -304
    WIRE 160 -304 -16 -304
    WIRE 400 -304 224 -304
    WIRE -160 -272 -160 -304
    WIRE 400 -272 400 -304
    WIRE -256 -256 -256 -304
    WIRE -16 -208 -16 -304
    WIRE -256 -160 -256 -192
    WIRE -256 -160 -288 -160
    WIRE -160 -160 -160 -192
    WIRE -160 -160 -256 -160
    WIRE -80 -160 -160 -160
    WIRE -48 -160 -80 -160
    WIRE 80 -160 48 -160
    WIRE 112 -160 80 -160
    WIRE 208 -160 192 -160
    WIRE 272 -160 208 -160
    WIRE 400 -160 400 -192
    WIRE 400 -160 352 -160
    WIRE -288 -112 -288 -160
    WIRE -80 -96 -80 -160
    WIRE -48 -96 -80 -96
    WIRE 80 -96 80 -160
    WIRE 80 -96 32 -96
    WIRE 208 -48 208 -160
    WIRE 208 -48 48 -48
    WIRE 272 -48 208 -48
    WIRE 400 -48 400 -160
    WIRE 400 -48 352 -48
    WIRE -384 32 -512 32
    WIRE 128 32 -384 32
    WIRE -512 80 -512 32
    WIRE 128 96 128 32
    WIRE -384 112 -384 32
    WIRE 48 112 48 -48
    WIRE 96 112 48 112
    WIRE 384 128 160 128
    WIRE 400 128 400 -48
    WIRE 400 128 384 128
    WIRE 528 128 400 128
    WIRE 560 128 528 128
    WIRE 96 144 -80 144
    WIRE -80 224 -80 144
    WIRE 16 224 -80 224
    WIRE 176 224 16 224
    WIRE 256 224 240 224
    WIRE 384 224 384 128
    WIRE 384 224 336 224
    WIRE -80 240 -80 224
    WIRE 16 240 16 224
    WIRE -512 320 -512 160
    WIRE -512 320 -592 320
    WIRE -592 336 -592 320
    WIRE -512 336 -512 320
    WIRE -384 336 -384 176
    WIRE -384 336 -512 336
    WIRE -368 336 -384 336
    WIRE -288 336 -288 -32
    WIRE -288 336 -368 336
    WIRE -80 336 -80 320
    WIRE -80 336 -288 336
    WIRE 16 336 16 304
    WIRE 16 336 -80 336
    WIRE -512 464 -512 336
    WIRE -368 496 -368 336
    WIRE -512 656 -512 544
    WIRE -368 656 -368 560
    WIRE -368 656 -512 656
    WIRE 128 656 128 160
    WIRE 128 656 -368 656
    FLAG 528 128 output
    FLAG -592 336 0
    DATAFLAG -464 32 "round(($)*100)/100"
    DATAFLAG 64 -160 "round(($)*100)/100"
    DATAFLAG 240 -160 "round(($)*100)/100"
    DATAFLAG 64 -304 "round(($)*100)/100"
    DATAFLAG 288 -304 "round(($)*100)/100"
    SYMBOL voltage -512 64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 352 208 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 10k
    SYMBOL cap 240 208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 15n
    SYMBOL cap 32 304 R180
    WINDOW 0 -33 54 Left 2
    WINDOW 3 -49 18 Left 2
    SYMATTR InstName C2
    SYMATTR Value 15n
    SYMBOL polcap -400 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100µ
    SYMBOL OpAmps\\LT1057 128 64 R0
    SYMATTR InstName U2
    SYMBOL res -176 -288 R0
    SYMATTR InstName R6
    SYMATTR Value 47k
    SYMBOL res 208 -176 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 4.7k
    SYMBOL res 368 -176 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 12k
    SYMBOL diode 160 -288 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL res 384 -288 R0
    SYMATTR InstName R9
    SYMATTR Value 1k
    SYMBOL njf 48 -208 R90
    WINDOW 0 -39 17 VRight 2
    WINDOW 3 -10 -13 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -512 448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL polcap -384 496 R0
    SYMATTR InstName C5
    SYMATTR Value 100µ
    SYMBOL res -96 224 R0
    SYMATTR InstName R2
    SYMATTR Value 10k
    SYMBOL polcap -240 -192 R180
    WINDOW 0 -35 53 Left 2
    WINDOW 3 -47 17 Left 2
    SYMATTR InstName C3
    SYMATTR Value 10µ
    SYMBOL res 48 -112 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 1k
    SYMBOL res -272 -16 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R4
    SYMATTR Value 150
    SYMBOL res 368 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R5
    SYMATTR Value 270k
    TEXT -496 352 Left 2 !.tran 3
    TEXT -536 -392 Left 2 ;Edward Rawde's 1KHz sinewave oscillator. 18 Oct 2024.\nCan the sine purity be inproved any further?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to invalid@invalid.invalid on Fri Oct 18 20:24:14 2024
    On Fri, 18 Oct 2024 23:03:20 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able
    though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Ok thanks Jeroen.

    It looks like the best approach for the gain control is either a filament or something like that used in the document Bill Sloman
    posted.
    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    Note that the LDR has a very small influence range on the loop gain.


    That's why I added R3 in this circuit.
    It does not seem to be safe to reduce R3 below 1k.

    R4 helps a lot too for reasons I don't fully understand.
    It may be moving the FET to a better part of its operating characteristics.

    A single rail version also works with another op amp producing 6V for R4 and two 20k resistors for R2 between 12V and 0V.
    As expected, this produces twice the output voltage and I've not found a way to reduce it.

    This will probably be my final offering for a 1KHz sinewave oscillator unless anyone can suggest improvements without using light
    dependent resistors.
    From the LTSpice plot, I can't discern any impurity in the signal this circuit produces.
    It would be interesting to see what a real circuit and a spectrum analyzer says but I probably won't be building it.

    I haven't used an LDR since playing with an ORP12 around age 10.
    I seem to remember that they can degrade over time but maybe that only happens in sunlight.


    LDRs are awful. Drifty, nonlinear, bad frequency response. But with a
    small influence, inside a tight control loop, they will work.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Liz Tuddenham@21:1/5 to Cursitor Doom on Sat Oct 19 09:58:13 2024
    Cursitor Doom <cd999666@notformail.com> wrote:

    emiconductors.

    There are plenty of examples online, but some of them don't seem to >>>>> simulate.
    Whether that's because they do work in reality but not in simulation >>>>> is hard to say.

    A real-world oscillator needs some kind of stimulus to start up.

    I don't seem to be having startup problems, startup is fine but then
    it goes up to clipping or dies to nothing.
    I don't find this surprising and I'm wondering whether a real circuit
    would do the same.

    Yes, it's just what they do without some kind of dynamic gain control.
    The overall loop gain needs to be 1.

    Yes. That's why I have a control loop which in theory should do that.

    Any calculator will show that repeated multiplication of a number
    slightly greater than 1 increases without limit.
    In practice an amplifier will limit at or near the supply rail.
    And if the number it slightly less than 1 it will reduce to 0.

    A Wien bridge has an overall voltage gain of 1/3 so the circuit needs to
    be held at a gain of 3.

    As long as it starts up then the gain control loop should be able to
    hold the gain at whatever is needed for a specific output level.
    I'm still working on that.

    Without doubt, it's the trickiest aspect of the design. Definitely do-able though. Let us know how you get on.


    Fixed resistors might give you that for a
    few seconds, but when something warms up, you're either damped or
    through the rails.


    This could be a voltage 'shock' at switch-on or just inherent noise
    in the circuitry. JL informs me LTSpice doesn't have such a stimulus >>>> unless you provide it yourself. I suspect that's the main reason you >>>> will find oscillators difficult to get started in simulation.



    --
    ~ Liz Tuddenham ~
    (Remove the ".invalid"s and add ".co.uk" to reply)
    www.poppyrecords.co.uk

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Liz Tuddenham@21:1/5 to Edward Rawde on Sat Oct 19 09:58:13 2024
    Edward Rawde <invalid@invalid.invalid> wrote:

    [...]
    A Wien bridge has an overall voltage gain of 1/3 ...

    If all the components are perfect and correctly matched.

    In a practical oscillator where the resistors are switched or the
    capacitors ganged, there will be slight mis-matches due to tolerances
    and the loss will be greater (and unpredictable).


    --
    ~ Liz Tuddenham ~
    (Remove the ".invalid"s and add ".co.uk" to reply)
    www.poppyrecords.co.uk

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Sat Oct 19 19:27:52 2024
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able
    though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here.

    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Ok thanks Jeroen.

    It looks like the best approach for the gain control is either a filament or something like that used in the document Bill Sloman
    posted.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    Note that the LDR has a very small influence range on the loop gain.


    That's why I added R3 in this circuit.
    It does not seem to be safe to reduce R3 below 1k.

    R4 helps a lot too for reasons I don't fully understand.
    It may be moving the FET to a better part of its operating characteristics.

    A single rail version also works with another op amp producing 6V for R4 and two 20k resistors for R2 between 12V and 0V.
    As expected, this produces twice the output voltage and I've not found a way to reduce it.

    This will probably be my final offering for a 1KHz sinewave oscillator unless anyone can suggest improvements without using light
    dependent resistors.
    From the LTSpice plot, I can't discern any impurity in the signal this circuit produces.
    It would be interesting to see what a real circuit and a spectrum analyzer says but I probably won't be building it.

    I haven't used an LDR since playing with an ORP12 around age 10.
    I seem to remember that they can degrade over time but maybe that only happens in sunlight.

    I got your earlier circuit to work a lot better simply by increasing R7
    to 5.6k. If you use the View option on the trace viewing panel to pull
    out an FFT of the output (I use Blackmann-Harris windowing) from 10sec
    to 20 sec, you can see that second harmonic distortion is about 20dB
    below the primary - not great but better than it was.

    And the waveform looks like a sine wave.

    The less influence the FET has on the gain of the circuit, the better
    the sine wave.

    The AD734 would do a lot better - or at least it does in my simulations
    - but it isn't cheap.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Liz Tuddenham on Sat Oct 19 23:17:25 2024
    On 19/10/2024 7:58 pm, Liz Tuddenham wrote:
    Edward Rawde <invalid@invalid.invalid> wrote:

    [...]
    A Wien bridge has an overall voltage gain of 1/3 ...

    If all the components are perfect and correctly matched.

    In a practical oscillator where the resistors are switched or the
    capacitors ganged, there will be slight mis-matches due to tolerances
    and the loss will be greater (and unpredictable).

    The whole point about Wein bridges is that they are perfectly linear.

    You have to introduce a controllable non-linearity that lets you tweak
    the gain to be exactly three when they are oscillating at the right
    amplitude, and dial it back if the amplitude is too big, or dial it up
    if it is too low.

    In practice tolerance on the two crucial capacitors and resistors means
    that the gain for stable output is never going to be exactly three.

    Just for kicks I simulated one with a thirty degree phase shift in the
    RC pairs (rather than the classical forty five degree phase shift) and
    it worked fine too.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to john larkin on Sat Oct 19 23:32:21 2024
    On 19/10/2024 2:36 am, john larkin wrote:
    On Fri, 18 Oct 2024 09:48:17 +0100, liz@poppyrecords.invalid.invalid
    (Liz Tuddenham) wrote:

    Edward Rawde <invalid@invalid.invalid> wrote:

    Is the reason why this doesn't produce a better looking sinewave because >>> the amplifier slew rate is faster going down than it is going up or some >>> other reason?

    Ignore the wild decoupling, it took me long enough to get the concept to >>> work at all.

    I'm aware that a single package containing two op amps could probably do a >>> much better job.

    if noise is more important than waveform, I found amplitude control by
    clipping gave the lowest noise. The oscillators in this...

    <http://www.poppyrecords.co.uk/other/DistortionMeter/intermodmeter.htm>

    ...are amplitude stabilised by clipping.

    If the gain of an oscillator loop is close to 1.00, say 0.98 to 1.02,
    one can add in a small tweak, a crude multiplier or even a clipper, to
    make up the difference.

    Clipper's add harmonic content. Multipliers can do better. The AD734
    adds some harmonic content but it can be 70dB below the fundamental, and
    if the tweak you need is 50dD below the main signal path, your op amp
    will add as much.

    Of course, with many-bit DACs being cheap nowadays, it's easier to do
    a DDS sine wave generator, and get super-precise frequency and
    amplitude. A 70 cent uP can do that, and even use PWM to eliminate the
    DAC.

    Sigma-delta DACs do rely on pulse width modulation.
    A well-designed Wein bridge can keep the harmonic content of the output
    120dD below the fundamental, and DDS devices can't do that without heavy filtering of the output.

    All sorts of elegant analog circuits are blown away by cheap digital
    junk. Sigh.

    Cheap digital junk doesn't blow away a well-designed Wein bridge. It may
    blow away anything that John Larkin can design, but that's a different competition.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sat Oct 19 12:36:42 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able
    though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here. >>>>>>
    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the
    top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Ok thanks Jeroen.

    It looks like the best approach for the gain control is either a filament or something like that used in the document Bill
    Sloman
    posted.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    Note that the LDR has a very small influence range on the loop gain.


    That's why I added R3 in this circuit.
    It does not seem to be safe to reduce R3 below 1k.

    R4 helps a lot too for reasons I don't fully understand.
    It may be moving the FET to a better part of its operating characteristics. >>
    A single rail version also works with another op amp producing 6V for R4 and two 20k resistors for R2 between 12V and 0V.
    As expected, this produces twice the output voltage and I've not found a way to reduce it.

    This will probably be my final offering for a 1KHz sinewave oscillator unless anyone can suggest improvements without using light
    dependent resistors.
    From the LTSpice plot, I can't discern any impurity in the signal this circuit produces.
    It would be interesting to see what a real circuit and a spectrum analyzer says but I probably won't be building it.

    I haven't used an LDR since playing with an ORP12 around age 10.
    I seem to remember that they can degrade over time but maybe that only happens in sunlight.

    I got your earlier circuit to work a lot better simply by increasing R7 to 5.6k. If you use the View option on the trace viewing
    panel to pull out an FFT of the output (I use Blackmann-Harris windowing) from 10sec to 20 sec, you can see that second harmonic
    distortion is about 20dB below the primary - not great but better than it was.

    And the waveform looks like a sine wave.

    The less influence the FET has on the gain of the circuit, the better the sine wave.


    If you run this circuit then View, FFT, Use current zoom extent, Ok
    It implies that unwanted harmonics are 40dB down.
    I'm not sure I believe that but if true then it's not bad for a very low cost circuit.

    Version 4
    SHEET 1 2196 916
    WIRE -160 -304 -256 -304
    WIRE -16 -304 -160 -304
    WIRE 96 -304 -16 -304
    WIRE 160 -304 96 -304
    WIRE 400 -304 224 -304
    WIRE -160 -272 -160 -304
    WIRE 96 -272 96 -304
    WIRE 400 -272 400 -304
    WIRE -256 -256 -256 -304
    WIRE -16 -208 -16 -304
    WIRE -256 -160 -256 -192
    WIRE -256 -160 -288 -160
    WIRE -160 -160 -160 -192
    WIRE -160 -160 -256 -160
    WIRE -80 -160 -160 -160
    WIRE -48 -160 -80 -160
    WIRE 80 -160 48 -160
    WIRE 96 -160 96 -192
    WIRE 96 -160 80 -160
    WIRE 112 -160 96 -160
    WIRE 208 -160 192 -160
    WIRE 272 -160 208 -160
    WIRE 400 -160 400 -192
    WIRE 400 -160 352 -160
    WIRE -288 -112 -288 -160
    WIRE -80 -96 -80 -160
    WIRE -48 -96 -80 -96
    WIRE 80 -96 80 -160
    WIRE 80 -96 32 -96
    WIRE 208 -48 208 -160
    WIRE 208 -48 48 -48
    WIRE 272 -48 208 -48
    WIRE 400 -48 400 -160
    WIRE 400 -48 352 -48
    WIRE -384 32 -512 32
    WIRE 128 32 -384 32
    WIRE -512 80 -512 32
    WIRE 128 96 128 32
    WIRE -384 112 -384 32
    WIRE 48 112 48 -48
    WIRE 96 112 48 112
    WIRE 384 128 160 128
    WIRE 400 128 400 -48
    WIRE 400 128 384 128
    WIRE 528 128 400 128
    WIRE 608 128 528 128
    WIRE 96 144 -80 144
    WIRE -80 208 -80 144
    WIRE -80 208 -176 208
    WIRE -80 224 -80 208
    WIRE 16 224 -80 224
    WIRE 176 224 16 224
    WIRE 256 224 240 224
    WIRE 384 224 384 128
    WIRE 384 224 336 224
    WIRE -176 240 -176 208
    WIRE -80 240 -80 224
    WIRE 16 240 16 224
    WIRE -512 320 -512 160
    WIRE -512 320 -592 320
    WIRE -592 336 -592 320
    WIRE -512 336 -512 320
    WIRE -384 336 -384 176
    WIRE -384 336 -512 336
    WIRE -368 336 -384 336
    WIRE -288 336 -288 -32
    WIRE -288 336 -368 336
    WIRE -176 336 -176 320
    WIRE -176 336 -288 336
    WIRE -80 336 -80 320
    WIRE -80 336 -176 336
    WIRE 16 336 16 304
    WIRE 16 336 -80 336
    WIRE -512 464 -512 336
    WIRE -368 496 -368 336
    WIRE -512 656 -512 544
    WIRE -368 656 -368 560
    WIRE -368 656 -512 656
    WIRE 128 656 128 160
    WIRE 128 656 -368 656
    FLAG 528 128 output
    FLAG -592 336 0
    DATAFLAG -464 32 "round(($)*100)/100"
    DATAFLAG 64 -160 "round(($)*100)/100"
    DATAFLAG 240 -160 "round(($)*100)/100"
    DATAFLAG 64 -304 "round(($)*100)/100"
    DATAFLAG 288 -304 "round(($)*100)/100"
    SYMBOL voltage -512 64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 352 208 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 10k
    SYMBOL cap 240 208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 15n
    SYMBOL cap 32 304 R180
    WINDOW 0 -33 54 Left 2
    WINDOW 3 -49 18 Left 2
    SYMATTR InstName C2
    SYMATTR Value 15n
    SYMBOL polcap -400 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100µ
    SYMBOL OpAmps\\LT1057 128 64 R0
    SYMATTR InstName U2
    SYMBOL res -176 -288 R0
    SYMATTR InstName R6
    SYMATTR Value 47k
    SYMBOL res 208 -176 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 4.7k
    SYMBOL res 368 -176 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 12k
    SYMBOL diode 160 -288 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL res 384 -288 R0
    SYMATTR InstName R9
    SYMATTR Value 1k
    SYMBOL njf 48 -208 R90
    WINDOW 0 -39 17 VRight 2
    WINDOW 3 -10 -13 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -512 448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL polcap -384 496 R0
    SYMATTR InstName C5
    SYMATTR Value 100µ
    SYMBOL res -96 224 R0
    SYMATTR InstName R2
    SYMATTR Value 12k
    SYMBOL polcap -240 -192 R180
    WINDOW 0 -35 53 Left 2
    WINDOW 3 -47 17 Left 2
    SYMATTR InstName C3
    SYMATTR Value 10µ
    SYMBOL res 48 -112 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 1k
    SYMBOL res -272 -16 R180
    WINDOW 0 36 76 Left 2
    WINDOW 3 36 40 Left 2
    SYMATTR InstName R4
    SYMATTR Value 180
    SYMBOL res 368 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R5
    SYMATTR Value 270k
    SYMBOL res 80 -288 R0
    WINDOW 0 36 43 Left 2
    WINDOW 3 36 65 Left 2
    SYMATTR InstName R10
    SYMATTR Value 150k
    SYMBOL res -192 224 R0
    SYMATTR InstName R11
    SYMATTR Value 100k
    TEXT -496 352 Left 2 !.tran 0 3 2.5
    TEXT -536 -392 Left 2 ;Edward Rawde's 1KHz sinewave oscillator. 19 Oct 2024.\nCan the sine purity be improved any further?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From piglet@21:1/5 to john larkin on Sat Oct 19 20:13:12 2024
    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise
    time still seems to be slower than the fall time. It may be that the
    amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the amplifier >>> by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due to >>> too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize amplitude.



    Here is an amusing oscillator that has a voltage follower as the active
    stage - it has no voltage gain so some people say it cannot work - they
    are wrong of course.

    Amplitude grows to power rail limits and non-linearities creep in.


    Version 4
    SHEET 1 1132 680
    WIRE 640 -272 400 -272
    WIRE 784 -272 640 -272
    WIRE 928 -272 784 -272
    WIRE 1072 -272 928 -272
    WIRE 640 -224 640 -272
    WIRE 400 -144 400 -272
    WIRE 784 -144 784 -272
    WIRE 640 -96 640 -144
    WIRE 720 -96 640 -96
    WIRE 640 -64 640 -96
    WIRE 928 -48 928 -272
    WIRE 1072 -48 1072 -272
    WIRE 272 -16 64 -16
    WIRE 400 -16 400 -64
    WIRE 400 -16 336 -16
    WIRE 432 -16 400 -16
    WIRE 576 -16 432 -16
    WIRE 784 0 784 -48
    WIRE 864 0 784 0
    WIRE 432 32 432 -16
    WIRE 784 48 784 0
    WIRE 64 96 64 -16
    WIRE 160 96 64 96
    WIRE 304 96 240 96
    WIRE 1072 112 1072 32
    WIRE 64 128 64 96
    WIRE 432 160 432 112
    WIRE 784 176 784 128
    WIRE 64 224 64 192
    WIRE 160 224 64 224
    WIRE 304 224 304 96
    WIRE 304 224 240 224
    WIRE 640 224 640 32
    WIRE 880 224 640 224
    WIRE 928 224 928 48
    WIRE 928 224 880 224
    WIRE 64 256 64 224
    WIRE 928 304 928 224
    WIRE 64 352 64 320
    WIRE 160 352 64 352
    WIRE 304 352 304 224
    WIRE 304 352 240 352
    WIRE 640 352 640 224
    WIRE 640 352 304 352
    WIRE 64 384 64 352
    WIRE 928 464 928 384
    WIRE 64 480 64 448
    FLAG 432 160 0
    FLAG 928 464 0
    FLAG 64 480 0
    FLAG 1072 112 0
    FLAG 784 176 0
    FLAG 880 224 OUT
    SYMBOL res 256 368 M270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R1
    SYMATTR Value 470
    SYMBOL res 256 240 M270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R2
    SYMATTR Value 4700
    SYMBOL res 256 112 M270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R3
    SYMATTR Value 47k
    SYMBOL cap 80 384 M0
    SYMATTR InstName C1
    SYMATTR Value 100n
    SYMBOL cap 80 128 M0
    SYMATTR InstName C3
    SYMATTR Value 1n
    SYMBOL cap 80 256 M0
    SYMATTR InstName C2
    SYMATTR Value 10n
    SYMBOL npn 720 -144 R0
    SYMATTR InstName Q2
    SYMATTR Value 2N2222
    SYMBOL voltage 1072 -64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value 20
    SYMBOL res 416 16 R0
    SYMATTR InstName R5
    SYMATTR Value 470k
    SYMBOL pnp 576 32 M180
    SYMATTR InstName Q1
    SYMATTR Value 2N3906
    SYMBOL npn 864 -48 R0
    SYMATTR InstName Q3
    SYMATTR Value 2N2222
    SYMBOL res 624 -240 R0
    SYMATTR InstName R6
    SYMATTR Value 220k
    SYMBOL res 768 32 R0
    SYMATTR InstName R7
    SYMATTR Value 4700
    SYMBOL res 912 288 R0
    SYMATTR InstName R8
    SYMATTR Value 1000
    SYMBOL res 384 -160 R0
    SYMATTR InstName R4
    SYMATTR Value 470k
    SYMBOL cap 336 -32 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C4
    SYMATTR Value 100n
    TEXT 728 480 Left 2 !.tran 100m
    TEXT 400 432 Left 2 ;EPW SED OCT 2024
    TEXT 304 480 Left 2 ;VOLTAGE FOLLOWER RC OSC

    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From piglet@21:1/5 to Edward Rawde on Sat Oct 19 20:18:29 2024
    On 18/10/2024 6:47 pm, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>> time still seems to be slower than the fall time. It may be that the >>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due
    to too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in
    response to Bill to produce a sine wave no matter what I do with the
    control loop gain.
    It either grows to clipping or dies.

    That's the main purpose behind having a thermistor or filament bulb in the >> f/b path.

    Sure, but why use thermistors or filaments if you don't have to?
    Filaments don't last forever, particularly not if you drop your equipment, and filaments make me think of something like a 5U4.
    I forget when I last saw a filament. House lamps don't even have them now.

    I'm trying to make a low cost oscillator which produces the cleanest 1K Hz sinewave I can get, using only resistors, capacitors and
    semiconductors.

    There are plenty of examples online, but some of them don't seem to simulate. Whether that's because they do work in reality but not in simulation is hard to say.



    Filaments, NTC thermistors and LDRs are awkward I agree. Sadly even
    JFETs are less mainstream than before. Here is an illustration I made
    showing a BJT long tail pair current steering the collector current of a
    basic ladder RC phase shift osc. Q1 is the oscillator and Q2-Q3 divert
    current into the load resistance as AGC directs.


    Version 4
    SHEET 1 1480 680
    WIRE 352 -352 304 -352
    WIRE 560 -352 352 -352
    WIRE -608 -336 -608 -432
    WIRE -496 -336 -496 -432
    WIRE 304 -320 304 -352
    WIRE 928 -272 928 -320
    WIRE -128 -240 -128 -352
    WIRE 0 -192 -64 -192
    WIRE 112 -192 0 -192
    WIRE 304 -192 304 -240
    WIRE 304 -192 176 -192
    WIRE 928 -176 928 -208
    WIRE -608 -128 -608 -256
    WIRE -496 -128 -496 -256
    WIRE -352 -96 -368 -96
    WIRE -128 -96 -128 -144
    WIRE -128 -96 -352 -96
    WIRE 304 -96 304 -192
    WIRE 560 -96 560 -352
    WIRE 0 -80 0 -192
    WIRE 240 -48 144 -48
    WIRE 672 -48 624 -48
    WIRE 752 -48 672 -48
    WIRE 800 -48 752 -48
    WIRE 928 -48 928 -96
    WIRE 928 -48 864 -48
    WIRE -128 -32 -128 -96
    WIRE 672 -16 672 -48
    WIRE 752 -16 752 -48
    WIRE 144 0 144 -48
    WIRE 304 32 304 0
    WIRE 432 32 304 32
    WIRE 560 32 560 0
    WIRE 560 32 432 32
    WIRE 928 32 928 -48
    WIRE 0 64 0 0
    WIRE -608 112 -608 32
    WIRE -496 112 -496 32
    WIRE -128 112 -128 48
    WIRE -128 128 -128 112
    WIRE 144 128 144 80
    WIRE 432 160 432 32
    WIRE 672 160 672 64
    WIRE 752 160 752 48
    WIRE 928 160 928 96
    WIRE -368 208 -368 -96
    WIRE -256 208 -368 208
    WIRE -128 208 -176 208
    WIRE -80 208 -128 208
    WIRE 64 208 0 208
    WIRE 112 208 64 208
    WIRE 240 208 192 208
    WIRE 368 208 240 208
    WIRE -608 240 -608 192
    WIRE -496 240 -496 192
    WIRE -128 288 -128 208
    WIRE 64 288 64 208
    WIRE 240 288 240 208
    WIRE 432 304 432 256
    WIRE 528 304 432 304
    WIRE 528 320 528 304
    WIRE 432 336 432 304
    WIRE -128 368 -128 352
    WIRE 64 368 64 352
    WIRE 240 368 240 352
    WIRE 528 416 528 384
    WIRE 432 448 432 416
    WIRE 528 528 528 496
    FLAG -128 368 0
    FLAG 64 368 0
    FLAG 240 368 0
    FLAG 528 528 0
    FLAG -608 -128 0
    FLAG 144 128 0
    FLAG -608 240 0
    FLAG -608 -432 P10
    FLAG 352 -352 P10
    FLAG -608 32 N10
    FLAG 432 448 N10
    FLAG -128 112 N10
    FLAG -496 240 0
    FLAG -496 32 N5
    FLAG -496 -128 0
    FLAG -496 -432 P5
    FLAG 0 64 0
    FLAG 928 160 0
    FLAG 752 160 0
    FLAG -352 -96 OUT
    FLAG 928 -320 OUT
    FLAG -128 -352 P10
    FLAG 672 160 0
    SYMBOL voltage -608 -352 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value 10
    SYMBOL npn 368 160 R0
    SYMATTR InstName Q1
    SYMATTR Value 2N3904
    SYMBOL npn 240 -96 R0
    SYMATTR InstName Q2
    SYMATTR Value 2N3904
    SYMBOL npn 624 -96 M0
    SYMATTR InstName Q3
    SYMATTR Value 2N3904
    SYMBOL res 288 -336 R0
    SYMATTR InstName R6
    SYMATTR Value 22k
    SYMBOL res 416 320 R0
    SYMATTR InstName R4
    SYMATTR Value 22k
    SYMBOL res 208 192 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 47k
    SYMBOL res 16 192 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R2
    SYMATTR Value 47k
    SYMBOL res -160 192 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 47k
    SYMBOL cap -144 288 R0
    SYMATTR InstName C1
    SYMATTR Value 10n
    SYMBOL cap 48 288 R0
    SYMATTR InstName C2
    SYMATTR Value 10n
    SYMBOL cap 224 288 R0
    SYMATTR InstName C3
    SYMATTR Value 10n
    SYMBOL cap 512 320 R0
    SYMATTR InstName C4
    SYMATTR Value 0.01m
    SYMBOL npn -64 -240 M0
    SYMATTR InstName Q4
    SYMATTR Value 2N3904
    SYMBOL res -112 -48 M0
    SYMATTR InstName R10
    SYMATTR Value 3300
    SYMBOL cap 912 -272 R0
    SYMATTR InstName C6
    SYMATTR Value 100n
    SYMBOL res 512 400 R0
    SYMATTR InstName R5
    SYMATTR Value 100
    SYMBOL voltage 144 -16 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V5
    SYMATTR Value 1
    SYMBOL voltage -608 96 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V3
    SYMATTR Value -10
    SYMBOL res 912 -192 R0
    SYMATTR InstName R8
    SYMATTR Value 100k
    SYMBOL res -16 -96 R0
    SYMATTR InstName R9
    SYMATTR Value 100k
    SYMBOL cap 112 -176 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName C7
    SYMATTR Value 1000n
    SYMBOL voltage -496 96 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V4
    SYMATTR Value -5
    SYMBOL voltage -496 -352 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V2
    SYMATTR Value 5
    SYMBOL diode 864 -64 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D1
    SYMATTR Value 1N914
    SYMBOL diode 944 96 R180
    WINDOW 0 24 64 Left 2
    WINDOW 3 24 0 Left 2
    SYMATTR InstName D2
    SYMATTR Value 1N914
    SYMBOL cap 736 -16 R0
    SYMATTR InstName C5
    SYMATTR Value 1000n
    SYMBOL res 656 -32 R0
    SYMATTR InstName R7
    SYMATTR Value 470k
    TEXT -624 472 Left 2 !.tran 3000m startup
    TEXT 920 480 Left 2 ;EPW SED OCT 2024
    TEXT 664 536 Left 2 ;CURRENT STEER AGC ON LADDER RC OSC

    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to All on Sat Oct 19 13:15:10 2024
    On Sat, 19 Oct 2024 20:13:12 +0100, piglet <erichpwagner@hotmail.com>
    wrote:

    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>> time still seems to be slower than the fall time. It may be that the >>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due to >>>> too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize
    amplitude.



    Here is an amusing oscillator that has a voltage follower as the active
    stage - it has no voltage gain so some people say it cannot work - they
    are wrong of course.

    This is a sort-of-Colpitts (not quite) oscillator that uses a BUF602
    unity-gain buffer amp. Phase noise is pretty good.

    https://www.dropbox.com/scl/fi/ffeer8ocqwyaeobh49zh7/BUF602_LC_Osc.jpg?rlkey=xl6pt8sjz7y6hhgynnloj1f36&raw=1

    The BUF part is much better than any discrete transistor would be.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From KevinJ93@21:1/5 to piglet on Sat Oct 19 12:46:35 2024
    On 10/19/24 12:13 PM, piglet wrote:
    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>> time still seems to be slower than the fall time. It may be that the >>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply
    due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in
    response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize
    amplitude.



    Here is an amusing oscillator that has a voltage follower as the active
    stage - it has no voltage gain so some people say it cannot work - they
    are wrong of course.

    <...>
    piglet


    If you move the ground to the emitter of Q3 and slide R8 through the
    power supply to the collector of Q3 you can see that it is a
    conventional phase shift oscillator with feedback from the output of an inverting amplifier via a 3-stage RC network.

    kw

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From piglet@21:1/5 to kevin_es@whitedigs.com on Sat Oct 19 19:57:43 2024
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/19/24 12:13 PM, piglet wrote:
    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>>> time still seems to be slower than the fall time. It may be that the >>>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply
    due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in
    response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize
    amplitude.



    Here is an amusing oscillator that has a voltage follower as the active
    stage - it has no voltage gain so some people say it cannot work - they
    are wrong of course.

    <...>
    piglet


    If you move the ground to the emitter of Q3 and slide R8 through the
    power supply to the collector of Q3 you can see that it is a
    conventional phase shift oscillator with feedback from the output of an inverting amplifier via a 3-stage RC network.

    kw



    What do you do with the cold end of C1 in that scenario?


    --
    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to All on Sat Oct 19 17:35:01 2024
    On Sat, 19 Oct 2024 20:13:12 +0100, piglet <erichpwagner@hotmail.com>
    wrote:

    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>> time still seems to be slower than the fall time. It may be that the >>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply due to >>>> too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize
    amplitude.



    Here is an amusing oscillator that has a voltage follower as the active
    stage - it has no voltage gain so some people say it cannot work - they
    are wrong of course.

    Yes. The old Touch-Tone keypads had just such an oscillator, with
    voltage gain due to a multi-tapped coil in a ferrite pot core. The
    circuit and analysis was in an article published in the BSTJ.

    Joe Gwinn

    Amplitude grows to power rail limits and non-linearities creep in.


    Version 4
    SHEET 1 1132 680
    WIRE 640 -272 400 -272
    WIRE 784 -272 640 -272
    WIRE 928 -272 784 -272
    WIRE 1072 -272 928 -272
    WIRE 640 -224 640 -272
    WIRE 400 -144 400 -272
    WIRE 784 -144 784 -272
    WIRE 640 -96 640 -144
    WIRE 720 -96 640 -96
    WIRE 640 -64 640 -96
    WIRE 928 -48 928 -272
    WIRE 1072 -48 1072 -272
    WIRE 272 -16 64 -16
    WIRE 400 -16 400 -64
    WIRE 400 -16 336 -16
    WIRE 432 -16 400 -16
    WIRE 576 -16 432 -16
    WIRE 784 0 784 -48
    WIRE 864 0 784 0
    WIRE 432 32 432 -16
    WIRE 784 48 784 0
    WIRE 64 96 64 -16
    WIRE 160 96 64 96
    WIRE 304 96 240 96
    WIRE 1072 112 1072 32
    WIRE 64 128 64 96
    WIRE 432 160 432 112
    WIRE 784 176 784 128
    WIRE 64 224 64 192
    WIRE 160 224 64 224
    WIRE 304 224 304 96
    WIRE 304 224 240 224
    WIRE 640 224 640 32
    WIRE 880 224 640 224
    WIRE 928 224 928 48
    WIRE 928 224 880 224
    WIRE 64 256 64 224
    WIRE 928 304 928 224
    WIRE 64 352 64 320
    WIRE 160 352 64 352
    WIRE 304 352 304 224
    WIRE 304 352 240 352
    WIRE 640 352 640 224
    WIRE 640 352 304 352
    WIRE 64 384 64 352
    WIRE 928 464 928 384
    WIRE 64 480 64 448
    FLAG 432 160 0
    FLAG 928 464 0
    FLAG 64 480 0
    FLAG 1072 112 0
    FLAG 784 176 0
    FLAG 880 224 OUT
    SYMBOL res 256 368 M270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R1
    SYMATTR Value 470
    SYMBOL res 256 240 M270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R2
    SYMATTR Value 4700
    SYMBOL res 256 112 M270
    WINDOW 0 32 56 VTop 2
    WINDOW 3 0 56 VBottom 2
    SYMATTR InstName R3
    SYMATTR Value 47k
    SYMBOL cap 80 384 M0
    SYMATTR InstName C1
    SYMATTR Value 100n
    SYMBOL cap 80 128 M0
    SYMATTR InstName C3
    SYMATTR Value 1n
    SYMBOL cap 80 256 M0
    SYMATTR InstName C2
    SYMATTR Value 10n
    SYMBOL npn 720 -144 R0
    SYMATTR InstName Q2
    SYMATTR Value 2N2222
    SYMBOL voltage 1072 -64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value 20
    SYMBOL res 416 16 R0
    SYMATTR InstName R5
    SYMATTR Value 470k
    SYMBOL pnp 576 32 M180
    SYMATTR InstName Q1
    SYMATTR Value 2N3906
    SYMBOL npn 864 -48 R0
    SYMATTR InstName Q3
    SYMATTR Value 2N2222
    SYMBOL res 624 -240 R0
    SYMATTR InstName R6
    SYMATTR Value 220k
    SYMBOL res 768 32 R0
    SYMATTR InstName R7
    SYMATTR Value 4700
    SYMBOL res 912 288 R0
    SYMATTR InstName R8
    SYMATTR Value 1000
    SYMBOL res 384 -160 R0
    SYMATTR InstName R4
    SYMATTR Value 470k
    SYMBOL cap 336 -32 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C4
    SYMATTR Value 100n
    TEXT 728 480 Left 2 !.tran 100m
    TEXT 400 432 Left 2 ;EPW SED OCT 2024
    TEXT 304 480 Left 2 ;VOLTAGE FOLLOWER RC OSC

    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From KevinJ93@21:1/5 to All on Sat Oct 19 14:57:58 2024
    On 10/19/24 12:46 PM, KevinJ93 wrote:
    On 10/19/24 12:13 PM, piglet wrote:
    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>>> time still seems to be slower than the fall time. It may be that the >>>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply
    due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted
    in response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize
    amplitude.



    Here is an amusing oscillator that has a voltage follower as the
    active stage - it has no voltage gain so some people say it cannot
    work - they are wrong of course.

    <...>
    piglet


    If you move the ground to the emitter of Q3 and slide R8 through the
    power supply to the collector of Q3 you can see that it is a
    conventional phase shift oscillator with feedback from the output of an inverting amplifier via a 3-stage RC network.

    kw


    Somehow it was truncated?

    This is what it was supposed to be:

    If you move the ground to the emitter of Q3 and slide R8 through the
    power supply to the collector of Q3 you can see that it is a
    conventional phase shift oscillator with feedback through a three
    section RC network.

    kw

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From KevinJ93@21:1/5 to piglet on Sat Oct 19 15:02:39 2024
    On 10/19/24 12:57 PM, piglet wrote:
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/19/24 12:13 PM, piglet wrote:
    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>>>> time still seems to be slower than the fall time. It may be that the >>>>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the
    amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply
    due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in >>>>> response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize
    amplitude.



    Here is an amusing oscillator that has a voltage follower as the active
    stage - it has no voltage gain so some people say it cannot work - they
    are wrong of course.

    <...>
    piglet


    If you move the ground to the emitter of Q3 and slide R8 through the
    power supply to the collector of Q3 you can see that it is a
    conventional phase shift oscillator with feedback from the output of an
    inverting amplifier via a 3-stage RC network.

    kw



    What do you do with the cold end of C1 in that scenario?



    That connects to the collector, as it is now and forms the first section
    of the RC network. (voltage sources are zero impedance from the point of
    view of AC). C4 is a coupling capacitor - its value and the high
    impedance of R4,R5 and Q1 mean it has little effect on the phase shift.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Sun Oct 20 15:27:59 2024
    On 20/10/2024 3:36 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message
    news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote: >>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>
    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able
    though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here. >>>>>>>
    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the >>>>>> top of the wave. In that region the dynamic resistance of the FET
    is very large, and therefore the gain of the opamp drops to about
    one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so
    great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is
    really hard to beat.

    Ok thanks Jeroen.

    It looks like the best approach for the gain control is either a filament or something like that used in the document Bill
    Sloman
    posted.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    Note that the LDR has a very small influence range on the loop gain.


    That's why I added R3 in this circuit.
    It does not seem to be safe to reduce R3 below 1k.

    R4 helps a lot too for reasons I don't fully understand.
    It may be moving the FET to a better part of its operating characteristics. >>>
    A single rail version also works with another op amp producing 6V for R4 and two 20k resistors for R2 between 12V and 0V.
    As expected, this produces twice the output voltage and I've not found a way to reduce it.

    This will probably be my final offering for a 1KHz sinewave oscillator unless anyone can suggest improvements without using light
    dependent resistors.
    From the LTSpice plot, I can't discern any impurity in the signal this circuit produces.
    It would be interesting to see what a real circuit and a spectrum analyzer says but I probably won't be building it.

    I haven't used an LDR since playing with an ORP12 around age 10.
    I seem to remember that they can degrade over time but maybe that only happens in sunlight.

    I got your earlier circuit to work a lot better simply by increasing R7 to 5.6k. If you use the View option on the trace viewing
    panel to pull out an FFT of the output (I use Blackmann-Harris windowing) from 10sec to 20 sec, you can see that second harmonic
    distortion is about 20dB below the primary - not great but better than it was.

    And the waveform looks like a sine wave.

    The less influence the FET has on the gain of the circuit, the better the sine wave.

    If you run this circuit then View, FFT, Use current zoom extent, Ok
    It implies that unwanted harmonics are 40dB down.
    I'm not sure I believe that but if true then it's not bad for a very low cost circuit.

    <snipped .asc file>

    The revised .asc file is a bit of a mess. You've added R11 to get the
    output frequency close to 1KHz.

    What you should have done is to have used 0.1% 10.5k resistors -it's an
    E96 value and you can buy them off the shelf - at R1 and R2.

    That got me to 1.001kHz.

    Since the capacitors at C1 and C2 can at best only be +/-1% tolerance
    parts - you can't buy anything better off the shelf - this is quite
    close enough.

    You can use a trimming potentiometer to get closer to the target
    frequency, but that does have its downsides.

    R4 certainly does make the circuit settle faster - how is a bit of a
    mystery - but you've created a total mess with R5,R7, R8, and R10. It's
    not clear what you were trying to do.

    I found that I could get by without R4 provided that I stuck with
    sensible resistance values at R7 and R8 - R7 went up to 6.2k and I put
    330R across J1.

    The cheapest plastic +/-1% film capacitors I could buy from Element-14
    in Australia cost $A1.53 each so it isn't a particularly low cost circuit.

    --
    Bill Sloman. Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Edward Rawde on Sun Oct 20 01:45:25 2024
    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vf2569$2f0q$1@nnrp.usenet.blueworldhosting.com...
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf20si$96u8$1@dont-email.me...
    On 20/10/2024 3:36 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>> news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote: >>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>

    Actually, having just looked at the time domain waveform, I'd say that's no good at all.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Edward Rawde on Sun Oct 20 01:52:09 2024
    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vf2569$2f0q$1@nnrp.usenet.blueworldhosting.com...
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf20si$96u8$1@dont-email.me...
    On 20/10/2024 3:36 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>> news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote: >>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>>

    Change R5 to 56k. Now that looks reasonable but only 35dB down at 2KHz.
    Maybe I'll notch that out.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Sun Oct 20 01:41:28 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf20si$96u8$1@dont-email.me...
    On 20/10/2024 3:36 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>> news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote: >>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote: >>>>>>>>>>>>>>>>>>
    ...

    Without doubt, it's the trickiest aspect of the design. Definitely do-able
    though. Let us know how you get on.


    Ok. This simple circuit is based on the circuit you can find here. >>>>>>>>
    https://electronics.stackexchange.com/questions/697687/how-to-control-the-amplitude-of-a-wien-bridge-oscillator

    It produces a something wave.
    I wouldn't call it sine but at least it's not clipping.
    What's going on here?

    Version 4
    [Snip...]

    You're hitting the flat portion of the Id vs. Vds curve around the >>>>>>> top of the wave. In that region the dynamic resistance of the FET >>>>>>> is very large, and therefore the gain of the opamp drops to about >>>>>>> one. As a result, the positive tip of the output gets sort-of
    squashed.

    There are probably ways to fix this, for example by feeding a
    portion of the output signal to the FET gate, but a quick
    attempt I made didn't work very well. This is why FETs aren't so >>>>>>> great as gain setting elements.

    Using a lightbulb --or more generally a PTC resistor-- for R7 is >>>>>>> really hard to beat.

    Ok thanks Jeroen.

    It looks like the best approach for the gain control is either a filament or something like that used in the document Bill
    Sloman
    posted.

    https://www.analog.com/media/en/technical-documentation/application-notes/AN132f.pdf

    Note that the LDR has a very small influence range on the loop gain. >>>>>

    That's why I added R3 in this circuit.
    It does not seem to be safe to reduce R3 below 1k.

    R4 helps a lot too for reasons I don't fully understand.
    It may be moving the FET to a better part of its operating characteristics.

    A single rail version also works with another op amp producing 6V for R4 and two 20k resistors for R2 between 12V and 0V.
    As expected, this produces twice the output voltage and I've not found a way to reduce it.

    This will probably be my final offering for a 1KHz sinewave oscillator unless anyone can suggest improvements without using
    light
    dependent resistors.
    From the LTSpice plot, I can't discern any impurity in the signal this circuit produces.
    It would be interesting to see what a real circuit and a spectrum analyzer says but I probably won't be building it.

    I haven't used an LDR since playing with an ORP12 around age 10.
    I seem to remember that they can degrade over time but maybe that only happens in sunlight.

    I got your earlier circuit to work a lot better simply by increasing R7 to 5.6k. If you use the View option on the trace viewing
    panel to pull out an FFT of the output (I use Blackmann-Harris windowing) from 10sec to 20 sec, you can see that second harmonic
    distortion is about 20dB below the primary - not great but better than it was.

    And the waveform looks like a sine wave.

    The less influence the FET has on the gain of the circuit, the better the sine wave.

    If you run this circuit then View, FFT, Use current zoom extent, Ok
    It implies that unwanted harmonics are 40dB down.
    I'm not sure I believe that but if true then it's not bad for a very low cost circuit.

    <snipped .asc file>

    The revised .asc file is a bit of a mess. You've added R11 to get the output frequency close to 1KHz.

    What you should have done is to have used 0.1% 10.5k resistors -it's an E96 value and you can buy them off the shelf - at R1 and
    R2.

    That would be fine in reality but so far this is only simulation.


    That got me to 1.001kHz.

    Since the capacitors at C1 and C2 can at best only be +/-1% tolerance parts - you can't buy anything better off the shelf - this
    is quite close enough.

    You can use a trimming potentiometer to get closer to the target frequency, but that does have its downsides.

    R4 certainly does make the circuit settle faster - how is a bit of a mystery

    So I'd leave it in.

    but you've created a total mess with R5,R7, R8, and R10. It's not clear what you were trying to do.

    R10 was experimental like R4 and has been removed.


    I found that I could get by without R4 provided that I stuck with sensible resistance values at R7 and R8 - R7 went up to 6.2k and
    I put 330R across J1.


    If I wanted to build this for experimental purposes I'd have R4 150 ten turn and R5 100k ten turn.
    I'd also do it through hole.

    If I were you I wouldn't get too excited over what, so far, is only a simulation.
    It could be bad for your blood pressure.
    I think reality would be a very different matter if the circuit were built for real but I don't have a suitable spectrum analyzer so
    there isn't much point doing that.

    Is this better?
    I still can't do better than 40dB for unwanted harmonics no matter what I do. Except perhaps filter the output. Maybe a notch at 2KHz.

    Version 4
    SHEET 1 2196 916
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    FLAG -592 336 0
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    WINDOW 0 12 7 Left 2
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    SYMATTR Value 100µ
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    TEXT -496 352 Left 2 !.tran 0 2 1 startup
    TEXT -536 -392 Left 2 ;Edward Rawde's 1KHz sinewave oscillator. 20 Oct 2024.\nCan the sine purity be improved any further?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From piglet@21:1/5 to kevin_es@whitedigs.com on Sun Oct 20 09:55:46 2024
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/19/24 12:57 PM, piglet wrote:
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/19/24 12:13 PM, piglet wrote:
    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>>>>> time still seems to be slower than the fall time. It may be that the >>>>>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the >>>>>>> amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply >>>>>>> due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in >>>>>> response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize
    amplitude.



    Here is an amusing oscillator that has a voltage follower as the active >>>> stage - it has no voltage gain so some people say it cannot work - they >>>> are wrong of course.

    <...>
    piglet


    If you move the ground to the emitter of Q3 and slide R8 through the
    power supply to the collector of Q3 you can see that it is a
    conventional phase shift oscillator with feedback from the output of an
    inverting amplifier via a 3-stage RC network.

    kw



    What do you do with the cold end of C1 in that scenario?



    That connects to the collector, as it is now and forms the first section
    of the RC network. (voltage sources are zero impedance from the point of
    view of AC). C4 is a coupling capacitor - its value and the high
    impedance of R4,R5 and Q1 mean it has little effect on the phase shift.


    It still works if I replace the transistors with an op amp non inverting follower - no inversion in sight. How would you re-describe that?

    --
    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From KevinJ93@21:1/5 to piglet on Sun Oct 20 15:01:50 2024
    On 10/20/24 2:55 AM, piglet wrote:
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/19/24 12:57 PM, piglet wrote:
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/19/24 12:13 PM, piglet wrote:
    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise >>>>>>>>> time still seems to be slower than the fall time. It may be that the >>>>>>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the >>>>>>>> amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply >>>>>>>> due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in >>>>>>> response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize >>>>>> amplitude.



    Here is an amusing oscillator that has a voltage follower as the active >>>>> stage - it has no voltage gain so some people say it cannot work - they >>>>> are wrong of course.

    <...>
    piglet


    If you move the ground to the emitter of Q3 and slide R8 through the
    power supply to the collector of Q3 you can see that it is a
    conventional phase shift oscillator with feedback from the output of an >>>> inverting amplifier via a 3-stage RC network.

    kw



    What do you do with the cold end of C1 in that scenario?



    That connects to the collector, as it is now and forms the first section
    of the RC network. (voltage sources are zero impedance from the point of
    view of AC). C4 is a coupling capacitor - its value and the high
    impedance of R4,R5 and Q1 mean it has little effect on the phase shift.


    It still works if I replace the transistors with an op amp non inverting follower - no inversion in sight. How would you re-describe that?


    Exactly the same argument applies - any current coming out of the opamp
    must come from the power supplies and so goes through R8. The gain to
    the PS pin can be much more than unity.

    Some circuit designs exploit this feature - I think I have seen John
    Larkin describing one. There are also designs in The Art of Electronics
    using it.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From piglet@21:1/5 to kevin_es@whitedigs.com on Sun Oct 20 22:08:47 2024
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/20/24 2:55 AM, piglet wrote:
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/19/24 12:57 PM, piglet wrote:
    KevinJ93 <kevin_es@whitedigs.com> wrote:
    On 10/19/24 12:13 PM, piglet wrote:
    On 18/10/2024 4:46 pm, john larkin wrote:
    On Fri, 18 Oct 2024 11:25:19 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "piglet" <erichpwagner@hotmail.com> wrote in message
    news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    The circuit below produces a reasonable looking sinewave but the rise
    time still seems to be slower than the fall time. It may be that the >>>>>>>>>> amplifier in use is not ideal for this.


    Could that just be second harmonic distortion? You could test the >>>>>>>>> amplifier
    by uncoupling the Wien network and injecting test inputs.

    Elsewhere I think your amplitude control problems could be simply >>>>>>>>> due to
    too much gain.

    Perhaps, but I've not so far been able to get the circuit I posted in >>>>>>>> response to Bill to produce a sine wave no matter what I do
    with the control loop gain.
    It either grows to clipping or dies.



    --
    piglet


    I do a lot of instant-start LC oscillators as the timebase of
    triggered delay generators. I let them clip just a bit to stabilize >>>>>>> amplitude.



    Here is an amusing oscillator that has a voltage follower as the active >>>>>> stage - it has no voltage gain so some people say it cannot work - they >>>>>> are wrong of course.

    <...>
    piglet


    If you move the ground to the emitter of Q3 and slide R8 through the >>>>> power supply to the collector of Q3 you can see that it is a
    conventional phase shift oscillator with feedback from the output of an >>>>> inverting amplifier via a 3-stage RC network.

    kw



    What do you do with the cold end of C1 in that scenario?



    That connects to the collector, as it is now and forms the first section >>> of the RC network. (voltage sources are zero impedance from the point of >>> view of AC). C4 is a coupling capacitor - its value and the high
    impedance of R4,R5 and Q1 mean it has little effect on the phase shift.


    It still works if I replace the transistors with an op amp non inverting
    follower - no inversion in sight. How would you re-describe that?


    Exactly the same argument applies - any current coming out of the opamp
    must come from the power supplies and so goes through R8. The gain to
    the PS pin can be much more than unity.

    Some circuit designs exploit this feature - I think I have seen John
    Larkin describing one. There are also designs in The Art of Electronics
    using it.




    Bingo! Yes that’s it


    --
    piglet

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to Edward Rawde on Mon Oct 21 22:24:04 2024
    On 20/10/2024 4:52 pm, Edward Rawde wrote:
    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vf2569$2f0q$1@nnrp.usenet.blueworldhosting.com...
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf20si$96u8$1@dont-email.me...
    On 20/10/2024 3:36 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote:

    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>> news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote: >>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    <snip>

    This will probably mess up the thread structure, but here's another
    variation. It struck me that the current spike being pulled from the amp through D1 is probably messing up the op amp's output stage, so I
    decided to buffer the op amp output with a PNP to minimise this.

    The 4th harmonic is now almost 50dB below the fundamental.

    You could probably do even better with a more elaborate circuit that
    kept the output frequency away from the gate of the FET. My more
    ambitious simulation put in a precision rectifier to get a DC output
    that I could compare with a voltage reference with an integrator, whose
    output was low pass filtered before it went into the AD734 to adjust the
    gain.

    A pure integrator would introduce too much phase shift to allow a stable control loop, so there was a resistor in series with the integrating
    capacitor to give you a sensible settling time for the loop.

    That wasn't any kind of low cost approach.

    Version 4
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    SYMATTR Value 15n
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    SYMATTR Value 15n
    SYMBOL polcap -368 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100l
    SYMBOL OpAmps\\LT1057 128 64 R0
    SYMATTR InstName U2
    SYMBOL res -160 -208 R0
    SYMATTR InstName R6
    SYMATTR Value 47k
    SYMBOL res 208 -128 R90
    WINDOW 0 -21 6 VBottom 2
    WINDOW 3 18 3 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 368 -128 R90
    WINDOW 0 -17 16 VBottom 2
    WINDOW 3 15 7 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL diode 48 -240 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL res 320 -368 R180
    WINDOW 0 15 28 Left 2
    WINDOW 3 15 -8 Left 2
    SYMATTR InstName R9
    SYMATTR Value 4.7k
    SYMBOL njf 48 -176 R90
    WINDOW 0 -38 17 VRight 2
    WINDOW 3 -7 -47 VRight 2
    SYMATTR InstName J1
    SYMATTR Value 2N3819
    SYMBOL voltage -480 448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 383 -483 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL polcap -352 496 R0
    SYMATTR InstName C5
    SYMATTR Value 100l
    SYMBOL res -80 272 R0
    SYMATTR InstName R2
    SYMATTR Value 10.5k
    SYMBOL polcap -240 -160 R180
    WINDOW 0 24 57 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C3
    SYMATTR Value 10µ
    SYMBOL res 16 -64 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 330
    SYMBOL FerriteBead 192 -256 R90
    WINDOW 0 -16 0 VBottom 2
    SYMATTR InstName L1
    SYMATTR Value 14µ
    SYMATTR SpiceLine Ipk=3 Rser=0.0122 Rpar=870 Cpar=1000f
    SYMBOL FerriteBead 272 -256 R90
    WINDOW 0 -16 0 VBottom 2
    SYMATTR InstName L2
    SYMATTR Value 14µ
    SYMATTR SpiceLine Ipk=3 Rser=0.0122 Rpar=870 Cpar=1000f
    SYMBOL pnp 528 -384 R180
    SYMATTR InstName Q1
    SYMATTR Value 2N2907
    SYMBOL res 464 -544 R0
    SYMATTR InstName R4
    SYMATTR Value 4.7k
    TEXT -184 472 Left 2 !.tran 0 20s 0s startup

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Mon Oct 21 14:11:22 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf5dkk$tubm$1@dont-email.me...
    On 20/10/2024 4:52 pm, Edward Rawde wrote:
    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vf2569$2f0q$1@nnrp.usenet.blueworldhosting.com...
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf20si$96u8$1@dont-email.me...
    On 20/10/2024 3:36 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote: >>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>> news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    <snip>

    This will probably mess up the thread structure, but here's another variation. It struck me that the current spike being pulled
    from the amp through D1 is probably messing up the op amp's output stage, so I decided to buffer the op amp output with a PNP to
    minimise this.

    The 4th harmonic is now almost 50dB below the fundamental.


    Yes that works well, thanks for taking the time to produce it.

    There were issues with resistors being out of position for unknown reasons but easy to correct.

    My next question is why does this circuit, which is based on yours, show unwanted amplitude modulation at the top of the time domain
    trace but only to a very small extent underneath.

    Changing the diode to a BAT54 improves it.

    Version 4
    SHEET 1 2196 916
    WIRE -352 -608 -480 -608
    WIRE 128 -608 -352 -608
    WIRE 464 -608 128 -608
    WIRE 464 -576 464 -608
    WIRE 464 -480 464 -496
    WIRE 464 -480 320 -480
    WIRE 320 -416 320 -480
    WIRE -160 -256 -256 -256
    WIRE -80 -256 -160 -256
    WIRE -16 -256 -80 -256
    WIRE 48 -256 -16 -256
    WIRE 160 -256 112 -256
    WIRE 240 -256 224 -256
    WIRE 320 -256 320 -336
    WIRE 320 -256 304 -256
    WIRE -160 -240 -160 -256
    WIRE -256 -224 -256 -256
    WIRE -16 -176 -16 -256
    WIRE -256 -128 -256 -160
    WIRE -160 -128 -160 -160
    WIRE -160 -128 -256 -128
    WIRE -80 -128 -160 -128
    WIRE -48 -128 -80 -128
    WIRE 80 -128 48 -128
    WIRE 160 -128 80 -128
    WIRE 256 -128 240 -128
    WIRE 320 -128 256 -128
    WIRE 448 -128 400 -128
    WIRE -256 -64 -256 -128
    WIRE -80 -64 -80 -128
    WIRE -32 -64 -80 -64
    WIRE 64 -64 48 -64
    WIRE 80 -64 80 -128
    WIRE 80 -64 64 -64
    WIRE 256 -16 256 -128
    WIRE 304 -16 256 -16
    WIRE 448 -16 448 -128
    WIRE 448 -16 384 -16
    WIRE 256 64 256 -16
    WIRE 256 64 48 64
    WIRE -480 80 -480 -608
    WIRE 128 96 128 -608
    WIRE -352 112 -352 -608
    WIRE 48 112 48 64
    WIRE 96 112 48 112
    WIRE 432 128 160 128
    WIRE 448 128 448 -16
    WIRE 448 128 432 128
    WIRE 528 128 528 -432
    WIRE 528 128 448 128
    WIRE 608 128 528 128
    WIRE 656 128 608 128
    WIRE 96 144 -80 144
    WIRE -80 224 -80 144
    WIRE 16 224 -80 224
    WIRE 224 224 16 224
    WIRE 304 224 288 224
    WIRE 432 224 432 128
    WIRE 432 224 384 224
    WIRE -80 240 -80 224
    WIRE 16 240 16 224
    WIRE -480 320 -480 160
    WIRE -480 320 -560 320
    WIRE -560 336 -560 320
    WIRE -480 336 -480 320
    WIRE -352 336 -352 176
    WIRE -352 336 -480 336
    WIRE -336 336 -352 336
    WIRE -256 336 -256 16
    WIRE -256 336 -336 336
    WIRE -80 336 -80 320
    WIRE -80 336 -256 336
    WIRE 16 336 16 304
    WIRE 16 336 -80 336
    WIRE -480 464 -480 336
    WIRE -336 496 -336 336
    WIRE -480 656 -480 544
    WIRE -336 656 -336 560
    WIRE -336 656 -480 656
    WIRE 128 656 128 160
    WIRE 128 656 -336 656
    WIRE 464 656 464 -384
    WIRE 464 656 128 656
    FLAG -560 336 0
    FLAG -80 -256 FET_gate
    FLAG 64 -64 TP
    FLAG 608 128 output
    SYMBOL voltage -480 64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 400 208 R90
    WINDOW 0 -20 5 VBottom 2
    WINDOW 3 21 -5 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 10.5k
    SYMBOL cap 288 208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 15n
    SYMBOL cap 32 304 R180
    WINDOW 0 -33 54 Left 2
    WINDOW 3 -49 18 Left 2
    SYMATTR InstName C2
    SYMATTR Value 15n
    SYMBOL polcap -368 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100l
    SYMBOL OpAmps\\LT1057 128 64 R0
    SYMATTR InstName U2
    SYMBOL res -176 -256 R0
    SYMATTR InstName R6
    SYMATTR Value 47k
    SYMBOL res 256 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 416 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL diode 48 -240 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D1
    SYMATTR Value 1N4148
    SYMBOL res 336 -320 R180
    WINDOW 0 15 28 Left 2
    WINDOW 3 15 -8 Left 2
    SYMATTR InstName R9
    SYMATTR Value 4.7k
    SYMBOL njf 48 -176 R90
    WINDOW 0 -38 17 VRight 2
    WINDOW 3 -9 -11 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -480 448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 383 -483 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL polcap -352 496 R0
    SYMATTR InstName C5
    SYMATTR Value 100l
    SYMBOL res -96 224 R0
    SYMATTR InstName R2
    SYMATTR Value 10.5k
    SYMBOL cap -240 -160 R180
    WINDOW 0 24 57 Left 2
    WINDOW 3 24 8 Left 2
    SYMATTR InstName C3
    SYMATTR Value 10µ
    SYMATTR Description Polarized Capacitor
    SYMATTR Type polcap
    SYMATTR SpiceLine V=4 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60G106ME15" type="X5R"
    SYMBOL res 64 -80 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 330
    SYMBOL FerriteBead 192 -256 R90
    WINDOW 0 -16 0 VBottom 2
    SYMATTR InstName L1
    SYMATTR Value 14µ
    SYMATTR SpiceLine Ipk=3 Rser=0.0122 Rpar=870 Cpar=1000f
    SYMBOL FerriteBead 272 -256 R90
    WINDOW 0 -16 0 VBottom 2
    SYMATTR InstName L2
    SYMATTR Value 14µ
    SYMATTR SpiceLine Ipk=3 Rser=0.0122 Rpar=870 Cpar=1000f
    SYMBOL pnp 528 -384 R180
    SYMATTR InstName Q1
    SYMATTR Value 2N2907
    SYMBOL res 448 -592 R0
    SYMATTR InstName R5
    SYMATTR Value 4.7k
    SYMBOL res 400 -32 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R10
    SYMATTR Value 820k
    SYMBOL res -272 -80 R0
    SYMATTR InstName R4
    SYMATTR Value 15
    TEXT -184 472 Left 2 !.tran 0 20s 0s startup

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Mon Oct 21 15:50:04 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf5dkk$tubm$1@dont-email.me...
    On 20/10/2024 4:52 pm, Edward Rawde wrote:
    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vf2569$2f0q$1@nnrp.usenet.blueworldhosting.com...
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf20si$96u8$1@dont-email.me...
    On 20/10/2024 3:36 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote: >>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>> news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    <snip>

    This will probably mess up the thread structure, but here's another variation. It struck me that the current spike being pulled
    from the amp through D1 is probably messing up the op amp's output stage, so I decided to buffer the op amp output with a PNP to
    minimise this.

    The 4th harmonic is now almost 50dB below the fundamental.

    If the problem is asymmetry in the drive from the amplifier then why not symmetricalize it like this.

    An FFT from 6s to 20s shows reasonably clean performance at 1kHz and a simple filter should be able to get more than 50dB down at
    other harmonics.

    R9 at 100 ohms is even better.

    Manual adjustment of R5 will be needed in any real circuit.

    I'd probably make R10 10 ohm variable, R9 1k variable and R5 100k variable and then use the extremely scientific process of
    adjusting all three for best performance.

    I may not be able to reply further for a few days after today.

    Version 4
    SHEET 1 2196 916
    WIRE -352 -608 -480 -608
    WIRE 128 -608 -352 -608
    WIRE -160 -496 -256 -496
    WIRE 48 -496 -160 -496
    WIRE 496 -496 112 -496
    WIRE -160 -480 -160 -496
    WIRE -256 -464 -256 -496
    WIRE -256 -368 -256 -400
    WIRE -160 -368 -160 -400
    WIRE -160 -368 -256 -368
    WIRE -256 -320 -256 -368
    WIRE -256 -320 -304 -320
    WIRE -160 -256 -256 -256
    WIRE -16 -256 -160 -256
    WIRE 48 -256 -16 -256
    WIRE 496 -256 496 -496
    WIRE 496 -256 112 -256
    WIRE -160 -240 -160 -256
    WIRE -256 -224 -256 -256
    WIRE -16 -176 -16 -256
    WIRE -304 -128 -304 -320
    WIRE -256 -128 -256 -160
    WIRE -256 -128 -304 -128
    WIRE -160 -128 -160 -160
    WIRE -160 -128 -256 -128
    WIRE -80 -128 -160 -128
    WIRE -48 -128 -80 -128
    WIRE 80 -128 48 -128
    WIRE 160 -128 80 -128
    WIRE 256 -128 240 -128
    WIRE 320 -128 256 -128
    WIRE 448 -128 400 -128
    WIRE -304 -80 -304 -128
    WIRE 496 -80 496 -256
    WIRE -80 -64 -80 -128
    WIRE -32 -64 -80 -64
    WIRE 64 -64 48 -64
    WIRE 80 -64 80 -128
    WIRE 80 -64 64 -64
    WIRE 256 -16 256 -128
    WIRE 304 -16 256 -16
    WIRE 448 -16 448 -128
    WIRE 448 -16 384 -16
    WIRE -304 32 -304 0
    WIRE 256 64 256 -16
    WIRE 256 64 48 64
    WIRE -480 80 -480 -608
    WIRE 128 96 128 -608
    WIRE -352 112 -352 -608
    WIRE 48 112 48 64
    WIRE 96 112 48 112
    WIRE 432 128 160 128
    WIRE 448 128 448 -16
    WIRE 448 128 432 128
    WIRE 496 128 496 0
    WIRE 496 128 448 128
    WIRE 608 128 496 128
    WIRE 656 128 608 128
    WIRE 96 144 -80 144
    WIRE -80 224 -80 144
    WIRE 16 224 -80 224
    WIRE 224 224 16 224
    WIRE 304 224 288 224
    WIRE 432 224 432 128
    WIRE 432 224 384 224
    WIRE -80 240 -80 224
    WIRE 16 240 16 224
    WIRE -480 320 -480 160
    WIRE -480 320 -560 320
    WIRE -560 336 -560 320
    WIRE -480 336 -480 320
    WIRE -352 336 -352 176
    WIRE -352 336 -480 336
    WIRE -336 336 -352 336
    WIRE -80 336 -80 320
    WIRE -80 336 -336 336
    WIRE 16 336 16 304
    WIRE 16 336 -80 336
    WIRE -480 464 -480 336
    WIRE -336 496 -336 336
    WIRE -480 656 -480 544
    WIRE -336 656 -336 560
    WIRE -336 656 -480 656
    WIRE 128 656 128 160
    WIRE 128 656 -336 656
    WIRE 464 656 128 656
    FLAG -560 336 0
    FLAG 64 -64 TP
    FLAG 608 128 output
    FLAG -304 32 0
    SYMBOL voltage -480 64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 400 208 R90
    WINDOW 0 -20 5 VBottom 2
    WINDOW 3 21 -5 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 10.5k
    SYMBOL cap 288 208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 15n
    SYMBOL cap 32 304 R180
    WINDOW 0 -33 54 Left 2
    WINDOW 3 -49 18 Left 2
    SYMATTR InstName C2
    SYMATTR Value 15n
    SYMBOL polcap -368 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100l
    SYMBOL OpAmps\\LT1057 128 64 R0
    SYMATTR InstName U2
    SYMBOL res -176 -256 R0
    SYMATTR InstName R6
    SYMATTR Value 47k
    SYMBOL res 256 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 416 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL schottky 48 -240 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D1
    SYMATTR Value BAT54
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL njf 48 -176 R90
    WINDOW 0 -38 17 VRight 2
    WINDOW 3 -9 -11 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -480 448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 383 -483 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL polcap -352 496 R0
    SYMATTR InstName C5
    SYMATTR Value 100l
    SYMBOL res -96 224 R0
    SYMATTR InstName R2
    SYMATTR Value 10.5k
    SYMBOL cap -240 -160 R180
    WINDOW 0 -27 59 Left 2
    WINDOW 3 -33 2 Left 2
    SYMATTR InstName C3
    SYMATTR Value 10µ
    SYMATTR Description Polarized Capacitor
    SYMATTR Type polcap
    SYMATTR SpiceLine V=4 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60G106ME15" type="X5R"
    SYMBOL res 64 -80 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 330
    SYMBOL res 400 -32 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R5
    SYMATTR Value 820k
    SYMBOL schottky 112 -512 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D2
    SYMATTR Value BAT54
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -176 -496 R0
    SYMATTR InstName R4
    SYMATTR Value 47k
    SYMBOL cap -240 -400 R180
    WINDOW 0 -27 61 Left 2
    WINDOW 3 -37 8 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10µ
    SYMATTR Description Polarized Capacitor
    SYMATTR Type polcap
    SYMATTR SpiceLine V=4 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60G106ME15" type="X5R"
    SYMBOL res 480 -96 R0
    SYMATTR InstName R9
    SYMATTR Value 1k
    SYMBOL res -320 -96 R0
    SYMATTR InstName R10
    SYMATTR Value 2.2
    TEXT -184 472 Left 2 !.tran 0 20s 0s startup

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Edward Rawde@21:1/5 to Bill Sloman on Mon Oct 21 17:01:06 2024
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf5dkk$tubm$1@dont-email.me...
    On 20/10/2024 4:52 pm, Edward Rawde wrote:
    "Edward Rawde" <invalid@invalid.invalid> wrote in message news:vf2569$2f0q$1@nnrp.usenet.blueworldhosting.com...
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vf20si$96u8$1@dont-email.me...
    On 20/10/2024 3:36 am, Edward Rawde wrote:
    "Bill Sloman" <bill.sloman@ieee.org> wrote in message news:vevqip$3q3dn$1@dont-email.me...
    On 19/10/2024 2:03 pm, Edward Rawde wrote:
    "john larkin" <JL@gct.com> wrote in message news:j656hjp1rq659uh61k3q75bipaf386qqh1@4ax.com...
    On Fri, 18 Oct 2024 18:58:43 -0400, "Edward Rawde"
    <invalid@invalid.invalid> wrote:

    "Jeroen Belleman" <jeroen@nospam.please> wrote in message news:veumn5$3fbqu$1@dont-email.me...
    On 10/18/24 23:19, Edward Rawde wrote:
    "Cursitor Doom" <cd999666@notformail.com> wrote in message news:veuirv$3cmo3$10@dont-email.me...
    On Fri, 18 Oct 2024 15:59:09 -0400, Edward Rawde wrote: >>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>> news:veucs2$3cmo3$9@dont-email.me...
    On Fri, 18 Oct 2024 14:20:48 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>> news:veu7kt$3cmo3$8@dont-email.me...
    On Fri, 18 Oct 2024 13:47:02 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>
    "Cursitor Doom" <cd999666@notformail.com> wrote in message >>>>>>>>>>>>>>>>> news:veu45s$3cmo3$5@dont-email.me...
    On Fri, 18 Oct 2024 11:25:19 -0400, Edward Rawde wrote: >>>>>>>>>>>>>>>>>>
    "piglet" <erichpwagner@hotmail.com> wrote in message >>>>>>>>>>>>>>>>>>> news:vetde5$38sbk$1@dont-email.me...
    Edward Rawde <invalid@invalid.invalid> wrote:

    <snip>


    I don't think the circuit below can be improved on in simulation and it's anybody's guess what reality would say.

    Shouldn't be hard to get 60dB down with a suitable filter.

    Version 4
    SHEET 1 2196 916
    WIRE -352 -608 -480 -608
    WIRE 128 -608 -352 -608
    WIRE -160 -496 -256 -496
    WIRE 48 -496 -160 -496
    WIRE 496 -496 112 -496
    WIRE -160 -480 -160 -496
    WIRE -256 -464 -256 -496
    WIRE -256 -368 -256 -400
    WIRE -160 -368 -160 -400
    WIRE -160 -368 -256 -368
    WIRE -256 -320 -256 -368
    WIRE -256 -320 -304 -320
    WIRE -160 -256 -256 -256
    WIRE -16 -256 -160 -256
    WIRE 48 -256 -16 -256
    WIRE 496 -256 496 -496
    WIRE 496 -256 112 -256
    WIRE -160 -240 -160 -256
    WIRE -256 -224 -256 -256
    WIRE -16 -176 -16 -256
    WIRE -304 -128 -304 -320
    WIRE -256 -128 -256 -160
    WIRE -256 -128 -304 -128
    WIRE -160 -128 -160 -160
    WIRE -160 -128 -256 -128
    WIRE -80 -128 -160 -128
    WIRE -48 -128 -80 -128
    WIRE 80 -128 48 -128
    WIRE 160 -128 80 -128
    WIRE 256 -128 240 -128
    WIRE 320 -128 256 -128
    WIRE 448 -128 400 -128
    WIRE -304 -80 -304 -128
    WIRE 496 -80 496 -256
    WIRE -80 -64 -80 -128
    WIRE -32 -64 -80 -64
    WIRE 64 -64 48 -64
    WIRE 80 -64 80 -128
    WIRE 80 -64 64 -64
    WIRE 256 -16 256 -128
    WIRE 304 -16 256 -16
    WIRE 448 -16 448 -128
    WIRE 448 -16 384 -16
    WIRE -304 32 -304 0
    WIRE 256 64 256 -16
    WIRE 256 64 48 64
    WIRE -480 80 -480 -608
    WIRE 128 96 128 -608
    WIRE -352 112 -352 -608
    WIRE 48 112 48 64
    WIRE 96 112 48 112
    WIRE 432 128 160 128
    WIRE 448 128 448 -16
    WIRE 448 128 432 128
    WIRE 496 128 496 0
    WIRE 496 128 448 128
    WIRE 608 128 496 128
    WIRE 656 128 608 128
    WIRE 96 144 -80 144
    WIRE -80 224 -80 144
    WIRE 16 224 -80 224
    WIRE 224 224 16 224
    WIRE 304 224 288 224
    WIRE 432 224 432 128
    WIRE 432 224 384 224
    WIRE -80 240 -80 224
    WIRE 16 240 16 224
    WIRE -480 320 -480 160
    WIRE -480 320 -560 320
    WIRE -560 336 -560 320
    WIRE -480 336 -480 320
    WIRE -352 336 -352 176
    WIRE -352 336 -480 336
    WIRE -336 336 -352 336
    WIRE -80 336 -80 320
    WIRE -80 336 -336 336
    WIRE 16 336 16 304
    WIRE 16 336 -80 336
    WIRE -480 464 -480 336
    WIRE -336 496 -336 336
    WIRE -480 656 -480 544
    WIRE -336 656 -336 560
    WIRE -336 656 -480 656
    WIRE 128 656 128 160
    WIRE 128 656 -336 656
    WIRE 464 656 128 656
    FLAG -560 336 0
    FLAG 64 -64 TP
    FLAG 608 128 output
    FLAG -304 32 0
    SYMBOL voltage -480 64 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 12 7 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V1
    SYMATTR Value 12
    SYMBOL res 400 208 R90
    WINDOW 0 -20 5 VBottom 2
    WINDOW 3 21 -5 VTop 2
    SYMATTR InstName R1
    SYMATTR Value 10.5k
    SYMBOL cap 288 208 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 15n
    SYMBOL cap 32 304 R180
    WINDOW 0 -33 54 Left 2
    WINDOW 3 -49 18 Left 2
    SYMATTR InstName C2
    SYMATTR Value 15n
    SYMBOL polcap -368 112 R0
    SYMATTR InstName C4
    SYMATTR Value 100µ
    SYMBOL OpAmps\\LT1057 128 64 R0
    SYMATTR InstName U2
    SYMBOL res -176 -256 R0
    SYMATTR InstName R6
    SYMATTR Value 47k
    SYMBOL res 256 -144 R90
    WINDOW 0 -1 46 VBottom 2
    WINDOW 3 35 56 VTop 2
    SYMATTR InstName R7
    SYMATTR Value 6.34k
    SYMBOL res 416 -144 R90
    WINDOW 0 -4 61 VBottom 2
    WINDOW 3 39 55 VTop 2
    SYMATTR InstName R8
    SYMATTR Value 13k
    SYMBOL schottky 48 -240 R270
    WINDOW 0 32 32 VTop 2
    WINDOW 3 0 32 VBottom 2
    SYMATTR InstName D1
    SYMATTR Value BAT54
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL njf 48 -176 R90
    WINDOW 0 -38 17 VRight 2
    WINDOW 3 -9 -11 VRight 2
    SYMATTR InstName J1
    SYMATTR Value J112
    SYMBOL voltage -480 448 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 10 135 Left 2
    WINDOW 0 383 -483 Left 2
    WINDOW 3 15 104 Left 2
    SYMATTR SpiceLine Rser=0.1
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL polcap -352 496 R0
    SYMATTR InstName C5
    SYMATTR Value 100µ
    SYMBOL res -96 224 R0
    SYMATTR InstName R2
    SYMATTR Value 10.5k
    SYMBOL cap -240 -160 R180
    WINDOW 0 -27 59 Left 2
    WINDOW 3 -33 2 Left 2
    SYMATTR InstName C3
    SYMATTR Value 10µ
    SYMATTR Description Polarized Capacitor
    SYMATTR Type polcap
    SYMATTR SpiceLine V=4 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60G106ME15" type="X5R"
    SYMBOL res 64 -80 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R3
    SYMATTR Value 330
    SYMBOL res 400 -32 R90
    WINDOW 0 0 56 VBottom 2
    WINDOW 3 32 56 VTop 2
    SYMATTR InstName R5
    SYMATTR Value 820k
    SYMBOL schottky 112 -512 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName D2
    SYMATTR Value BAT54
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res -176 -496 R0
    SYMATTR InstName R4
    SYMATTR Value 47k
    SYMBOL cap -240 -400 R180
    WINDOW 0 -27 61 Left 2
    WINDOW 3 -37 8 Left 2
    SYMATTR InstName C6
    SYMATTR Value 10µ
    SYMATTR Description Polarized Capacitor
    SYMATTR Type polcap
    SYMATTR SpiceLine V=4 Irms=0 Rser=0 Lser=0 mfg="Murata" pn="GRM155R60G106ME15" type="X5R"
    SYMBOL res 480 -96 R0
    SYMATTR InstName R9
    SYMATTR Value 100
    SYMBOL res -320 -96 R0
    SYMATTR InstName R10
    SYMATTR Value 2.2
    TEXT -184 472 Left 2 !.tran 0 20s 5s startup

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