• Re: faster DDS clock

    From Phil Hobbs@21:1/5 to john larkin on Wed Sep 18 21:56:59 2024
    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock frequency, and then a lowpass filter and a comparator, generating a programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts.



    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

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  • From piglet@21:1/5 to john larkin on Wed Sep 18 21:58:13 2024
    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock frequency, and then a lowpass filter and a comparator, generating a programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts.



    How important is it that the duty cycle is 50%?

    --
    piglet

    --- SoupGate-Win32 v1.05
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  • From john larkin@21:1/5 to All on Wed Sep 18 14:39:39 2024
    Assume a DAC being driven with an n-bit sine waveform at some clock
    frequency, and then a lowpass filter and a comparator, generating a programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That
    de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to erichpwagner@hotmail.com on Wed Sep 18 18:51:17 2024
    On Wed, 18 Sep 2024 21:58:13 -0000 (UTC), piglet
    <erichpwagner@hotmail.com> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock
    frequency, and then a lowpass filter and a comparator, generating a
    programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That
    de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts.



    How important is it that the duty cycle is 50%?

    Not super critical. The product is an arbitrary waveform generator and
    a small wobble in the output sample timing won't be noticed.

    I'm thinking I can keep the duty cycle close to 50%.

    The falling-edge jitter should be about the same as the rising edge
    jitter.

    A dual DAC would save me a lot of data lines, so maybe I can go from
    single-8 to a dual-10 DAC or something.

    --- SoupGate-Win32 v1.05
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  • From john larkin@21:1/5 to pcdhSpamMeSenseless@electrooptical. on Wed Sep 18 18:44:34 2024
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock
    frequency, and then a lowpass filter and a comparator, generating a
    programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That
    de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts.



    The usual trouble is that you have to get the other edge from somewhere. An >xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.

    Cheers

    Phil Hobbs

    I'm trying to make things cheaper and simpler. I need a clock that's programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to john larkin on Thu Sep 19 03:28:09 2024
    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock
    frequency, and then a lowpass filter and a comparator, generating a
    programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That
    de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts.



    The usual trouble is that you have to get the other edge from somewhere. An >> xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part
    of the RC + XOR, and dork the ON resistance to square up the duty cycle. (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to pcdhSpamMeSenseless@electrooptical. on Wed Sep 18 20:57:39 2024
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock
    frequency, and then a lowpass filter and a comparator, generating a
    programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That
    de-stresses everything by 2:1, which could well be a net win on jitter >>>> and such. Or gives twice the clock frequency with the same parts.



    The usual trouble is that you have to get the other edge from somewhere. An >>> xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's
    programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part
    of the RC + XOR, and dork the ON resistance to square up the duty cycle. >(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
    it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my
    FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Chris Jones@21:1/5 to john larkin on Thu Sep 19 21:49:30 2024
    On 19/09/2024 7:39 am, john larkin wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock frequency, and then a lowpass filter and a comparator, generating a programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts.


    Doing that doubling trick when you take a sine wave oscillator and feed
    it via a comparator to the reference input of a PLL has a subtle
    advantage: Any additive 1/f voltage noise affecting the input stage of
    the comparator, or from any buffering stages for the sine wave before it
    gets to the comparator, will move the rising and falling edges of the comparator in opposite directions, and if both the rising and falling
    edges are clocking the phase detector of the PLL then the 1/f noise will
    cancel out at low frequencies and not make it through the loop filter,
    and not cause phase modulation of the RF output from the PLL. It's
    really a nice bonus. I guess it wouldn't work so well if the incoming
    waveform had asymmetric slew rates.

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  • From john larkin@21:1/5 to lugnut808@spam.yahoo.com on Thu Sep 19 07:39:50 2024
    On Thu, 19 Sep 2024 21:49:30 +1000, Chris Jones
    <lugnut808@spam.yahoo.com> wrote:

    On 19/09/2024 7:39 am, john larkin wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock
    frequency, and then a lowpass filter and a comparator, generating a
    programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That
    de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts.


    Doing that doubling trick when you take a sine wave oscillator and feed
    it via a comparator to the reference input of a PLL has a subtle
    advantage: Any additive 1/f voltage noise affecting the input stage of
    the comparator, or from any buffering stages for the sine wave before it
    gets to the comparator, will move the rising and falling edges of the >comparator in opposite directions, and if both the rising and falling
    edges are clocking the phase detector of the PLL then the 1/f noise will >cancel out at low frequencies and not make it through the loop filter,
    and not cause phase modulation of the RF output from the PLL. It's
    really a nice bonus. I guess it wouldn't work so well if the incoming >waveform had asymmetric slew rates.

    I can't feed my DDS into a PLL; frequency change has to be
    instantaneous, and cover a huge frequency range.

    I'm generating waveforms that simulate a geared jet engine, which is a
    noisy shakey vibrating thing, so nanoseconds of jitter/phase noise
    doesn't matter much.

    Using a synthesizer would be great, like an LMX2571... no filters or comparators needed. $7 and we'd be all done. But it takes way too
    much math to program.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt@21:1/5 to john larkin on Fri Sep 20 00:30:28 2024
    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock
    frequency, and then a lowpass filter and a comparator, generating a
    programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That
    de-stresses everything by 2:1, which could well be a net win on jitter >>>>> and such. Or gives twice the clock frequency with the same parts.



    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's
    programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part
    of the RC + XOR, and dork the ON resistance to square up the duty cycle.
    (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
    it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my
    FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jan Panteltje@21:1/5 to llc@fonz.dk on Fri Sep 20 05:11:38 2024
    On a sunny day (Fri, 20 Sep 2024 00:30:28 +0200) it happened Lasse Langwadt <llc@fonz.dk> wrote in <vci8m4$o1le$3@dont-email.me>:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>> and such. Or gives twice the clock frequency with the same parts.



    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's
    programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part >>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>> it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my
    FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html

    Last time I used a R2R DAC on my FPGA .. was only 8 bit though.. video
    https://panteltje.nl/pub/FPGA_board_with_25MHz_VCXO_locked_to_rubidium_10MHz_reference_IMG_3724.GIF
    bottom board top right, all the resistors...

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to All on Fri Sep 20 07:49:01 2024
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>> and such. Or gives twice the clock frequency with the same parts.



    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's
    programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part >>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
    it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my
    FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    That's cool. I need 4 DDSs so I'd use two of them, but it
    is still appealing. It looks like I'll have to use an Efinix T130 FPGA
    to get the RAM I need for waveform storage, so I'll have tons of logic
    and i/o's to go hard parallel to the DACs.

    I could use 10 or 9 or 8 bits if that is easier to route, and the
    current outputs dump right into the right kind of filter.

    I have a Spice model of a DDS clock generator. I wonder how awful a
    lowpass filter I can get away with. CLC? Or even RC?



    or 3x8bit@330MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html






    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Bill Sloman@21:1/5 to john larkin on Sat Sep 21 01:49:47 2024
    On 21/09/2024 12:49 am, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>


    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's >>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part >>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>> it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my
    FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    That's cool. I need 4 DDSs so I'd use two of them, but it
    is still appealing. It looks like I'll have to use an Efinix T130 FPGA
    to get the RAM I need for waveform storage, so I'll have tons of logic
    and i/o's to go hard parallel to the DACs.

    I could use 10 or 9 or 8 bits if that is easier to route, and the
    current outputs dump right into the right kind of filter.

    I have a Spice model of a DDS clock generator. I wonder how awful a
    lowpass filter I can get away with. CLC? Or even RC?

    Active RC filters are a lot easier to design than anything involving an inductor. Close tolerance inductors are rare and expensive when they are available. 25 MHz calls for fast op amps, but you can find them.

    Williams and Taylor is a useful reference - not as user-friendly as Don Lancaster, but a whole lot more comprehensive. And they do cover finite
    impulse response filters.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to All on Sat Sep 21 08:42:18 2024
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>> and such. Or gives twice the clock frequency with the same parts.



    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's
    programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part >>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
    it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my
    FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html






    It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
    drive a color CRT monitor, which I expect nobody makes any more.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt@21:1/5 to john larkin on Sat Sep 21 23:56:08 2024
    On 9/20/24 16:49, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>


    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's >>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part >>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>> it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my
    FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    That's cool. I need 4 DDSs so I'd use two of them, but it
    is still appealing. It looks like I'll have to use an Efinix T130 FPGA
    to get the RAM I need for waveform storage, so I'll have tons of logic
    and i/o's to go hard parallel to the DACs.

    you can probably get away with wiring the DAC datalines in parallel and
    use separate clock for each DAC, sorta like DDR

    use DDR output with the data for each DAC, make the clock for each DAC
    use the other DDR outputs, one with 0,1 data the other with 1,0 data

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt@21:1/5 to john larkin on Sun Sep 22 03:11:53 2024
    On 9/21/24 17:42, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>


    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's >>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use
    some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part >>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>> it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my
    FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html






    It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
    drive a color CRT monitor, which I expect nobody makes any more.


    It's for VGA (that's why it has sync and blank input)
    While VGA is old I doubt it is going anywhere soon, it still widely
    used, go buy a server and it has VGA

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to john larkin on Sat Sep 21 18:40:49 2024
    On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/21/24 17:42, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>


    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>
    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>> some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part
    of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>>>> it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the >>>>> filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my >>>>> FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html






    It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
    drive a color CRT monitor, which I expect nobody makes any more.


    It's for VGA (that's why it has sync and blank input)
    While VGA is old I doubt it is going anywhere soon, it still widely
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    And why do we have those firehoses of HDMI connectors and cables? Why
    not use Ethernet or USB out to a monitor?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to All on Sat Sep 21 18:37:26 2024
    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/21/24 17:42, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>>


    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter.

    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's >>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>> some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part >>>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>>> it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the
    filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my >>>> FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast,
    brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html






    It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
    drive a color CRT monitor, which I expect nobody makes any more.


    It's for VGA (that's why it has sync and blank input)
    While VGA is old I doubt it is going anywhere soon, it still widely
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jan Panteltje@21:1/5 to JL@gct.com on Sun Sep 22 08:45:13 2024
    On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin <JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
    to control brightness for the red green and blue guns.
    There are still many analog monitors around.
    I still have a nice one in the attic, my personal particle accelerator.
    Still used in places:
    https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
    History:
    https://en.wikipedia.org/wiki/Cathode-ray_tube

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt@21:1/5 to john larkin on Sun Sep 22 18:37:54 2024
    On 9/22/24 03:40, john larkin wrote:
    On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/21/24 17:42, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>>


    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>>
    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>>> some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part
    of the RC + XOR, and dork the ON resistance to square up the duty cycle.
    (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
    it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the >>>>>> filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my >>>>>> FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky
    filter.


    this will give you 3x10bit@140MHZ DACs for about the same price
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html






    It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
    drive a color CRT monitor, which I expect nobody makes any more.


    It's for VGA (that's why it has sync and blank input)
    While VGA is old I doubt it is going anywhere soon, it still widely
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    And why do we have those firehoses of HDMI connectors and cables? Why
    not use Ethernet or USB out to a monitor?

    HDMI is ~10-20 times the bandwidth of regular ethernet

    there are plenty of monitors that can use USB-C

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to All on Sun Sep 22 13:32:11 2024
    On Sun, 22 Sep 2024 18:37:54 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/22/24 03:40, john larkin wrote:
    On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/21/24 17:42, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>>>>> programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>>>


    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>>>
    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>>>> some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part
    of the RC + XOR, and dork the ON resistance to square up the duty cycle.
    (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
    it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the >>>>>>> filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my >>>>>>> FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges.

    But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky >>>>>>> filter.


    this will give you 3x10bit@140MHZ DACs for about the same price
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz >>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html






    It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
    drive a color CRT monitor, which I expect nobody makes any more.


    It's for VGA (that's why it has sync and blank input)
    While VGA is old I doubt it is going anywhere soon, it still widely
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    And why do we have those firehoses of HDMI connectors and cables? Why
    not use Ethernet or USB out to a monitor?

    HDMI is ~10-20 times the bandwidth of regular ethernet

    Maybe some gamers need multi-gigabit bandwidth.

    I can watch a movie that arrives at my house over a cable modem and
    CAT5 or WiFi to my computers. So a CAT5 from the computer to a monitor
    should be OK.



    there are plenty of monitors that can use USB-C


    That's sensible. The HDMI connectors and cables are klunky.

    We really only need ethernet, USB-c, and one unified wireless/wifi
    network.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt@21:1/5 to john larkin on Sun Sep 22 23:26:35 2024
    On 9/22/24 22:32, john larkin wrote:
    On Sun, 22 Sep 2024 18:37:54 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/22/24 03:40, john larkin wrote:
    On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/21/24 17:42, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/19/24 05:57, john larkin wrote:
    On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <JL@gct.com> wrote:
    On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    john larkin <jl@650pot.com> wrote:
    Assume a DAC being driven with an n-bit sine waveform at some clock
    frequency, and then a lowpass filter and a comparator, generating a
    programmable frequency clock.

    Why not use both edges of the comparator output as our clock? That >>>>>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
    and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>>>>


    The usual trouble is that you have to get the other edge from somewhere. An
    xor gate and an RC is typical.

    Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>>>>
    A 2:1 PLL would probably get my vote.


    I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>>>>> some relatively cheap dual DACs.

    Understood. A Joergesque solution would be to use a discrete FET as part
    of the RC + XOR, and dork the ON resistance to square up the duty cycle.
    (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
    it’s possible to use a TinyLogic inverter with VDD open.)

    Cheers

    Phil Hobbs

    An LVDS line receiver would make a pretty good comparator, after the >>>>>>>> filter.

    If I have enough balls (no pun intended) I can use an LVDS input of my >>>>>>>> FPGA. One could even servo that to exactly 50%.

    I don't know if this FPGA could internally clock on both edges. >>>>>>>>
    But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky >>>>>>>> filter.


    this will give you 3x10bit@140MHZ DACs for about the same price
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html

    or 3x8bit@330MHz
    https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html

    if you opt for the Chinese clone, less than half for 3x10bit@240MHz >>>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html






    It occurrs to me that the use for a 3-channel fast 10-bit DAC is to >>>>>> drive a color CRT monitor, which I expect nobody makes any more.


    It's for VGA (that's why it has sync and blank input)
    While VGA is old I doubt it is going anywhere soon, it still widely
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    And why do we have those firehoses of HDMI connectors and cables? Why
    not use Ethernet or USB out to a monitor?

    HDMI is ~10-20 times the bandwidth of regular ethernet

    anyone that wants sensible refresh rates and better resolutions than was
    the norm 20 years ago do too

    Maybe some gamers need multi-gigabit bandwidth.

    I can watch a movie that arrives at my house over a cable modem and
    CAT5 or WiFi to my computers. So a CAT5 from the computer to a monitor
    should be OK.

    that's lossy compressed to the extreme and adds lots of latency which
    for a movie doesn't matter, but for a desktop display it would unbearable

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to All on Sun Sep 22 19:10:37 2024
    On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid>
    wrote:

    On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin ><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
    to control brightness for the red green and blue guns.
    There are still many analog monitors around.
    I still have a nice one in the attic, my personal particle accelerator.
    Still used in places:
    https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
    History:
    https://en.wikipedia.org/wiki/Cathode-ray_tube


    I wonder how many people here are using a CRT monitor. Or know
    somebody who does.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jan Panteltje@21:1/5 to JL@gct.com on Mon Sep 23 07:42:03 2024
    On a sunny day (Sun, 22 Sep 2024 19:10:37 -0700) it happened john larkin <JL@gct.com> wrote in <qej1fj9tphl57fh8atqi8uqtc3aqev7c25@4ax.com>:

    On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid>
    wrote:

    On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin >><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
    to control brightness for the red green and blue guns.
    There are still many analog monitors around.
    I still have a nice one in the attic, my personal particle accelerator. >>Still used in places:

    https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
    History:
    https://en.wikipedia.org/wiki/Cathode-ray_tube


    I wonder how many people here are using a CRT monitor. Or know
    somebody who does.


    Did not we ship all old stuff to third world countries as garbage?

    Some CRT monitiors, like tha old color Samsung I still have, were very good and brighter than the LCD I now sit in front of.
    And I still use my old Trio analog scope with a real green CRT!
    Also for playing old analog video of course:
    https://panteltje.nl/panteltje/scope_tv/index.html
    after the WW3 nuking that will be great to know how to do,
    with tubes of course, when all semi-conductors will be conductors...


    In a way I regret throwing away my old BW CRT portable TV...
    I had added a video input and it could display 80x40 text no problem from my Z80 system.

    Analog video is still in use here from some of my security cams...
    but digitally recorded...

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From john larkin@21:1/5 to All on Mon Sep 23 06:59:56 2024
    On Mon, 23 Sep 2024 07:42:03 GMT, Jan Panteltje <alien@comet.invalid>
    wrote:

    On a sunny day (Sun, 22 Sep 2024 19:10:37 -0700) it happened john larkin ><JL@gct.com> wrote in <qej1fj9tphl57fh8atqi8uqtc3aqev7c25@4ax.com>:

    On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid> >>wrote:

    On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin >>><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six >>>>feet, and convert it back to digital.

    Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
    to control brightness for the red green and blue guns.
    There are still many analog monitors around.
    I still have a nice one in the attic, my personal particle accelerator. >>>Still used in places:

    https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
    History:
    https://en.wikipedia.org/wiki/Cathode-ray_tube


    I wonder how many people here are using a CRT monitor. Or know
    somebody who does.


    Did not we ship all old stuff to third world countries as garbage?

    Some CRT monitiors, like tha old color Samsung I still have, were very good and brighter than the LCD I now sit in front of.
    And I still use my old Trio analog scope with a real green CRT!
    Also for playing old analog video of course:
    https://panteltje.nl/panteltje/scope_tv/index.html
    after the WW3 nuking that will be great to know how to do,
    with tubes of course, when all semi-conductors will be conductors...


    In a way I regret throwing away my old BW CRT portable TV...
    I had added a video input and it could display 80x40 text no problem from my Z80 system.

    Analog video is still in use here from some of my security cams...
    but digitally recorded...

    The really cool displays are OLED.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jan Panteltje@21:1/5 to JL@gct.com on Mon Sep 23 15:22:55 2024
    On a sunny day (Mon, 23 Sep 2024 06:59:56 -0700) it happened john larkin <JL@gct.com> wrote in <02t2fj5kgu82k9drjiv87j88r0431u8s84@4ax.com>:

    On Mon, 23 Sep 2024 07:42:03 GMT, Jan Panteltje <alien@comet.invalid>
    wrote:

    On a sunny day (Sun, 22 Sep 2024 19:10:37 -0700) it happened john larkin >><JL@gct.com> wrote in <qej1fj9tphl57fh8atqi8uqtc3aqev7c25@4ax.com>:

    On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid> >>>wrote:

    On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin >>>><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk> >>>>>wrote:
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six >>>>>feet, and convert it back to digital.

    Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
    to control brightness for the red green and blue guns.
    There are still many analog monitors around.
    I still have a nice one in the attic, my personal particle accelerator. >>>>Still used in places:


    https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
    History:
    https://en.wikipedia.org/wiki/Cathode-ray_tube


    I wonder how many people here are using a CRT monitor. Or know
    somebody who does.


    Did not we ship all old stuff to third world countries as garbage?

    Some CRT monitiors, like tha old color Samsung I still have, were very good and brighter than the LCD I now sit in front of.
    And I still use my old Trio analog scope with a real green CRT!
    Also for playing old analog video of course:
    https://panteltje.nl/panteltje/scope_tv/index.html
    after the WW3 nuking that will be great to know how to do,
    with tubes of course, when all semi-conductors will be conductors...


    In a way I regret throwing away my old BW CRT portable TV...
    I had added a video input and it could display 80x40 text no problem from my Z80 system.

    Analog video is still in use here from some of my security cams...
    but digitally recorded...

    The really cool displays are OLED.

    I have several in use now, this small one I had to replace after about 8 years because of burn-in:
    https://panteltje.nl/panteltje/pic/gm_pic2/GPS_clock_with_GPS_off_local_IMG_4393.JPG

    Here an other OLED is use:
    https://panteltje.online/pub/SWR_bridge_on_dummy_load_IMG_5046.JPG

    My new TV is a Samsung QlED however...
    LCD like, never a burn-in problem, brighter for light rooms as where I have mine.
    So far I am happy with it.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jasen Betts@21:1/5 to john larkin on Fri Sep 27 08:04:19 2024
    On 2024-09-22, john larkin <JL@gct.com> wrote:
    On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:

    On 9/21/24 17:42, john larkin wrote:
    On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:


    It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
    drive a color CRT monitor, which I expect nobody makes any more.


    It's for VGA (that's why it has sync and blank input)
    While VGA is old I doubt it is going anywhere soon, it still widely
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    And why do we have those firehoses of HDMI connectors and cables? Why
    not use Ethernet or USB out to a monitor?

    They do, an IP based KVM (built in on most servers), is fine for an opeating system install, (especially if the server is on a different continent), but admittedly a direct IP connection to the installer OS is better (so I select that option as soon as it is available).

    On the other hand VGA over CAT5 is also a thing. I think they use
    baluns at each end.

    --
    Jasen.
    🇺🇦 Слава Україні

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jasen Betts@21:1/5 to john larkin on Fri Sep 27 08:07:26 2024
    On 2024-09-23, john larkin <JL@gct.com> wrote:
    On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid>
    wrote:

    On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin >><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:

    On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
    wrote:
    used, go buy a server and it has VGA


    Seems silly to take digital data, convert it to analog, ship it six
    feet, and convert it back to digital.

    Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
    to control brightness for the red green and blue guns.
    There are still many analog monitors around.
    I still have a nice one in the attic, my personal particle accelerator. >>Still used in places:
    https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
    History:
    https://en.wikipedia.org/wiki/Cathode-ray_tube


    I wonder how many people here are using a CRT monitor. Or know
    somebody who does.

    I have one that I use occasionally, and a CRT oscilloscope that
    I use less often.



    --
    Jasen.
    🇺🇦 Слава Україні

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)