Assume a DAC being driven with an n-bit sine waveform at some clock frequency, and then a lowpass filter and a comparator, generating a programmable frequency clock.
Why not use both edges of the comparator output as our clock? That de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
Assume a DAC being driven with an n-bit sine waveform at some clock frequency, and then a lowpass filter and a comparator, generating a programmable frequency clock.
Why not use both edges of the comparator output as our clock? That de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
How important is it that the duty cycle is 50%?
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An >xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
Cheers
Phil Hobbs
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An >> xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter >>>> and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An >>> xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle. >(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
Assume a DAC being driven with an n-bit sine waveform at some clock frequency, and then a lowpass filter and a comparator, generating a programmable frequency clock.
Why not use both edges of the comparator output as our clock? That de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
On 19/09/2024 7:39 am, john larkin wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts.
Doing that doubling trick when you take a sine wave oscillator and feed
it via a comparator to the reference input of a PLL has a subtle
advantage: Any additive 1/f voltage noise affecting the input stage of
the comparator, or from any buffering stages for the sine wave before it
gets to the comparator, will move the rising and falling edges of the >comparator in opposite directions, and if both the rising and falling
edges are clocking the phase detector of the PLL then the 1/f noise will >cancel out at low frequencies and not make it through the loop filter,
and not cause phase modulation of the RF output from the PLL. It's
really a nice bonus. I guess it wouldn't work so well if the incoming >waveform had asymmetric slew rates.
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That
de-stresses everything by 2:1, which could well be a net win on jitter >>>>> and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>> and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part >>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>> it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>> and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part >>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's >>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part >>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>> it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
That's cool. I need 4 DDSs so I'd use two of them, but it
is still appealing. It looks like I'll have to use an Efinix T130 FPGA
to get the RAM I need for waveform storage, so I'll have tons of logic
and i/o's to go hard parallel to the DACs.
I could use 10 or 9 or 8 bits if that is easier to route, and the
current outputs dump right into the right kind of filter.
I have a Spice model of a DDS clock generator. I wonder how awful a
lowpass filter I can get away with. CLC? Or even RC?
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>> and such. Or gives twice the clock frequency with the same parts.
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's
programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part >>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz >https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's >>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part >>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>> it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
That's cool. I need 4 DDSs so I'd use two of them, but it
is still appealing. It looks like I'll have to use an Efinix T130 FPGA
to get the RAM I need for waveform storage, so I'll have tons of logic
and i/o's to go hard parallel to the DACs.
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's >>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use
some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part >>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>> it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my
FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/21/24 17:42, john larkin wrote:
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>> some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>>>> it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the >>>>> filter.
If I have enough balls (no pun intended) I can use an LVDS input of my >>>>> FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
On 9/21/24 17:42, john larkin wrote:
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter >>>>>>>> and such. Or gives twice the clock frequency with the same parts. >>>>>>>>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter.
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's >>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>> some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part >>>>> of the RC + XOR, and dork the ON resistance to square up the duty cycle. >>>>> (He’d probably use a CD4007 DIY gate package to do a few at once. Maybe >>>>> it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the
filter.
If I have enough balls (no pun intended) I can use an LVDS input of my >>>> FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast,
brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/21/24 17:42, john larkin wrote:
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>>
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>>> some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the >>>>>> filter.
If I have enough balls (no pun intended) I can use an LVDS input of my >>>>>> FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky
filter.
this will give you 3x10bit@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
And why do we have those firehoses of HDMI connectors and cables? Why
not use Ethernet or USB out to a monitor?
On 9/22/24 03:40, john larkin wrote:
On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/21/24 17:42, john larkin wrote:
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock >>>>>>>>>>> frequency, and then a lowpass filter and a comparator, generating a >>>>>>>>>>> programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>>>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>>>
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>>>> some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the >>>>>>> filter.
If I have enough balls (no pun intended) I can use an LVDS input of my >>>>>>> FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges.
But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky >>>>>>> filter.
this will give you 3x10bit@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz >>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
And why do we have those firehoses of HDMI connectors and cables? Why
not use Ethernet or USB out to a monitor?
HDMI is ~10-20 times the bandwidth of regular ethernet
there are plenty of monitors that can use USB-C
On Sun, 22 Sep 2024 18:37:54 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/22/24 03:40, john larkin wrote:
On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/21/24 17:42, john larkin wrote:
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/19/24 05:57, john larkin wrote:
On Thu, 19 Sep 2024 03:28:09 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <JL@gct.com> wrote:
On Wed, 18 Sep 2024 21:56:59 -0000 (UTC), Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
john larkin <jl@650pot.com> wrote:
Assume a DAC being driven with an n-bit sine waveform at some clock
frequency, and then a lowpass filter and a comparator, generating a
programmable frequency clock.
Why not use both edges of the comparator output as our clock? That >>>>>>>>>>>> de-stresses everything by 2:1, which could well be a net win on jitter
and such. Or gives twice the clock frequency with the same parts. >>>>>>>>>>>>
The usual trouble is that you have to get the other edge from somewhere. An
xor gate and an RC is typical.
Any asymmetry in the square wave turns into subharmonic jitter. >>>>>>>>>>>
A 2:1 PLL would probably get my vote.
I'm trying to make things cheaper and simpler. I need a clock that's >>>>>>>>>> programmable up to maybe 20 or 25 MHz, and it would be nice to use >>>>>>>>>> some relatively cheap dual DACs.
Understood. A Joergesque solution would be to use a discrete FET as part
of the RC + XOR, and dork the ON resistance to square up the duty cycle.
(He’d probably use a CD4007 DIY gate package to do a few at once. Maybe
it’s possible to use a TinyLogic inverter with VDD open.)
Cheers
Phil Hobbs
An LVDS line receiver would make a pretty good comparator, after the >>>>>>>> filter.
If I have enough balls (no pun intended) I can use an LVDS input of my >>>>>>>> FPGA. One could even servo that to exactly 50%.
I don't know if this FPGA could internally clock on both edges. >>>>>>>>
But I can get a TI DAC908 for under $5, so may just clock that fast, >>>>>>>> brute force at 100 MHz or so. That would make 20 MHz with a dinky >>>>>>>> filter.
this will give you 3x10bit@140MHZ DACs for about the same price
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7123KSTZ140-RL_C172724.html
or 3x8bit@330MHz
https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_Analog-Devices-ADV7125JSTZ330_C662165.html
if you opt for the Chinese clone, less than half for 3x10bit@240MHz >>>>>>> https://www.lcsc.com/product-detail/Digital-to-Analog-Converters-DAC_HTCSEMI-HT7123ARQZ_C2886392.html
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to >>>>>> drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
And why do we have those firehoses of HDMI connectors and cables? Why
not use Ethernet or USB out to a monitor?
HDMI is ~10-20 times the bandwidth of regular ethernet
Maybe some gamers need multi-gigabit bandwidth.
I can watch a movie that arrives at my house over a cable modem and
CAT5 or WiFi to my computers. So a CAT5 from the computer to a monitor
should be OK.
On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin ><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
to control brightness for the red green and blue guns.
There are still many analog monitors around.
I still have a nice one in the attic, my personal particle accelerator.
Still used in places:
https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
History:
https://en.wikipedia.org/wiki/Cathode-ray_tube
On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid>
wrote:
On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin >><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
to control brightness for the red green and blue guns.
There are still many analog monitors around.
I still have a nice one in the attic, my personal particle accelerator. >>Still used in places:
https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
History:
https://en.wikipedia.org/wiki/Cathode-ray_tube
I wonder how many people here are using a CRT monitor. Or know
somebody who does.
On a sunny day (Sun, 22 Sep 2024 19:10:37 -0700) it happened john larkin ><JL@gct.com> wrote in <qej1fj9tphl57fh8atqi8uqtc3aqev7c25@4ax.com>:
On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid> >>wrote:
On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin >>><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six >>>>feet, and convert it back to digital.
Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
to control brightness for the red green and blue guns.
There are still many analog monitors around.
I still have a nice one in the attic, my personal particle accelerator. >>>Still used in places:
https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
History:
https://en.wikipedia.org/wiki/Cathode-ray_tube
I wonder how many people here are using a CRT monitor. Or know
somebody who does.
Did not we ship all old stuff to third world countries as garbage?
Some CRT monitiors, like tha old color Samsung I still have, were very good and brighter than the LCD I now sit in front of.
And I still use my old Trio analog scope with a real green CRT!
Also for playing old analog video of course:
https://panteltje.nl/panteltje/scope_tv/index.html
after the WW3 nuking that will be great to know how to do,
with tubes of course, when all semi-conductors will be conductors...
In a way I regret throwing away my old BW CRT portable TV...
I had added a video input and it could display 80x40 text no problem from my Z80 system.
Analog video is still in use here from some of my security cams...
but digitally recorded...
On Mon, 23 Sep 2024 07:42:03 GMT, Jan Panteltje <alien@comet.invalid>
wrote:
On a sunny day (Sun, 22 Sep 2024 19:10:37 -0700) it happened john larkin >><JL@gct.com> wrote in <qej1fj9tphl57fh8atqi8uqtc3aqev7c25@4ax.com>:
On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid> >>>wrote:
On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin >>>><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk> >>>>>wrote:
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six >>>>>feet, and convert it back to digital.
Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
to control brightness for the red green and blue guns.
There are still many analog monitors around.
I still have a nice one in the attic, my personal particle accelerator. >>>>Still used in places:
https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
History:
https://en.wikipedia.org/wiki/Cathode-ray_tube
I wonder how many people here are using a CRT monitor. Or know
somebody who does.
Did not we ship all old stuff to third world countries as garbage?
Some CRT monitiors, like tha old color Samsung I still have, were very good and brighter than the LCD I now sit in front of.
And I still use my old Trio analog scope with a real green CRT!
Also for playing old analog video of course:
https://panteltje.nl/panteltje/scope_tv/index.html
after the WW3 nuking that will be great to know how to do,
with tubes of course, when all semi-conductors will be conductors...
In a way I regret throwing away my old BW CRT portable TV...
I had added a video input and it could display 80x40 text no problem from my Z80 system.
Analog video is still in use here from some of my security cams...
but digitally recorded...
The really cool displays are OLED.
On Sat, 21 Sep 2024 18:37:26 -0700, john larkin <JL@gct.com> wrote:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
On 9/21/24 17:42, john larkin wrote:
On Fri, 20 Sep 2024 00:30:28 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
It occurrs to me that the use for a 3-channel fast 10-bit DAC is to
drive a color CRT monitor, which I expect nobody makes any more.
It's for VGA (that's why it has sync and blank input)
While VGA is old I doubt it is going anywhere soon, it still widely
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
And why do we have those firehoses of HDMI connectors and cables? Why
not use Ethernet or USB out to a monitor?
On Sun, 22 Sep 2024 08:45:13 GMT, Jan Panteltje <alien@comet.invalid>
wrote:
On a sunny day (Sat, 21 Sep 2024 18:37:26 -0700) it happened john larkin >><JL@gct.com> wrote in <54tuejh1gdvq6i2tist29h0ikmmo55ks3u@4ax.com>:
On Sun, 22 Sep 2024 03:11:53 +0200, Lasse Langwadt <llc@fonz.dk>
wrote:
used, go buy a server and it has VGA
Seems silly to take digital data, convert it to analog, ship it six
feet, and convert it back to digital.
Well the receiving site was analog amps that where outputing high voltage to CRT R,G,B grids
to control brightness for the red green and blue guns.
There are still many analog monitors around.
I still have a nice one in the attic, my personal particle accelerator. >>Still used in places:
https://www.electronicdesign.com/technologies/industrial/displays/article/55126442/thomas-electronics-the-evolution-of-cathode-ray-tube-crt-monitor-technology
History:
https://en.wikipedia.org/wiki/Cathode-ray_tube
I wonder how many people here are using a CRT monitor. Or know
somebody who does.
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