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  • decimating a delta-sigma ADC

    From John Larkin@21:1/5 to All on Wed Oct 4 09:56:01 2023
    There are some dynamite isolated d-s ADCs around. You give them a 20
    MHz clock and they output a single clocked logic level whose duty
    cycle expresses the analog input.

    The data bit is "decimated", really averaged, to give an integer
    analog value. That is usually done in an FPGA, with a sinc3 filter or something.

    I'm wondering of such an ADC can be used without an FPGA.

    I guess an analog lowpass filter and a regular low-speed ADC might
    work, at moderate accuracy.

    Or, more radical, use the SPI port of a uP to gather up bits and let
    software take over. A 125 MHz ARM has a lot of compute power.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Wed Oct 4 10:28:20 2023
    onsdag den 4. oktober 2023 kl. 18.56.24 UTC+2 skrev John Larkin:
    There are some dynamite isolated d-s ADCs around. You give them a 20
    MHz clock and they output a single clocked logic level whose duty
    cycle expresses the analog input.

    The data bit is "decimated", really averaged, to give an integer
    analog value. That is usually done in an FPGA, with a sinc3 filter or something.

    I'm wondering of such an ADC can be used without an FPGA.

    I guess an analog lowpass filter and a regular low-speed ADC might
    work, at moderate accuracy.

    Or, more radical, use the SPI port of a uP to gather up bits and let
    software take over. A 125 MHz ARM has a lot of compute power.

    or use the module in some MCUs meant for DSM/PDM

    https://www.st.com/resource/en/application_note/an5027-interfacing-pdm-digital-microphones-using-stm32-mcus-and-mpus-stmicroelectronics.pdf

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Wed Oct 4 16:27:10 2023
    On Wednesday, October 4, 2023 at 12:56:24 PM UTC-4, John Larkin wrote:
    There are some dynamite isolated d-s ADCs around. You give them a 20
    MHz clock and they output a single clocked logic level whose duty
    cycle expresses the analog input.

    The data bit is "decimated", really averaged, to give an integer
    analog value. That is usually done in an FPGA, with a sinc3 filter or something.

    I'm wondering of such an ADC can be used without an FPGA.

    I guess an analog lowpass filter and a regular low-speed ADC might
    work, at moderate accuracy.

    Or, more radical, use the SPI port of a uP to gather up bits and let software take over. A 125 MHz ARM has a lot of compute power.

    It's not the error output that suffers using a simple filter, it's the response time, so, essentially, the upper frequency response. But, you can use a higher cutoff on the filter for a faster response time, which will impact the output error.

    --

    Rick C.

    - Get 1,000 miles of free Supercharging
    - Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)