Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
John Larkin <jl@997PotHill.com> wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
I have an app note from EPC that says that the gates are pretty delicate. >Since the gate is in contact with the 2DEG, I’d expect it to be very >vulnerable to hot-carrier damage.
I’ll try to dig out the app note.
Cheers
Phil Hobbs
John Larkin <jl@997PotHill.com> wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
I have an app note from EPC that says that the gates are pretty delicate. >Since the gate is in contact with the 2DEG, I’d expect it to be very >vulnerable to hot-carrier damage.
I’ll try to dig out the app note.
Cheers
Phil Hobbs
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily >short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <jl@997PotHill.com>
wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily >>short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
I have experience with Rohm SiC FETs. These were -4V maximum negative >voltage for those gen 3 (I think) parts.
They do NOT like being over-biased negatively. I think everybody's
SiC FETs don't like too much negative voltage.
I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.
My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.
boB
On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:
On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com> >wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily >>short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
I have experience with Rohm SiC FETs. These were -4V maximum negative >voltage for those gen 3 (I think) parts.
They do NOT like being over-biased negatively. I think everybody's
SiC FETs don't like too much negative voltage.
I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.
My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.
boB
Right. I want to run the Cree gates at +15 and -5, and the upper fet
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.
tirsdag den 26. september 2023 kl. 18.53.44 UTC+2 skrev John Larkin:
On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:
On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com> >wrote:
Does anyone know anything about the effects of negaive-voltage >>zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>I'm wondering about what might happen in the rare case that I zener >>the gate by a mA or so. The intent is to drive it -5 to +15, but the >>-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily >>short-term. I have seen long-term changes in some Gan parts from >>abusing the gate a bit.
googling hasn't helped.
I have experience with Rohm SiC FETs. These were -4V maximum negative >voltage for those gen 3 (I think) parts.
They do NOT like being over-biased negatively. I think everybody's
SiC FETs don't like too much negative voltage.
I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.
My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.
boB
Right. I want to run the Cree gates at +15 and -5, and the upper fet source pulses to +500, so I have to be careful that there is no caseplenty with <1pf and ~5Vbr , https://www.onsemi.com/products/discrete-power-modules/esd-protection-diodes
where I over-voltage the gate in either direction. I want speed, and zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.
tirsdag den 26. september 2023 kl. 18.53.44 UTC+2 skrev John Larkin:
On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:
On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com>Right. I want to run the Cree gates at +15 and -5, and the upper fet
wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.
They do NOT like being over-biased negatively. I think everybody's
SiC FETs don't like too much negative voltage.
I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.
My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.
boB
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.
plenty with <1pf and ~5Vbr , https://www.onsemi.com/products/discrete-power-modules/esd-protection-diodes
Does anyone know anything about the effects of negaive-voltagePlease check out: https://www.powerelectronicsnews.com/how-to-select-the-right-gate-driver-for-your-sic-mosfet/
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
On Monday, September 25, 2023 at 10:37:25?PM UTC+5:30, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltagePlease check out: >https://www.powerelectronicsnews.com/how-to-select-the-right-gate-driver-for-your-sic-mosfet/
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
Also if you use the search string "SiC FET gate driver" on Google, a list of semiconductor device
manufacturers(notably Infinieon, TI etc.,) is shown, which have whole sets of gate driver ICs for both
SiC and GaN power FETs.
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
What does your gate driver look like? Maybe you just need better decoupling.
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs <bloggs.fredbloggs.fred@gmail.com> wrote:
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
What does your gate driver look like? Maybe you just need better decoupling.
This looks pretty good:
https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs <bloggs.fred...@gmail.com> wrote:
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
What does your gate driver look like? Maybe you just need better decoupling. This looks pretty good:
https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.
On Wednesday, September 27, 2023 at 10:56:15 AM UTC-4, John Larkin wrote:
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
<bloggs.fred...@gmail.com> wrote:
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:This looks pretty good:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>>> I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
What does your gate driver look like? Maybe you just need better decoupling.
https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.
Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.
That UCC5120 is powerful. I'm surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC's take though.
On 27/09/2023 15:55, John Larkin wrote:
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>>> I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
What does your gate driver look like? Maybe you just need better decoupling.
This looks pretty good:
https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.
Or use BSS126 / LND150 as pulldowns?
piglet
On Wednesday, September 27, 2023 at 10:56:15?AM UTC-4, John Larkin wrote:
On Wed, 27 Sep 2023 07:22:31 -0700 (PDT), Fred Bloggs
<bloggs.fred...@gmail.com> wrote:
On Monday, September 25, 2023 at 1:07:25?PM UTC-4, John Larkin wrote:This looks pretty good:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
What does your gate driver look like? Maybe you just need better decoupling.
https://www.dropbox.com/scl/fi/egp4a8oq1g5hnfryry84g/Ucc_Cree.jpg?rlkey=qoyam26226iyggw5whm91ahx8&raw=1
If I change one dc/dc converter, I can make the -10 into -24, which
makes things nicer. R1+R2 can get bigger, which helps when they have
to go from 5 to 500 volts across them.
Generally speaking, larger resistance makes for more damping irrespective of amplitudes, and you can go through the time constant modeling jazz, but pulling to a lower voltage via a resistor speeds up the fall time.
That UCC5120 is powerful. I'm surprised the 4040 can take the abuse. Have no idea how much gate charge those SiC's take though.
On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:
On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com> >wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and >>I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily >>short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
I have experience with Rohm SiC FETs. These were -4V maximum negative >voltage for those gen 3 (I think) parts.
They do NOT like being over-biased negatively. I think everybody's
SiC FETs don't like too much negative voltage.
I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.
My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.
boB
Right. I want to run the Cree gates at +15 and -5, and the upper fet
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.
SiC fets are hard to drive but otherwise great.
On Tuesday, September 26, 2023 at 9:53:44?AM UTC-7, John Larkin wrote:
On Tue, 26 Sep 2023 09:15:13 -0700, boB <b...@K7IQ.com> wrote:
On Mon, 25 Sep 2023 10:07:09 -0700, John Larkin <j...@997PotHill.com>Right. I want to run the Cree gates at +15 and -5, and the upper fet
wrote:
Does anyone know anything about the effects of negaive-voltage
zenering the gate of a SiC power fet?
Specifically, I'm designing a gate driver for the Cree C2M0280120D and
I'm wondering about what might happen in the rare case that I zener
the gate by a mA or so. The intent is to drive it -5 to +15, but the
-5 could be more in some pathological case.
I'll get some from stock later and test some, but that's necessarily
short-term. I have seen long-term changes in some Gan parts from
abusing the gate a bit.
googling hasn't helped.
I have experience with Rohm SiC FETs. These were -4V maximum negative
voltage for those gen 3 (I think) parts.
They do NOT like being over-biased negatively. I think everybody's
SiC FETs don't like too much negative voltage.
I remember that they start acting very strangely when too much
negative voltage is applied. Even for very short times.
My solution was to use miller clamps. Whatever you do, you need to
check very closely what that Vgs is doing.
boB
source pulses to +500, so I have to be careful that there is no case
where I over-voltage the gate in either direction. I want speed, and
zeners have a lot of capacitance, so a simple dual zener clamp is not
for consideration.
SiC fets are hard to drive but otherwise great.
A non-simple zener clamp would bias the zeners and use switch diodes
to those (the switch diode having presumably lower capacitance).
Switch diodes have low cost, both money and capacitance.
| Sysop: | Keyop |
|---|---|
| Location: | Huddersfield, West Yorkshire, UK |
| Users: | 300 |
| Nodes: | 16 (2 / 14) |
| Uptime: | 83:30:11 |
| Calls: | 6,716 |
| Files: | 12,247 |
| Messages: | 5,358,195 |
