• DDS clock generator in LT Spice

    From John Larkin@21:1/5 to All on Sat Aug 13 07:37:04 2022
    https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1

    https://www.dropbox.com/s/3859sc4qayv3jva/JLDDS_100M_4K_A.asc?dl=0

    It would have been a horror to build a digital phase accumulator in LT
    Spice, so I did it with the bootstrapped sample-and-hold. 1 LSB is 1
    volt, making a 4 kilovolt sawtooth. Close enough.

    We'll probably do this in a cute little efinix FPGA (digitally, and
    not 4KV) which has a megabit of ram, so we can pull more bits out of
    the phase accumulator and have a lot more entries in the sine table,
    which will improve jitter at low frequencies.

    We might even use a 14-bit DAC, if that helps much. The efinix RAM
    comes in slices 5 bits wide, so 14 takes no more than 12. Might
    explore 10 and see what happens.

    Now I need a good way to measure peroid jitter, so I can play with
    options.

    keywords LT Spice DDS clock frequency synthesizer phase accumulator
    jitter filter coffee yardwork sucks

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  • From Ricky@21:1/5 to John Larkin on Sat Aug 13 10:52:43 2022
    On Saturday, August 13, 2022 at 10:37:24 AM UTC-4, John Larkin wrote:
    https://www.dropbox.com/s/1xx7sz1e5rg6jsi/JLDDS_100M_4K.jpg?raw=1

    https://www.dropbox.com/s/3859sc4qayv3jva/JLDDS_100M_4K_A.asc?dl=0

    It would have been a horror to build a digital phase accumulator in LT Spice, so I did it with the bootstrapped sample-and-hold. 1 LSB is 1
    volt, making a 4 kilovolt sawtooth. Close enough.

    We'll probably do this in a cute little efinix FPGA (digitally, and
    not 4KV) which has a megabit of ram, so we can pull more bits out of
    the phase accumulator and have a lot more entries in the sine table,
    which will improve jitter at low frequencies.

    We might even use a 14-bit DAC, if that helps much. The efinix RAM
    comes in slices 5 bits wide, so 14 takes no more than 12. Might
    explore 10 and see what happens.

    Now I need a good way to measure peroid jitter, so I can play with
    options.

    The main aspect of the DDS design to minimize jitter will be to increase the useful size of the phase accumulator, the NCO. If your DAC is only 14 bits, that will cause distortions, but mostly in easy to filter frequencies. Reducing your phase word
    size into the sine generator will generate close in spurs that are very hard to filter.

    You can use a few multipliers and adders to extend the word width of your sine generator on the input side using a variety of techniques. It doesn't need to be one massive look up table. As you have pointed out, when examining a small enough region,
    the sine function is nearly linear.

    --

    Rick C.

    - Get 1,000 miles of free Supercharging
    - Tesla referral code - https://ts.la/richard11209

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