• DDS questions

    From John Larkin@21:1/5 to All on Sun Aug 7 06:55:19 2022
    To make a programmable-frequency clock, the usual DDS chip has

    A frequency-set register, N=32 or 48 bits or something

    which adds, every clock, to a phase accumulator

    M most-significant bits of that goes into a sine lookup table

    Which clocks D bits into a DAC

    Which drives a lowpass filter and a comparator.

    (Ignoring DAC quantization and zero-order hold, this is the tail end
    of the Shannon sampling theorem.)

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    Why not use some clever VHDL and make a trapezoid with faster rise
    time, especially at low frequencies where time quantization and
    comparator errors make a lot of period jitter and the filter doesn't interpolate.

    If one just takes the MSB of the phase accumulator, you have a programmable-frequency clock without all that other junk. But its
    period is quantized to the clock, which gets totally ugly at high
    frequencies. I wonder if some clever math could make that output
    always some perfect multiple of, say 1 Hz or 1 mHz.

    Somebody left a bag of second-rate coffee in the freezer at the cabin, otherwise I'd figure all this out myself.


    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
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  • From Anthony William Sloman@21:1/5 to John Larkin on Sun Aug 7 07:19:39 2022
    On Sunday, August 7, 2022 at 11:55:32 PM UTC+10, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has

    A frequency-set register, N=32 or 48 bits or something

    which adds, every clock, to a phase accumulator

    M most-significant bits of that goes into a sine lookup table

    Which clocks D bits into a DAC

    Which drives a lowpass filter and a comparator.

    (Ignoring DAC quantization and zero-order hold, this is the tail end
    of the Shannon sampling theorem.)

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    The triangle waveform has all the odd harmonics of the fundamental, reduced in proportion to the square of the harmonic number - a triangular wave is just the integral of a square wave. This is a lot more low-harmonic number frequency content than you
    get out of a sine look-up.

    The low-pass filter "wouldn't know" but anybody with any sense looking at it's output would.

    Why not use some clever VHDL and make a trapezoid with faster rise
    time, especially at low frequencies where time quantization and
    comparator errors make a lot of period jitter and the filter doesn't interpolate.

    Because the low order harmonic content is higher.

    If one just takes the MSB of the phase accumulator, you have a programmable-frequency clock without all that other junk. But its
    period is quantized to the clock, which gets totally ugly at high frequencies. I wonder if some clever math could make that output
    always some perfect multiple of, say 1 Hz or 1 mHz.

    Wonder away, but wander away while you are doing it. Doing it here doesn't do anything for the perceived quality of this forum..

    Somebody left a bag of second-rate coffee in the freezer at the cabin, otherwise I'd figure all this out myself.

    You may be flattering yourself.

    --
    Bill Sloman, Sydney

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  • From whit3rd@21:1/5 to John Larkin on Sun Aug 7 08:23:49 2022
    On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has

    A frequency-set register, N=32 or 48 bits or something

    which adds, every clock, to a phase accumulator

    M most-significant bits of that goes into a sine lookup table

    Which clocks D bits into a DAC

    Which drives a lowpass filter and a comparator.

    (Ignoring DAC quantization and zero-order hold, this is the tail end
    of the Shannon sampling theorem.)

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    The sine lookup minimizes the difference function, which is the target of
    the (analog) lowpass filter. That makes it a kind of digital filter doing the bulk of the work. Starting with a square wave, integrating to a triangle wave,
    double-integrating to a parabola wave... is another approach that kinda
    works, but it's low-pass filtering of a sort, that just isn't as elegant. That's
    how a phase-shift oscillator works, basically (those aren't known for precision).

    Other than synchronization possibilities, the triangle-wave basis hasn't an advantage to speak of.

    Why not use some clever VHDL and make a trapezoid with faster rise
    time,...

    Any polygon would have roughly the same harmonics as a triangle, to filter out.

    Another approach, from yesteryear, would be to microstep a motor that
    runs a flywheel and generator; you can get sine and cosine out, and
    it's hard to beat a flywheel for parts cost of high quality filter components. If you ever see a sine source that precesses when tilted, that's why.

    --- SoupGate-Win32 v1.05
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  • From Ricky@21:1/5 to John Larkin on Sun Aug 7 08:53:24 2022
    On Sunday, August 7, 2022 at 9:55:32 AM UTC-4, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has

    A frequency-set register, N=32 or 48 bits or something

    which adds, every clock, to a phase accumulator

    M most-significant bits of that goes into a sine lookup table

    Which clocks D bits into a DAC

    Which drives a lowpass filter and a comparator.

    (Ignoring DAC quantization and zero-order hold, this is the tail end
    of the Shannon sampling theorem.)

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    The lowpass filter it typically, not sentient. But filters provide some amount of attenuation. It seems silly to require a filter with more attenuation because you supply a signal with higher noise content to be filtered. If your spurious signal
    requirements are so low that you can use a filter driven by a triangle wave, you probably could use a simple sine generator, with no filter at all!


    Why not use some clever VHDL and make a trapezoid with faster rise
    time, especially at low frequencies where time quantization and
    comparator errors make a lot of period jitter and the filter doesn't interpolate.

    "Clever VHDL" is an odd way to term it. HDLs simply express a logic design. I assume you mean a clever logic design. That is easily done, but a DDS is already a very efficient means of generating a sine function. The table size can be minimized by
    using approximation methods such as sin (a + b) = sin a cos b + cos a sin b where a is msbs and b is lsbs, so that cos(b) is always close to 1 and cos(a) sin(b) can be a second, smaller table or found with a multiplication. Since cos(a) sin(b) is a
    small value, it does not require as much resolution as sin(a) and the inputs are just the msbs of a and b.

    The CORDIC algorithm is another algorithm to produce a stepped sine function with high resolution.

    In other words, it is not hard to get more resolution than the DAC can ever hope to spit out.


    If one just takes the MSB of the phase accumulator, you have a programmable-frequency clock without all that other junk. But its
    period is quantized to the clock, which gets totally ugly at high frequencies. I wonder if some clever math could make that output
    always some perfect multiple of, say 1 Hz or 1 mHz.

    Yes, you can make your output a perfect multiple of arbitrary time values, by changing the modulus of the phase accumulator. I once constructed a phase accumulator with three sections with different moduli. The middle section had a modulus that gave a
    setting of 1 Hz resolution. The upper two bits were binary to for use as the sign and slope msb to allow folding of the waveform and so reduction of the sine table size (a very common technique). The lsbs were binary to provide fractions of Hz
    resolution. The table was sized to fit the middle counter bits which means it did not fit in a binary sized memory. However, there are other ways of calculating a sine.

    You can also construct a sine using the CORDIC algorithm, or various other approximations.

    It is important to preserve as much phase resolution as you can. The impact of resolution in the output of the sine generator produces errors that mostly appear as harmonics which can be filtered without too much difficulty. Truncation errors in the
    phase word, produce spurious frequencies which include values close to the fundamental of interest. These are hard to filter.


    Somebody left a bag of second-rate coffee in the freezer at the cabin, otherwise I'd figure all this out myself.

    Incomplete thought. Does "second-rate coffee" in the freezer mean you are drinking too much coffee, or that you refuse to drink any and are suffering from withdrawal?

    As much as I love coffee, I had to give it up because caffeine gives me an irregular heartbeat. Not good for the soul.

    --

    Rick C.

    - Get 1,000 miles of free Supercharging
    - Tesla referral code - https://ts.la/richard11209

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  • From John Larkin@21:1/5 to All on Sun Aug 7 09:08:02 2022
    On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whit3rd@gmail.com>
    wrote:

    On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has

    A frequency-set register, N=32 or 48 bits or something

    which adds, every clock, to a phase accumulator

    M most-significant bits of that goes into a sine lookup table

    Which clocks D bits into a DAC

    Which drives a lowpass filter and a comparator.

    (Ignoring DAC quantization and zero-order hold, this is the tail end
    of the Shannon sampling theorem.)

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    The sine lookup minimizes the difference function, which is the target of
    the (analog) lowpass filter. That makes it a kind of digital filter doing the
    bulk of the work. Starting with a square wave, integrating to a triangle wave,
    double-integrating to a parabola wave... is another approach that kinda >works, but it's low-pass filtering of a sort, that just isn't as elegant. That's
    how a phase-shift oscillator works, basically (those aren't known for >precision).

    The positive zero crossing of a sine wave and a triangle look a lot
    alike, a straight line within the attention span of the lowpass
    filter. It can't remember enough long-ago to tell the difference.

    We don't push the Nyquist rate, which needs an ideal lowpass filter.
    In fact, the sawtooth looks better to me... there is more linear
    history before the zero cross than a sine.


    Other than synchronization possibilities, the triangle-wave basis hasn't an >advantage to speak of.

    No sine lookup table and no error contributions from that.


    Why not use some clever VHDL and make a trapezoid with faster rise
    time,...

    Any polygon would have roughly the same harmonics as a triangle, to filter out.

    It's a clock. We don't want to filter out harmonics. Who designs
    digital clocks with low harmonic content?


    Another approach, from yesteryear, would be to microstep a motor that
    runs a flywheel and generator; you can get sine and cosine out, and
    it's hard to beat a flywheel for parts cost of high quality filter components. >If you ever see a sine source that precesses when tilted, that's why.

    There is a clever synchro digitizer that simulates a rotating mass
    internally. It tracks a constant-velocity rotation with zero error.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jjlarkin@highlandtechnology.com on Sun Aug 7 12:57:40 2022
    On Sun, 07 Aug 2022 09:08:02 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:

    On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whit3rd@gmail.com>
    wrote:

    On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has

    A frequency-set register, N=32 or 48 bits or something

    which adds, every clock, to a phase accumulator

    M most-significant bits of that goes into a sine lookup table

    Which clocks D bits into a DAC

    Which drives a lowpass filter and a comparator.

    (Ignoring DAC quantization and zero-order hold, this is the tail end
    of the Shannon sampling theorem.)

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    The sine lookup minimizes the difference function, which is the target of >>the (analog) lowpass filter. That makes it a kind of digital filter doing the
    bulk of the work. Starting with a square wave, integrating to a triangle wave,
    double-integrating to a parabola wave... is another approach that kinda >>works, but it's low-pass filtering of a sort, that just isn't as elegant. That's
    how a phase-shift oscillator works, basically (those aren't known for >>precision).

    The positive zero crossing of a sine wave and a triangle look a lot
    alike, a straight line within the attention span of the lowpass
    filter. It can't remember enough long-ago to tell the difference.

    We don't push the Nyquist rate, which needs an ideal lowpass filter.
    In fact, the sawtooth looks better to me... there is more linear
    history before the zero cross than a sine.


    Other than synchronization possibilities, the triangle-wave basis hasn't an >>advantage to speak of.

    No sine lookup table and no error contributions from that.


    Why not use some clever VHDL and make a trapezoid with faster rise
    time,...

    Any polygon would have roughly the same harmonics as a triangle, to filter out.

    It's a clock. We don't want to filter out harmonics. Who designs
    digital clocks with low harmonic content?

    Not applicable in your application, but in the time world, reference
    clocks are always sent as low-distortion sine waves, because the
    harmonics don't travel in real cable all at the same speed, or all
    have the same temperature coefficient of electrical length (group
    velocity).

    This is the answer to the usual querulous question: Given that the
    first thing done to an arriving reference is to square it up, why
    bother with a sine wave at all?


    Joe Gwinn

    --- SoupGate-Win32 v1.05
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  • From Gerhard Hoffmann@21:1/5 to All on Sun Aug 7 19:07:02 2022
    Am 07.08.22 um 15:55 schrieb John Larkin:

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    Why not use some clever VHDL and make a trapezoid with faster rise
    time, especially at low frequencies where time quantization and
    comparator errors make a lot of period jitter and the filter doesn't interpolate.

    If one just takes the MSB of the phase accumulator, you have a programmable-frequency clock without all that other junk. But its
    period is quantized to the clock, which gets totally ugly at high frequencies. I wonder if some clever math could make that output
    always some perfect multiple of, say 1 Hz or 1 mHz.

    There was a DDS from Stanford Telecom (Standard? T.) that was
    BCD and that thusly could produce exact mHz from 10 MHz etc.

    Just using the MSB would inherit awful phase modulation / noise.

    I have published a sine table on opencores.org with a
    DDS as test bed. It stores only one quarter of the circle and
    mirrors the rest. Table size is generic and taken automagically
    from the connected busses. 0 up to 10 pipeline registers may be
    selected and are strategically inserted as food for the register
    balancer.

    Without any work it ran at 230 MHz on a Spartan6 eval board,
    just by asking for 250 MHz. I needed only 200 MHz.
    Sine and cosine are available at no extra table cost to feed
    the multipliers of a complex mixer.

    It is pure VHDL that does not lock you into a silicon vendor.

    < https://opencores.org/projects/sincos >

    Cordic was ruled out for me because of its delays.
    It is hard to get a digital Costas loop stable when
    it takes a year for the oscillator to follow and it's
    staggering around in the mean time after a frequency change.

    Cheers, Gerhard

    --- SoupGate-Win32 v1.05
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  • From Ricky@21:1/5 to John Larkin on Sun Aug 7 10:11:02 2022
    On Sunday, August 7, 2022 at 12:08:13 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has

    A frequency-set register, N=32 or 48 bits or something

    which adds, every clock, to a phase accumulator

    M most-significant bits of that goes into a sine lookup table

    Which clocks D bits into a DAC

    Which drives a lowpass filter and a comparator.

    (Ignoring DAC quantization and zero-order hold, this is the tail end
    of the Shannon sampling theorem.)

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    The sine lookup minimizes the difference function, which is the target of >the (analog) lowpass filter. That makes it a kind of digital filter doing the
    bulk of the work. Starting with a square wave, integrating to a triangle wave,
    double-integrating to a parabola wave... is another approach that kinda >works, but it's low-pass filtering of a sort, that just isn't as elegant. That's
    how a phase-shift oscillator works, basically (those aren't known for >precision).
    The positive zero crossing of a sine wave and a triangle look a lot
    alike, a straight line within the attention span of the lowpass
    filter. It can't remember enough long-ago to tell the difference.

    We don't push the Nyquist rate, which needs an ideal lowpass filter.
    In fact, the sawtooth looks better to me... there is more linear
    history before the zero cross than a sine.

    Other than synchronization possibilities, the triangle-wave basis hasn't an >advantage to speak of.
    No sine lookup table and no error contributions from that.

    Why not use some clever VHDL and make a trapezoid with faster rise
    time,...

    Any polygon would have roughly the same harmonics as a triangle, to filter out.
    It's a clock. We don't want to filter out harmonics. Who designs
    digital clocks with low harmonic content?

    If you wish to generate a minimum jitter signal, then the sine wave is what you want because is can be filtered most easily. You may think your triangle waveform has the best properties for this, but you aren't being realistic about the properties. I
    expect you are picturing a single wave in your mind and not picturing the eye diagram. At some point in the process the triangle or trapezoid has to be applied to a threshold to become a clock. The steeper the waveform is, the more pronounced will be
    the jitter from the quantization errors. Filtering will only attenuate this, not eliminate. The sine wave is the waveform with the least spurious content, and so the most easily filtered. What is most important, are the close in spurs which are
    difficult to attenuate. Pay attention to those and the rest is just mental masturbation.

    --

    Rick C.

    + Get 1,000 miles of free Supercharging
    + Tesla referral code - https://ts.la/richard11209

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  • From whit3rd@21:1/5 to John Larkin on Sun Aug 7 10:11:44 2022
    On Sunday, August 7, 2022 at 9:08:13 AM UTC-7, John Larkin wrote:
    On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has
    ...
    M most-significant bits of that goes into a sine lookup table

    The sine lookup minimizes the difference function, which is the target of >the (analog) lowpass filter. That makes it a kind of digital filter doing the
    bulk of the work.

    The positive zero crossing of a sine wave and a triangle look a lot
    alike, a straight line within the attention span of the lowpass
    filter. It can't remember enough long-ago to tell the difference.

    But one wouldn't use the zero crossing (adds voltage offset error
    to the timing signal) when a trangle wave has a nice crisp
    cusp to define a timing.

    We don't push the Nyquist rate, which needs an ideal lowpass filter.
    In fact, the sawtooth looks better to me... there is more linear
    history before the zero cross than a sine.

    Other than synchronization possibilities, the triangle-wave basis hasn't an >advantage to speak of.

    No sine lookup table and no error contributions from that.

    But, the triangle wave, for a given amplitude, has lower slew rate (lower
    V signal at delta-T from the zero) than a sine wave. So, lower signal/noise.

    It's a clock. We don't want to filter out harmonics. Who designs
    digital clocks with low harmonic content?

    A 'digital clock' would usually be square-wave, neither triangle or sine.
    The 'trapezoidal wave' suggestion is just a slew-limited square wave.
    Reasons to use a sine for clocking would be analog
    phase comparison in a PLL, or bandwidth limiting (as in,
    a WWVB transmission).

    --- SoupGate-Win32 v1.05
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  • From whit3rd@21:1/5 to John Larkin on Sun Aug 7 11:09:02 2022
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sun Aug 7 10:53:17 2022
    On Sun, 7 Aug 2022 10:11:44 -0700 (PDT), whit3rd <whit3rd@gmail.com>
    wrote:

    On Sunday, August 7, 2022 at 9:08:13 AM UTC-7, John Larkin wrote:
    On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has
    ...
    M most-significant bits of that goes into a sine lookup table

    The sine lookup minimizes the difference function, which is the target of >> >the (analog) lowpass filter. That makes it a kind of digital filter doing the
    bulk of the work.

    The positive zero crossing of a sine wave and a triangle look a lot
    alike, a straight line within the attention span of the lowpass
    filter. It can't remember enough long-ago to tell the difference.

    But one wouldn't use the zero crossing (adds voltage offset error
    to the timing signal) when a trangle wave has a nice crisp
    cusp to define a timing.

    The point of the DDS lowpass filter is to interpolate multiple samples
    and reduce jitter. If we use sharp edges on the waveform, the filter
    just delays but doesn't reduce jitter. May as well use the phase
    accumulator MSB.

    A sawtooth has a nice long straight line rising edge. The filter will
    love that.




    We don't push the Nyquist rate, which needs an ideal lowpass filter.
    In fact, the sawtooth looks better to me... there is more linear
    history before the zero cross than a sine.

    Other than synchronization possibilities, the triangle-wave basis hasn't an >> >advantage to speak of.

    No sine lookup table and no error contributions from that.

    But, the triangle wave, for a given amplitude, has lower slew rate (lower
    V signal at delta-T from the zero) than a sine wave. So, lower signal/noise.


    If D MSBs of the phase accumulator are pushed into the DAC, we get a
    sawtooth that goes rail-to-rail in one DDS cycle. Nice. We conjecture
    that some digital tricks could do even better, make a steeper
    waveform, especially at low frequencies.

    It's a clock. We don't want to filter out harmonics. Who designs
    digital clocks with low harmonic content?

    A 'digital clock' would usually be square-wave, neither triangle or sine.

    Exactly. Synchronous harmonics add no period jitter. But we want to
    make the square clock *after* the analog filter does its Shannon
    thing.



    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sun Aug 7 10:57:07 2022
    On Sun, 7 Aug 2022 19:07:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
    wrote:

    Am 07.08.22 um 15:55 schrieb John Larkin:

    Why do the sine lookup? The ms D bits of the accumulator are a
    triangle waveform. Why not DAC and filter that? The lowpass filter
    wouldn't know... it would interpolate as usual.

    Why not use some clever VHDL and make a trapezoid with faster rise
    time, especially at low frequencies where time quantization and
    comparator errors make a lot of period jitter and the filter doesn't
    interpolate.

    If one just takes the MSB of the phase accumulator, you have a
    programmable-frequency clock without all that other junk. But its
    period is quantized to the clock, which gets totally ugly at high
    frequencies. I wonder if some clever math could make that output
    always some perfect multiple of, say 1 Hz or 1 mHz.

    There was a DDS from Stanford Telecom (Standard? T.) that was
    BCD and that thusly could produce exact mHz from 10 MHz etc.

    We discussed a radix-10 phase accumulator. That's not awful.


    Just using the MSB would inherit awful phase modulation / noise.

    The MSB is the exact average programmed frequency but has one clock of
    p-p jitter.


    I have published a sine table on opencores.org with a
    DDS as test bed. It stores only one quarter of the circle and
    mirrors the rest. Table size is generic and taken automagically
    from the connected busses. 0 up to 10 pipeline registers may be
    selected and are strategically inserted as food for the register
    balancer.

    Without any work it ran at 230 MHz on a Spartan6 eval board,
    just by asking for 250 MHz. I needed only 200 MHz.
    Sine and cosine are available at no extra table cost to feed
    the multipliers of a complex mixer.

    It is pure VHDL that does not lock you into a silicon vendor.

    < https://opencores.org/projects/sincos >

    Cordic was ruled out for me because of its delays.
    It is hard to get a digital Costas loop stable when
    it takes a year for the oscillator to follow and it's
    staggering around in the mean time after a frequency change.

    Cheers, Gerhard



    My question was, why make a sine wave if the final result is a digital
    clock?



    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Gerhard Hoffmann@21:1/5 to All on Sun Aug 7 21:00:02 2022
    Am 07.08.22 um 19:57 schrieb John Larkin:


    My question was, why make a sine wave if the final result is a digital
    clock?

    You can get by with a counter if you are happy with an exact subharmonic
    of the clock source.

    Trying to build a DDS without a sine table is like shooting
    oneself into both feet and then enjoying the feeling as the
    proud winner of the filtering wheelchair championchip.

    I said it here 2 or 3 years ago that the cleanest time stamp
    is a sine zero crossing and maybe a qualifier.
    No dispersion, minimum noise bandwidth.


    Least jitter sine -> square conversion:

    Oliver Collins, Member, IEEE
    The Design of Low Jitter Hard Limiters
    IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 44, NO. 5, MAY 1996

    It resurfaces now & then in the time nuts list on febo.com.


    Cheers, Gerhard

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sun Aug 7 12:53:40 2022
    On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
    wrote:

    Am 07.08.22 um 19:57 schrieb John Larkin:


    My question was, why make a sine wave if the final result is a digital
    clock?

    You can get by with a counter if you are happy with an exact subharmonic
    of the clock source.

    Trying to build a DDS without a sine table is like shooting
    oneself into both feet and then enjoying the feeling as the
    proud winner of the filtering wheelchair championchip.

    What advantage does a sine table have over making a sawtooth directly
    from the MSBs of the phase accumulator? The sine conversion just adds
    errors, seems to me.

    Near the zero crossing, the filter can't tell them apart. The
    comparator isn't very smart.



    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sun Aug 7 12:48:37 2022
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whit3rd@gmail.com>
    wrote:

    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.

    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is incremented infrequently and the filter doesn't do much.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 7 13:27:44 2022
    søndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Sun Aug 7 13:26:12 2022
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    --

    Rick C.

    -+ Get 1,000 miles of free Supercharging
    -+ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Sun Aug 7 13:23:35 2022
    On Sunday, August 7, 2022 at 3:53:55 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk...@arcor.de>
    wrote:
    Am 07.08.22 um 19:57 schrieb John Larkin:


    My question was, why make a sine wave if the final result is a digital
    clock?

    You can get by with a counter if you are happy with an exact subharmonic >of the clock source.

    Trying to build a DDS without a sine table is like shooting
    oneself into both feet and then enjoying the feeling as the
    proud winner of the filtering wheelchair championchip.
    What advantage does a sine table have over making a sawtooth directly
    from the MSBs of the phase accumulator? The sine conversion just adds errors, seems to me.

    Near the zero crossing, the filter can't tell them apart. The
    comparator isn't very smart.

    What a myopic view. The most difficult part of designing a DDS, is the phase truncation error which produces close in spurs, which can not be effectively filtered.

    Whatever. In many ways, Larkin is like many others here who come for expert advice, then ignore it when they don't understand it. It would be so much more productive if he would ask relevant questions instead of trying to think in terms that don't
    apply like localizing the action of a filter to a small segment of the waveform, when filters are typically IIR and so reflect a history of the signal.

    --

    Rick C.

    -- Get 1,000 miles of free Supercharging
    -- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Gerhard Hoffmann@21:1/5 to All on Sun Aug 7 22:37:41 2022
    Am 07.08.22 um 21:53 schrieb John Larkin:
    On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
    wrote:

    Am 07.08.22 um 19:57 schrieb John Larkin:


    My question was, why make a sine wave if the final result is a digital
    clock?

    You can get by with a counter if you are happy with an exact subharmonic
    of the clock source.

    Trying to build a DDS without a sine table is like shooting
    oneself into both feet and then enjoying the feeling as the
    proud winner of the filtering wheelchair championchip.

    What advantage does a sine table have over making a sawtooth directly
    from the MSBs of the phase accumulator? The sine conversion just adds
    errors, seems to me.

    Near the zero crossing, the filter can't tell them apart. The
    comparator isn't very smart.

    A sine is nowhere steeper than at the zero crossing.
    The essence of the Collins paper is that it takes several
    pairs of (filter + amplifier) in cascade, not a dumb comparator.

    Talking of comparators, I just got quite disappointing results
    from an ADCMP580, CML.

    ~70 ps rise and fall time, should be half of that, typ.

    rising edge, falling edge is abt. the same:
    <
    https://www.flickr.com/photos/137684711@N07/52270474769/in/dateposted-public/
    >

    entire cycle:
    <
    https://www.flickr.com/photos/137684711@N07/52269244147/in/dateposted-public/
    >


    Gerhard

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Gerhard Hoffmann@21:1/5 to All on Sun Aug 7 22:47:36 2022
    Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

    The essence of the Collins paper is that it takes several
    pairs of (filter + amplifier) in cascade, not a dumb comparator.

    I forgot:

    The filters have to be tighter from stage to stage.
    There is an optimum.
    In the time nuts archives, there is a spreadsheet
    that computes the number of stages, gain per stage
    and bandwidth.

    Gerhard

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to langwadt@fonz.dk on Sun Aug 7 13:51:54 2022
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    søndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff


    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a
    trapezoid with a steep rise.

    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.

    One way to get low trigger rates, which we do now, is synthesize an
    octave or so at the high end of the DDS and divide after the
    comparator. That has uglies if the DDS is slow to program, like an SPI interface. It's not so awful if we make our own DDS in an FPGA, so we
    can change the DDS frequency and the divisor (almost) simultaneously.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sun Aug 7 14:03:19 2022
    On Sun, 7 Aug 2022 22:37:41 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
    wrote:

    Am 07.08.22 um 21:53 schrieb John Larkin:
    On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
    wrote:

    Am 07.08.22 um 19:57 schrieb John Larkin:


    My question was, why make a sine wave if the final result is a digital >>>> clock?

    You can get by with a counter if you are happy with an exact subharmonic >>> of the clock source.

    Trying to build a DDS without a sine table is like shooting
    oneself into both feet and then enjoying the feeling as the
    proud winner of the filtering wheelchair championchip.

    What advantage does a sine table have over making a sawtooth directly
    from the MSBs of the phase accumulator? The sine conversion just adds
    errors, seems to me.

    Near the zero crossing, the filter can't tell them apart. The
    comparator isn't very smart.

    A sine is nowhere steeper than at the zero crossing.
    The essence of the Collins paper is that it takes several
    pairs of (filter + amplifier) in cascade, not a dumb comparator.

    Talking of comparators, I just got quite disappointing results
    from an ADCMP580, CML.

    ~70 ps rise and fall time, should be half of that, typ.

    rising edge, falling edge is abt. the same:
    < >https://www.flickr.com/photos/137684711@N07/52270474769/in/dateposted-public/

    You are signal averaging. Could the problem be jitter?

    >

    entire cycle:
    < >https://www.flickr.com/photos/137684711@N07/52269244147/in/dateposted-public/



    Gerhard

    My inventory report includes the 580, with the note DECIDED TO NOT
    USE PART. I can't remember why. We do use the 582.



    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 7 14:06:02 2022
    søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
    sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital >> >> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >> >not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a trapezoid with a steep rise.

    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.

    but if the DAC can't run any faster or have any more bits, how?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Miles, KE5FX@21:1/5 to John Larkin on Sun Aug 7 14:53:39 2022
    On Sunday, August 7, 2022 at 1:52:07 PM UTC-7, John Larkin wrote:
    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.

    That's actually a good way to visualize the problem. You don't care
    about the peak, you care about the zero crossings. At frequencies
    where the LSBs toggle less often, the resulting phase error will corrupt
    the zero crossing points at low offset frequencies. You can't fix this
    with a filter, only with a DAC.

    Try it and you'll see (as I did, back when the HI5731 DAC was the SotA
    and I didn't have one in the parts drawer.) The ugliness of the output
    that you will get from the MSB by itself is hard to exaggerate.

    -- john, KE5FX

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From whit3rd@21:1/5 to John Larkin on Sun Aug 7 15:36:23 2022
    On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

    ... My proposed sawtooth has a sharp jump that a sine wave
    doesn't. If the filter has forgotten the jump, the sawtooth is ideal.
    If not, the soft history of a sine wave might be better.

    But, doesn't the 'sharp jump' have synchrony with a clock edge?
    And, doesn't a sharp jump, like a clock, require a big impulse of current out of your filtered
    power supply? The sinewave is cleaner to drive, and less insistent on knowledge
    of dispersion in the dielectric materials. As others have pointed out,
    that's why wiring time delays are precise only with sinewaves: no hook there.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to jmiles@gmail.com on Sun Aug 7 15:28:51 2022
    On Sun, 7 Aug 2022 14:53:39 -0700 (PDT), "John Miles, KE5FX"
    <jmiles@gmail.com> wrote:

    On Sunday, August 7, 2022 at 1:52:07 PM UTC-7, John Larkin wrote:
    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.

    That's actually a good way to visualize the problem. You don't care
    about the peak, you care about the zero crossings. At frequencies
    where the LSBs toggle less often, the resulting phase error will corrupt
    the zero crossing points at low offset frequencies. You can't fix this
    with a filter, only with a DAC.

    Try it and you'll see (as I did, back when the HI5731 DAC was the SotA
    and I didn't have one in the parts drawer.) The ugliness of the output
    that you will get from the MSB by itself is hard to exaggerate.

    -- john, KE5FX

    Anywhere near Nyquist, the DAC output is ghastly. It looks like random
    noise, hard to see anything coherent on a scope. But after a good
    filter, it becomes a beautiful sine wave.

    If you flip the impulse response of a lowpass filter (like doing
    convolution) it shows how much the filter remembers, how much it looks
    back in time. My proposed sawtooth has a sharp jump that a sine wave
    doesn't. If the filter has forgotten the jump, the sawtooth is ideal.
    If not, the soft history of a sine wave might be better.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sun Aug 7 15:55:33 2022
    On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whit3rd@gmail.com>
    wrote:

    On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

    ... My proposed sawtooth has a sharp jump that a sine wave
    doesn't. If the filter has forgotten the jump, the sawtooth is ideal.
    If not, the soft history of a sine wave might be better.

    But, doesn't the 'sharp jump' have synchrony with a clock edge?

    Sure. The dds DAC is clocked by the main clock. Every dac output point
    is clocked.


    And, doesn't a sharp jump, like a clock, require a big impulse of current out of your filtered
    power supply? The sinewave is cleaner to drive, and less insistent on knowledge
    of dispersion in the dielectric materials. As others have pointed out, >that's why wiring time delays are precise only with sinewaves: no hook there.

    We are in the picosecond timing business. We use sub-ns edges for
    clocks and events. We don't use sine waves!

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Sun Aug 7 16:04:40 2022
    On Sunday, August 7, 2022 at 4:52:07 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
    sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital >> >> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >> >not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a trapezoid with a steep rise.

    Making the trapezoid from the NCO output is not the same as making a sine wave and filtering. The "logical end" of that is actually generating a square wave with all the attendant jitter. So the trapezoid would increase the jitter and be harder to
    filter than the sine wave.


    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.

    You must have enough phase bits to prevent phase noise since this produces, hard to filter (meaning impossible) close in spurs.


    One way to get low trigger rates, which we do now, is synthesize an
    octave or so at the high end of the DDS and divide after the
    comparator. That has uglies if the DDS is slow to program, like an SPI interface. It's not so awful if we make our own DDS in an FPGA, so we
    can change the DDS frequency and the divisor (almost) simultaneously.

    Yup. Is there some reason you can't piggy back on the SPI protocol to add bits to control your octave divider?

    --

    Rick C.

    +- Get 1,000 miles of free Supercharging
    +- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Miles, KE5FX@21:1/5 to John Larkin on Sun Aug 7 16:50:40 2022
    On Sunday, August 7, 2022 at 3:55:46 PM UTC-7, John Larkin wrote:
    We are in the picosecond timing business. We use sub-ns edges for
    clocks and events. We don't use sine waves!

    Around here, picosecond-level errors mean that somebody (i.e., me)
    is going to have a bad day at the (proverbial) office. :)

    -- john, KE5FX

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to jmiles@gmail.com on Sun Aug 7 17:53:04 2022
    On Sun, 7 Aug 2022 16:50:40 -0700 (PDT), "John Miles, KE5FX"
    <jmiles@gmail.com> wrote:

    On Sunday, August 7, 2022 at 3:55:46 PM UTC-7, John Larkin wrote:
    We are in the picosecond timing business. We use sub-ns edges for
    clocks and events. We don't use sine waves!

    Around here, picosecond-level errors mean that somebody (i.e., me)
    is going to have a bad day at the (proverbial) office. :)

    -- john, KE5FX

    We swept two edges across one another and poked them into the data and
    clock of an NB7V52 GigaComm flipflop.

    https://www.dropbox.com/s/qahpb8uh1xr53vj/NB7_Steps.jpg?raw=1

    We saw about 60 fS RMS jitter, which is the flop and the circuits that generated the time sweep.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sun Aug 7 17:48:04 2022
    On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whit3rd@gmail.com>
    wrote:

    On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

    ... My proposed sawtooth has a sharp jump that a sine wave
    doesn't. If the filter has forgotten the jump, the sawtooth is ideal.
    If not, the soft history of a sine wave might be better.

    But, doesn't the 'sharp jump' have synchrony with a clock edge?
    And, doesn't a sharp jump, like a clock, require a big impulse of current out of your filtered
    power supply? The sinewave is cleaner to drive, and less insistent on knowledge
    of dispersion in the dielectric materials. As others have pointed out, >that's why wiring time delays are precise only with sinewaves: no hook there.

    The power supply isn't an issue. All sorts of things are whacking the
    power supply.

    But if we make a sawtooth that ramps from -V to +V, and we filter
    that, the big negative spike happens at the input clock rate, so
    wobbles the zero crossing and makes jitter. The filter isn't perfect
    so doesn't forget the big negative step in half the sawtooth time.

    So move the comparator trigger level up, to 0.9V instead of zero, and
    that gives the filter almost twice the time to forget.



    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Clifford Heath@21:1/5 to John Larkin on Mon Aug 8 11:53:28 2022
    On 7/8/22 23:55, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has
    A frequency-set register, N=32 or 48 bits or something
    which adds, every clock, to a phase accumulator
    M most-significant bits of that goes into a sine lookup table
    Which clocks D bits into a DAC
    Which drives a lowpass filter and a comparator.

    Why do the sine lookup?


    Common DDS evaluation boards come with a 7th-order filter at about 40%
    of the clock rate, so for a 180MHz AD9851 at 180MHz the filter is around
    72MHz. That produces reasonable signals between 30-70Mhz, but if you
    want to produce 1MHz, the signal turns into a staircase roughly
    following the sine curve. (the 40% is a compromise to allow the filter
    to remove most of the first DDS image, which will be at 60%)

    If they started with a triangle wave (as you can get from a cheap AD9834
    for example) it would still be a staircased triangle - the filter
    softens the staircase steps but doesn't do anything to make the signal
    look like a sine wave. You'd need a different filer for that.

    Clifford Heath

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  • From whit3rd@21:1/5 to John Larkin on Sun Aug 7 19:12:17 2022
    On Sunday, August 7, 2022 at 3:55:46 PM UTC-7, John Larkin wrote:
    On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

    ... My proposed sawtooth has a sharp jump that a sine wave
    doesn't. If the filter has forgotten the jump, the sawtooth is ideal.
    If not, the soft history of a sine wave might be better.

    But, doesn't the 'sharp jump' have synchrony with a clock edge?

    Sure. The dds DAC is clocked by the main clock. Every dac output point
    is clocked.

    A post-filter sinewave's zero crossings are NOT clocked, though, so can be asynchronous.
    The 'filter' has a Q of maybe 100, gives the sinewave's stability a couple of extra
    digits worth of jitter suppression. Such a filter, with a transient rather than a
    single-frequency drive, depends on response over ALL the harmonics that
    make up that slope. Self-resonance of inductors makes the high harmonics
    hard to predict (and other broadband component issues apply to other cases).

    Folk with serious timing issues can use LC filters with superconductors... and regulate the tank temperature with helium boiloff pressure gages.

    --- SoupGate-Win32 v1.05
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  • From Clifford Heath@21:1/5 to John Larkin on Mon Aug 8 12:26:03 2022
    On 8/8/22 05:53, John Larkin wrote:
    On Sun, 7 Aug 2022 21:00:02 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
    wrote:

    Am 07.08.22 um 19:57 schrieb John Larkin:


    My question was, why make a sine wave if the final result is a digital
    clock?

    You can get by with a counter if you are happy with an exact subharmonic
    of the clock source.

    Trying to build a DDS without a sine table is like shooting
    oneself into both feet and then enjoying the feeling as the
    proud winner of the filtering wheelchair championchip.

    What advantage does a sine table have over making a sawtooth directly
    from the MSBs of the phase accumulator? The sine conversion just adds
    errors, seems to me.

    The filter adds back in some of what you would have got by increasing
    the number of MSBs fed to a sine lookup table (and more amplitude steps, maybe).

    Two adjacent zero-crossings will occur at a different time in the filter
    output compared to its input, unless the clock is a harmonic of your
    output frequency.

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  • From Ricky@21:1/5 to John Larkin on Sun Aug 7 21:56:41 2022
    On Sunday, August 7, 2022 at 8:48:17 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 15:36:23 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 3:29:03 PM UTC-7, John Larkin wrote:

    ... My proposed sawtooth has a sharp jump that a sine wave
    doesn't. If the filter has forgotten the jump, the sawtooth is ideal.
    If not, the soft history of a sine wave might be better.

    But, doesn't the 'sharp jump' have synchrony with a clock edge?
    And, doesn't a sharp jump, like a clock, require a big impulse of current out of your filtered
    power supply? The sinewave is cleaner to drive, and less insistent on knowledge
    of dispersion in the dielectric materials. As others have pointed out, >that's why wiring time delays are precise only with sinewaves: no hook there.
    The power supply isn't an issue. All sorts of things are whacking the
    power supply.

    But if we make a sawtooth that ramps from -V to +V, and we filter
    that, the big negative spike happens at the input clock rate, so
    wobbles the zero crossing and makes jitter. The filter isn't perfect
    so doesn't forget the big negative step in half the sawtooth time.

    So move the comparator trigger level up, to 0.9V instead of zero, and
    that gives the filter almost twice the time to forget.

    You don't want the filter to forget. The point of the filter is to integrate the timing, average to put it another way. You want it to remember the zero crossings so as to remove as much jitter as possible. You keep talking like what is important is
    only the careful construction of the current edge of the waveform.

    --

    Rick C.

    ++ Get 1,000 miles of free Supercharging
    ++ Tesla referral code - https://ts.la/richard11209

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  • From Phil Hobbs@21:1/5 to Gerhard Hoffmann on Mon Aug 8 11:10:08 2022
    Gerhard Hoffmann wrote:
    Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

    The essence of the Collins paper is that it takes several
    pairs of (filter + amplifier) in cascade, not a dumb comparator.

    I forgot:

    The filters have to be tighter from stage to stage.
    There is an optimum.
    In the time nuts archives, there is a spreadsheet
    that computes the number of stages, gain per stage
    and bandwidth.

    Gerhard


    I suspect the minimum will vary depending on the criteria. You don't
    gain much by making the filters so narrow that their parametric drifts
    start going all over the place. Lots of things get worse by factors of Q.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

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  • From Mike Monett@21:1/5 to Mike Monett on Mon Aug 8 17:52:24 2022
    Mike Monett <spamme@not.com> wrote:

    [...]

    One problem with high gain limiters is ground bounce. This can cause
    feedback to the input stage that causes effects similar to hysteresis,
    or even oscillations. Many limiters restrict the minimum slew rate, or
    even do not specify the performance in a band around zero. This means
    the circuit cannot be used at low frequencies or even DC.

    It took a while to find the right google-fu, but I finally found an
    example:

    MINIMUM INPUT SLEW RATE REQUIREMENT
    As with many high speed comparators, a minimum slew rate
    requirement must be met to ensure that the device does not
    oscillate as the input signal crosses the threshold. This oscil-
    lation is due in part to the high input bandwidth of the comparator
    and the feedback parasitics inherent in the package. A
    minimum slew rate of 50 V/µs must ensure clean output
    transitions from the ADCMP580/ADCMP581/ADCMP582
    family of comparators.

    https://www.analog.com/media/en/technical-documentation/data-sheets/ADCMP58 0_581_582.pdf

    I believe it was Bruce Griffiths who championed low gain stages driving back-to-back diodes between stages. This would alleviate the ground
    bounce problem and allow slew rates down to DC.




    --
    MRM

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  • From Mike Monett@21:1/5 to Phil Hobbs on Mon Aug 8 17:35:06 2022
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Gerhard Hoffmann wrote:
    Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

    The essence of the Collins paper is that it takes several pairs of
    (filter + amplifier) in cascade, not a dumb comparator.

    I forgot:

    The filters have to be tighter from stage to stage.
    There is an optimum.
    In the time nuts archives, there is a spreadsheet
    that computes the number of stages, gain per stage
    and bandwidth.

    Gerhard


    I suspect the minimum will vary depending on the criteria. You don't
    gain much by making the filters so narrow that their parametric drifts
    start going all over the place. Lots of things get worse by factors of
    Q.

    Cheers

    Phil Hobbs

    I never bought into the Collins theory. A bit of fiddling in LTspice and
    simple pen-and-paper work shows the last stage is all that matters.

    Other attempts to improve on Collins fail in the first paragraphs. For
    example, Attila Kinali assumes the limiter has hysteresis. As far as I
    know, no limiter worth it's salt has hysteresis. See

    http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

    It is referenced in

    https://www.mail-archive.com/time-nuts@lists.febo.com/msg08534.html

    One problem with high gain limiters is ground bounce. This can cause
    feedback to the input stage that causes effects similar to hysteresis, or
    even oscillations. Many limiters restrict the minimum slew rate, or even
    do not specify the performance in a band around zero. This means the
    circuit cannot be used at low frequencies or even DC.

    I believe it was Bruce Griffiths who championed low gain stages driving back-to-back diodes between stages. This would alleviate the ground bounce problem and allow slew rates down to DC.





    --
    MRM

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  • From Phil Hobbs@21:1/5 to Mike Monett on Mon Aug 8 14:14:36 2022
    Mike Monett wrote:
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Gerhard Hoffmann wrote:
    Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

    The essence of the Collins paper is that it takes several pairs of
    (filter + amplifier) in cascade, not a dumb comparator.

    I forgot:

    The filters have to be tighter from stage to stage.
    There is an optimum.
    In the time nuts archives, there is a spreadsheet
    that computes the number of stages, gain per stage
    and bandwidth.

    Gerhard


    I suspect the minimum will vary depending on the criteria. You don't
    gain much by making the filters so narrow that their parametric drifts
    start going all over the place. Lots of things get worse by factors of
    Q.

    Cheers

    Phil Hobbs

    I never bought into the Collins theory. A bit of fiddling in LTspice and simple pen-and-paper work shows the last stage is all that matters.

    Other attempts to improve on Collins fail in the first paragraphs. For example, Attila Kinali assumes the limiter has hysteresis. As far as I
    know, no limiter worth it's salt has hysteresis. See

    http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

    It is referenced in

    https://www.mail-archive.com/time-nuts@lists.febo.com/msg08534.html

    One problem with high gain limiters is ground bounce. This can cause
    feedback to the input stage that causes effects similar to hysteresis, or even oscillations. Many limiters restrict the minimum slew rate, or even
    do not specify the performance in a band around zero. This means the
    circuit cannot be used at low frequencies or even DC.

    I believe it was Bruce Griffiths who championed low gain stages driving back-to-back diodes between stages. This would alleviate the ground bounce problem and allow slew rates down to DC.

    Just using fully differential stages (a la ECL) fixes the ground bounce
    problem pretty well.

    The wideband noise both adds and intermodulates with the desired signal, causing phase noise. In the high-SNR limit, the RMS phase noise
    deviation (rad/sqrt(Hz)) due to additive noise can be found from the small-angle approximation:

    <delta phi> = 1/sqrt(2 * SNR ).

    As long as the intermodulation is small, I agree that the last stage is
    most of what matters, but not 100%.

    Noise intermodulation will shift not just the zero crossings, but also
    the times when the amplifier goes in and out of clipping. The next
    filter will turn that into a zero-crossing shift.


    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

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  • From Phil Hobbs@21:1/5 to Phil Hobbs on Mon Aug 8 14:23:54 2022
    Phil Hobbs wrote:
    Mike Monett wrote:
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Gerhard Hoffmann wrote:
    Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

    The essence of the Collins paper is that it takes several pairs of
    (filter + amplifier) in cascade, not a dumb comparator.

    I forgot:

    The filters have to be tighter from stage to stage.
    There is an optimum.
    In the time nuts archives, there is a spreadsheet
    that computes the number of stages, gain per stage
    and bandwidth.

    Gerhard


    I suspect the minimum will vary depending on the criteria.  You don't
    gain much by making the filters so narrow that their parametric drifts
    start going all over the place.  Lots of things get worse by factors of >>> Q.

    Cheers

    Phil Hobbs

    I never bought into the Collins theory. A bit of fiddling in LTspice and
    simple pen-and-paper work shows the last stage is all that matters.

    Other attempts to improve on Collins fail in the first paragraphs. For
    example, Attila Kinali assumes the limiter has hysteresis. As far as I
    know, no limiter worth it's salt has hysteresis. See

    http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

    It is referenced in

    https://www.mail-archive.com/time-nuts@lists.febo.com/msg08534.html

    One problem with high gain limiters is ground bounce. This can cause
    feedback to the input stage that causes effects similar to hysteresis, or
    even oscillations. Many limiters restrict the minimum slew rate, or even
    do not specify the performance in a band around zero. This means the
    circuit cannot be used at low frequencies or even DC.

    I believe it was Bruce Griffiths who championed low gain stages driving
    back-to-back diodes between stages. This would alleviate the ground
    bounce
    problem and allow slew rates down to DC.

    Just using fully differential stages (a la ECL) fixes the ground bounce problem pretty well.

    The wideband noise both adds and intermodulates with the desired signal, causing phase noise.  In the high-SNR limit, the RMS phase noise
    deviation (rad/sqrt(Hz)) due to additive noise can be found from the small-angle approximation:

    <delta phi> = 1/sqrt(2 * SNR ).

    As long as the intermodulation is small, I agree that the last stage is
    most of what matters, but not 100%.

    Noise intermodulation will shift not just the zero crossings, but also
    the times when the amplifier goes in and out of clipping. The next
    filter will turn that into a zero-crossing shift.

    I should add that it's important that the limiter be fully differential, because otherwise you get a bunch of AM-PM conversion.

    It's also quite feasible to mix down, limit, filter, and mix back up
    again. With ideal mixers, this reduces the limiter's phase noise power
    by a factor

    (f_RF/f_IF)**2.

    The LO doesn't have to be as stable as the desired signal, because its
    phase gets subtracted and then added again.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

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    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to lang...@fonz.dk on Mon Aug 8 13:17:29 2022
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:
    sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >> >not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >> up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine
    value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    --

    Rick C.

    --- Get 1,000 miles of free Supercharging
    --- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to langwadt@fonz.dk on Mon Aug 8 15:02:17 2022
    On Sun, 7 Aug 2022 14:06:02 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital >> >> >> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >> >> >not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a
    trapezoid with a steep rise.

    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    Maybe. But it's worth thinking about. The optimum DDS waveform is
    entangled with the filter response. The sawtooth is interesting. It
    could be Spiced, in some number of hours. Or days.

    We can design the schematic and do a board layout and futz with DDS
    shapes and filters and dividers later.


    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.

    but if the DAC can't run any faster or have any more bits, how?

    It would run at the XO rate of course, but one might generate a very
    slow trigger rate by doing something smarter that generating a very
    slow sine wave. A 1 Hz synthesized sine wave, filtered and stuffed
    into a comparator, is going to have a lot of jitter.

    Just thinking. That's often not popular.


    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

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  • From Mike Monett@21:1/5 to Phil Hobbs on Tue Aug 9 00:36:49 2022
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Phil Hobbs wrote:

    [...]

    Just using fully differential stages (a la ECL) fixes the ground bounce
    problem pretty well.

    I should add that it's important that the limiter be fully differential, because otherwise you get a bunch of AM-PM conversion.

    ECL helps as long as both outputs are equally loaded. For example, higher capacitance on one output can introduce switching transients. However, it
    is difficult to find differential sources. Double balanced mixers and XOR
    gates are single-ended. If you are trying to achieve high gain, small
    effects can add up.

    It's also quite feasible to mix down, limit, filter, and mix back up
    again. With ideal mixers, this reduces the limiter's phase noise power
    by a factor

    (f_RF/f_IF)**2.

    The LO doesn't have to be as stable as the desired signal, because its
    phase gets subtracted and then added again.

    I'm not so sure about cancellation. The propagation delay through the
    filter will change the phase. The group delay around cutoff of a
    butterworth filter can have enormous phase shift. High frequencies may even
    add instead of subtract.

    Cheers

    Phil Hobbs




    --
    MRM

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  • From Phil Hobbs@21:1/5 to Mike Monett on Mon Aug 8 20:44:00 2022
    Mike Monett wrote:
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Phil Hobbs wrote:

    [...]

    Just using fully differential stages (a la ECL) fixes the ground bounce
    problem pretty well.

    I should add that it's important that the limiter be fully differential,
    because otherwise you get a bunch of AM-PM conversion.

    ECL helps as long as both outputs are equally loaded. For example, higher capacitance on one output can introduce switching transients. However, it
    is difficult to find differential sources. Double balanced mixers and XOR gates are single-ended. If you are trying to achieve high gain, small
    effects can add up.

    It's also quite feasible to mix down, limit, filter, and mix back up
    again. With ideal mixers, this reduces the limiter's phase noise power
    by a factor

    (f_RF/f_IF)**2.

    The LO doesn't have to be as stable as the desired signal, because its
    phase gets subtracted and then added again.

    I'm not so sure about cancellation. The propagation delay through the
    filter will change the phase. The group delay around cutoff of a
    butterworth filter can have enormous phase shift. High frequencies may even add instead of subtract.


    The filter phase stays reasonably still, though, so the LO phase
    fluctuations remain highly coherent between the down- and
    up-conversions. 'T'ain't perfect, but it can really help sometimes.

    Cheers

    Phil Hobbs


    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Mike Monett@21:1/5 to Phil Hobbs on Tue Aug 9 01:06:01 2022
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Mike Monett wrote:

    [...]

    I believe it was Bruce Griffiths who championed low gain stages driving
    back-to-back diodes between stages. This would alleviate the ground
    bounce problem and allow slew rates down to DC.

    The wideband noise both adds and intermodulates with the desired signal, causing phase noise. In the high-SNR limit, the RMS phase noise
    deviation (rad/sqrt(Hz)) due to additive noise can be found from the small-angle approximation:

    <delta phi> = 1/sqrt(2 * SNR ).

    As long as the intermodulation is small, I agree that the last stage is
    most of what matters, but not 100%.

    Noise intermodulation will shift not just the zero crossings, but also
    the times when the amplifier goes in and out of clipping. The next
    filter will turn that into a zero-crossing shift.

    I'm not sure I understand what you mean. The noise is symmetrical. It can
    add jitter to the zero crossings, but that's what noise does. You show this
    in your equation.

    In the Griffiths approach, the limiting is done by back-to-back diodes.

    There is no amplifier going in and out of clipping, so it's not clear how
    there can be a shift in the zero crossing.



    Cheers

    Phil Hobbs




    --
    MRM

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  • From Anthony William Sloman@21:1/5 to Mike Monett on Mon Aug 8 18:01:58 2022
    On Tuesday, August 9, 2022 at 10:36:56 AM UTC+10, Mike Monett wrote:
    Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

    Phil Hobbs wrote:

    [...]
    Just using fully differential stages (a la ECL) fixes the ground bounce >> problem pretty well.
    I should add that it's important that the limiter be fully differential, because otherwise you get a bunch of AM-PM conversion.
    ECL helps as long as both outputs are equally loaded. For example, higher capacitance on one output can introduce switching transients. However, it
    is difficult to find differential sources. Double balanced mixers and XOR gates are single-ended. If you are trying to achieve high gain, small effects can add up.
    It's also quite feasible to mix down, limit, filter, and mix back up again. With ideal mixers, this reduces the limiter's phase noise power
    by a factor

    (f_RF/f_IF)**2.

    The LO doesn't have to be as stable as the desired signal, because its phase gets subtracted and then added again.

    I'm not so sure about cancellation. The propagation delay through the
    filter will change the phase. The group delay around cutoff of a
    butterworth filter can have enormous phase shift. High frequencies may even add instead of subtract.

    So you don't use a Butterworth filter, but a Bessel linear phase shift filter, or one of the variations on that that comes close enough. Finite impulse response filters (built around a tapped delay line) can be linear phase. A filter design handbook -
    Williams and Taylor is well thought of - can be helpful.

    https://www.google.com.au/books/edition/Electronic_Filter_Design_Handbook_Fourth/2CBGAQAAIAAJ?hl=en

    --
    Bill Sloman, Sydney

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  • From Phil Hobbs@21:1/5 to Mike Monett on Mon Aug 8 21:08:56 2022
    Mike Monett wrote:
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Phil Hobbs wrote:

    [...]

    Just using fully differential stages (a la ECL) fixes the ground bounce
    problem pretty well.

    I should add that it's important that the limiter be fully differential,
    because otherwise you get a bunch of AM-PM conversion.

    ECL helps as long as both outputs are equally loaded. For example, higher capacitance on one output can introduce switching transients. However, it
    is difficult to find differential sources. Double balanced mixers and XOR gates are single-ended. If you are trying to achieve high gain, small
    effects can add up.

    Single-ended XOR gates are single-ended, but DBMs aren't necessarily.
    The RF and LO ports are both transformer-coupled, so you can drive them differentially with no issues. Even the LO port can be driven
    differentially for the upconversion.

    <snip stuff I commented on already>

    Cheers

    Phil Hobbs


    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

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  • From Phil Hobbs@21:1/5 to Mike Monett on Mon Aug 8 21:26:20 2022
    Mike Monett wrote:
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    <snippage restored>
    Gerhard Hoffmann wrote:
    Am 07.08.22 um 22:37 schrieb Gerhard Hoffmann:

    The essence of the Collins paper is that it takes several pairs of
    (filter + amplifier) in cascade, not a dumb comparator.

    I forgot:

    The filters have to be tighter from stage to stage.
    There is an optimum.
    In the time nuts archives, there is a spreadsheet
    that computes the number of stages, gain per stage
    and bandwidth.

    Gerhard


    I suspect the minimum will vary depending on the criteria. You don't
    gain much by making the filters so narrow that their parametric drifts
    start going all over the place. Lots of things get worse by factors of
    Q.

    Cheers

    Phil Hobbs

    I never bought into the Collins theory. A bit of fiddling in LTspice and simple pen-and-paper work shows the last stage is all that matters.

    Other attempts to improve on Collins fail in the first paragraphs. For example, Attila Kinali assumes the limiter has hysteresis. As far as I
    know, no limiter worth it's salt has hysteresis. See

    http://people.mpi-inf.mpg.de/~adogan/pubs/IFCS2018_comparator_noise.pdf

    It is referenced in

    https://www.mail-archive.com/time-nuts@lists.febo.com/msg08534.html

    One problem with high gain limiters is ground bounce. This can cause
    feedback to the input stage that causes effects similar to hysteresis, or even oscillations. Many limiters restrict the minimum slew rate, or even
    do not specify the performance in a band around zero. This means the
    circuit cannot be used at low frequencies or even DC.

    I believe it was Bruce Griffiths who championed low gain stages driving back-to-back diodes between stages. This would alleviate the ground bounce problem and allow slew rates down to DC.


    Phil Hobbs wrote:

    [...]

    Just using fully differential stages (a la ECL) fixes the ground
    bounce problem pretty well.

    I should add that it's important that the limiter be fully
    differential, because otherwise you get a bunch of AM-PM
    conversion.

    ECL helps as long as both outputs are equally loaded. For example,
    higher capacitance on one output can introduce switching transients.
    However, it is difficult to find differential sources. Double
    balanced mixers and XOR gates are single-ended. If you are trying to
    achieve high gain, small effects can add up.

    Single-ended XOR gates are single-ended, but DBMs aren't
    necessarily. The RF and LO ports are both transformer-coupled, so
    you can drive them differentially with no issues. Even the LO port
    can be driven differentially for the upconversion.

    Yes, the RF and LO ports are both transformer-coupled. So what
    difference does it make if these ports are driven single-ended vs differential? How does the transformer know how the input is driven?

    That's the point. You claimed that DBMs were single-ended, and they
    aren't necessarily. So the fully differential approach is a good
    solution to the supply/ground coupling problem.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

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  • From Phil Hobbs@21:1/5 to Mike Monett on Mon Aug 8 21:18:27 2022
    Mike Monett wrote:
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Mike Monett wrote:

    [...]

    I believe it was Bruce Griffiths who championed low gain stages driving
    back-to-back diodes between stages. This would alleviate the ground
    bounce problem and allow slew rates down to DC.

    The wideband noise both adds and intermodulates with the desired signal,
    causing phase noise. In the high-SNR limit, the RMS phase noise
    deviation (rad/sqrt(Hz)) due to additive noise can be found from the
    small-angle approximation:

    <delta phi> = 1/sqrt(2 * SNR ).

    As long as the intermodulation is small, I agree that the last stage is
    most of what matters, but not 100%.

    Noise intermodulation will shift not just the zero crossings, but also
    the times when the amplifier goes in and out of clipping. The next
    filter will turn that into a zero-crossing shift.

    I'm not sure I understand what you mean. The noise is symmetrical. It can
    add jitter to the zero crossings, but that's what noise does. You show this in your equation.

    It adds jitter to everything, including the time when the amplifier goes
    in and out of clipping. The filter applies a convolution to the entire waveform, not just the zero-crossings, so that shift is equally important.


    In the Griffiths approach, the limiting is done by back-to-back diodes.

    There is no amplifier going in and out of clipping, so it's not clear how there can be a shift in the zero crossing.

    The additive noise does the shifting, even if the rest of the hardware
    is noiseless. Diodes are not noiseless devices either.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

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  • From Mike Monett@21:1/5 to Phil Hobbs on Tue Aug 9 01:18:45 2022
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    [...]

    Single-ended XOR gates are single-ended, but DBMs aren't necessarily.
    The RF and LO ports are both transformer-coupled, so you can drive them differentially with no issues. Even the LO port can be driven
    differentially for the upconversion.

    Yes, the RF and LO ports are both transformer-coupled. So what difference
    does it make if these ports are driven single-ended vs differential? How does the transformer know how the input is driven?

    Cheers

    Phil Hobbs





    --
    MRM

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  • From Clifford Heath@21:1/5 to Mike Monett on Tue Aug 9 12:55:15 2022
    On 9/8/22 11:18, Mike Monett wrote:
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    [...]

    Single-ended XOR gates are single-ended, but DBMs aren't necessarily.
    The RF and LO ports are both transformer-coupled, so you can drive them
    differentially with no issues. Even the LO port can be driven
    differentially for the upconversion.

    Yes, the RF and LO ports are both transformer-coupled. So what difference does it make if these ports are driven single-ended vs differential? How does the transformer know how the input is driven?

    Capacitive coupling? Transformers aren't perfect.

    And single-ended drive means the drive current goes into the local
    ground plane and spreads from there to whatever decoupling there is,
    leaving a visible signal across ground plane inductance and resistance.

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  • From Mike Monett@21:1/5 to Clifford Heath on Wed Aug 10 05:19:49 2022
    Clifford Heath <no_spam@please.net> wrote:

    On 9/8/22 11:18, Mike Monett wrote:
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    [...]

    Single-ended XOR gates are single-ended, but DBMs aren't necessarily.
    The RF and LO ports are both transformer-coupled, so you can drive
    them differentially with no issues. Even the LO port can be driven
    differentially for the upconversion.

    Yes, the RF and LO ports are both transformer-coupled. So what
    difference does it make if these ports are driven single-ended vs
    differential? How does the transformer know how the input is driven?

    Capacitive coupling? Transformers aren't perfect.

    And single-ended drive means the drive current goes into the local
    ground plane and spreads from there to whatever decoupling there is,
    leaving a visible signal across ground plane inductance and resistance.

    Yes. This is why I put noisy and sensitive circuits on their own ground
    plane, separated from the main ground plane.

    Signals in and out are differential whenever possible, and ground
    connections between the planes are chosen to minimise crosstalk.

    A number of oscilloscopes, such as Rigol, do the same thing.



    --
    MRM

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  • From Martin Brown@21:1/5 to Ricky on Wed Aug 10 09:50:48 2022
    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:
    sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>
    My question was, why make a sine wave if the final result is a digital >>>>>>> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a
    trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice
    so far then one of the cheap and nasty Chinese DDS signal generators
    that has a user defined waveform lookup table would be the way to go.

    Nothing refutes a daft idea so effectively as practical experiment.

    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default.

    I suppose triangle wave and diode shaping to a sine wave would be an
    option (HP once used it to very good effect and their patent for that
    network has probably long since expired by now). ICL8038 did a crude
    imitation of the same trick in their monolithic function generator chip.

    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in
    the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the
    harmonics generated by the discrete steps in the DAC waveform.

    --
    Regards,
    Martin Brown

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  • From Ricky@21:1/5 to Martin Brown on Wed Aug 10 03:27:51 2022
    On Wednesday, August 10, 2022 at 4:50:56 AM UTC-4, Martin Brown wrote:
    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:
    sųndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a
    trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include >>> some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.
    If he wants to waste his time on this after ignoring all the good advice
    so far then one of the cheap and nasty Chinese DDS signal generators
    that has a user defined waveform lookup table would be the way to go.

    Nothing refutes a daft idea so effectively as practical experiment.

    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default.

    I suppose triangle wave and diode shaping to a sine wave would be an
    option (HP once used it to very good effect and their patent for that network has probably long since expired by now). ICL8038 did a crude imitation of the same trick in their monolithic function generator chip.

    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the sine
    value/DAC resolution.

    Anyone who wishes to research DDS design will find this.
    The low pass filter needs to be frequency matched to the artefacts in
    the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the harmonics generated by the discrete steps in the DAC waveform.

    A 1 MHz filter would be appropriate if the sample rate is well above 1 MSPS. But the resolution of the DAC needs to also support such a wide range of frequencies. If he only needs a low frequency output, then this is not a good solution. But he seems
    to be saying he needs the wide frequency range. In that case, it would seem obvious that multiple filters would useful. Just like they don't build radios to cover all bands without separate band select filters, there will not be a one size fits all
    solution here. Most of the ideas he has talked about will impact the jitter requirements. Unless he addresses the phase accumulator truncation, he's never going to get really good jitter, no matter how good the filtering is.

    I don't recall the impact on jitter for a given resolution, but I found a reasonable phase truncation was 18 bits with an 18 bit sine table output. To improve beyond that with reasonable hardware (reasonable for my designs) requires sine approximation
    methods. But for his work, it would seem a CORDIC might be the right way to go. Add dithering to a few extra bits of sine with rounding, perhaps.

    --

    Rick C.

    --+ Get 1,000 miles of free Supercharging
    --+ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to '''newspam'''@nonad.co.uk on Wed Aug 10 07:47:05 2022
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>
    My question was, why make a sine wave if the final result is a digital >>>>>>>> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a
    trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter. >>

    The DAC lsb increments rarely at low frequencies, so magically include >>>> some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice
    so far then one of the cheap and nasty Chinese DDS signal generators
    that has a user defined waveform lookup table would be the way to go.

    Thinking about possibilities is never a waste of time. It may lead to
    something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default.

    I suppose triangle wave and diode shaping to a sine wave would be an
    option (HP once used it to very good effect and their patent for that
    network has probably long since expired by now). ICL8038 did a crude >imitation of the same trick in their monolithic function generator chip.

    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in
    the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the >harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.
    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

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  • From whit3rd@21:1/5 to John Larkin on Wed Aug 10 11:50:17 2022
    On Wednesday, August 10, 2022 at 7:47:20 AM UTC-7, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.

    Oh, the refutation of an idea by an application of theory is just as effective as experiment, and multiple refutations of both sort have entered the discussion.

    There are no 'idea shooters' more useless than those who keep up
    a chorus of 'why not' and ignore the sensible answers.

    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in >gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default.

    Yes, that's a good analysis. Transient analysis might tell you what a
    filter gives for a triangle wave or sawtooth, but the sinewave analysis
    of filter operation is much easier, and supports useful conclusions.

    It's useful; use it.

    --- SoupGate-Win32 v1.05
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  • From upsidedown@downunder.com@21:1/5 to gnuarm.deletethisbit@gmail.com on Wed Aug 10 22:37:09 2022
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.deletethisbit@gmail.com> wrote:

    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide
    noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or
    amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.

    --- SoupGate-Win32 v1.05
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  • From Lasse Langwadt Christensen@21:1/5 to All on Wed Aug 10 13:22:13 2022
    onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin:

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly insisting on making a slow sine into the filter+comparator. At high frequencies, the unfiltered MSB is a horror.


    ahh now I see what are on about, at very low frequencies
    the fixed jitter of a Fclk cycle could be better than
    a comparator trying to digitize a (noisy) slow rising sine

    maybe a frequency dependent gain and clamp to maintain a constant slew-rate could work

    --- SoupGate-Win32 v1.05
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  • From John Larkin@21:1/5 to langwadt@fonz.dk on Wed Aug 10 14:15:42 2022
    On Wed, 10 Aug 2022 13:22:13 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin:

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.


    ahh now I see what are on about, at very low frequencies
    the fixed jitter of a Fclk cycle could be better than
    a comparator trying to digitize a (noisy) slow rising sine

    maybe a frequency dependent gain and clamp to maintain a constant slew-rate could work

    The MSB of the phase accumulator has jitter of one clock p-p. The RMS
    jitter of that is 1 clock period / sqrt(12). That could be a few ns
    RMS jitter at mHz frequencies.

    I was just thinking about possible tricks to reduce DDS period jitter
    at low frequencies, without the obvious post-comparator divisor.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Wed Aug 10 15:03:20 2022
    onsdag den 10. august 2022 kl. 23.15.59 UTC+2 skrev John Larkin:
    On Wed, 10 Aug 2022 13:22:13 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin:

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.


    ahh now I see what are on about, at very low frequencies
    the fixed jitter of a Fclk cycle could be better than
    a comparator trying to digitize a (noisy) slow rising sine

    maybe a frequency dependent gain and clamp to maintain a constant slew-rate could work
    The MSB of the phase accumulator has jitter of one clock p-p. The RMS
    jitter of that is 1 clock period / sqrt(12). That could be a few ns
    RMS jitter at mHz frequencies.

    I was just thinking about possible tricks to reduce DDS period jitter
    at low frequencies, without the obvious post-comparator divisor.

    The sine and filter does that. Draw a line between the data points and see
    that the zero crossing doesn't fall on a clock edge

    but it might help to gain up the sine to increase the slew rate so it doesn't hang around the comparator threshold forever, when all it has to do is delay
    a variable +/-1 cycle

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  • From John Larkin@21:1/5 to langwadt@fonz.dk on Wed Aug 10 15:18:21 2022
    On Wed, 10 Aug 2022 15:03:20 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    onsdag den 10. august 2022 kl. 23.15.59 UTC+2 skrev John Larkin:
    On Wed, 10 Aug 2022 13:22:13 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    onsdag den 10. august 2022 kl. 16.47.20 UTC+2 skrev John Larkin:

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.


    ahh now I see what are on about, at very low frequencies
    the fixed jitter of a Fclk cycle could be better than
    a comparator trying to digitize a (noisy) slow rising sine

    maybe a frequency dependent gain and clamp to maintain a constant slew-rate could work
    The MSB of the phase accumulator has jitter of one clock p-p. The RMS
    jitter of that is 1 clock period / sqrt(12). That could be a few ns
    RMS jitter at mHz frequencies.

    I was just thinking about possible tricks to reduce DDS period jitter
    at low frequencies, without the obvious post-comparator divisor.

    The sine and filter does that. Draw a line between the data points and see >that the zero crossing doesn't fall on a clock edge

    Obviously, the filter is there to interpolate between DAC clocks. But
    it doesn't at low frequencies.

    At, say, 1 Hz, the dac increments infrequently and comparator noise
    becomes a serious jitter source. Even comparators have 1/f noise.


    but it might help to gain up the sine to increase the slew rate so it doesn't >hang around the comparator threshold forever, when all it has to do is delay >a variable +/-1 cycle

    Or maybe something even better.


    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to upsid...@downunder.com on Wed Aug 10 15:42:00 2022
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital >> >> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >> >not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide
    noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.

    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is
    a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he
    is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for
    the different ranges of clock output rates.

    Don't you agree?

    --

    Rick C.

    -+- Get 1,000 miles of free Supercharging
    -+- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Wed Aug 10 16:37:28 2022
    torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >> >not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >> up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide
    noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this is
    a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he
    is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters for
    the different ranges of clock output rates.

    Don't you agree?

    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just jitter
    on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate



    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From bitrex@21:1/5 to John Larkin on Wed Aug 10 21:08:48 2022
    On 8/7/2022 1:53 PM, John Larkin wrote:
    On Sun, 7 Aug 2022 10:11:44 -0700 (PDT), whit3rd <whit3rd@gmail.com>
    wrote:

    On Sunday, August 7, 2022 at 9:08:13 AM UTC-7, John Larkin wrote:
    On Sun, 7 Aug 2022 08:23:49 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 6:55:32 AM UTC-7, John Larkin wrote:
    To make a programmable-frequency clock, the usual DDS chip has
    ...
    M most-significant bits of that goes into a sine lookup table

    The sine lookup minimizes the difference function, which is the target of >>>> the (analog) lowpass filter. That makes it a kind of digital filter doing the
    bulk of the work.

    The positive zero crossing of a sine wave and a triangle look a lot
    alike, a straight line within the attention span of the lowpass
    filter. It can't remember enough long-ago to tell the difference.

    But one wouldn't use the zero crossing (adds voltage offset error
    to the timing signal) when a trangle wave has a nice crisp
    cusp to define a timing.

    The point of the DDS lowpass filter is to interpolate multiple samples
    and reduce jitter. If we use sharp edges on the waveform, the filter
    just delays but doesn't reduce jitter. May as well use the phase
    accumulator MSB.

    A sawtooth has a nice long straight line rising edge. The filter will
    love that.




    We don't push the Nyquist rate, which needs an ideal lowpass filter.
    In fact, the sawtooth looks better to me... there is more linear
    history before the zero cross than a sine.

    Other than synchronization possibilities, the triangle-wave basis hasn't an
    advantage to speak of.

    No sine lookup table and no error contributions from that.

    But, the triangle wave, for a given amplitude, has lower slew rate (lower
    V signal at delta-T from the zero) than a sine wave. So, lower signal/noise.


    If D MSBs of the phase accumulator are pushed into the DAC, we get a
    sawtooth that goes rail-to-rail in one DDS cycle. Nice. We conjecture
    that some digital tricks could do even better, make a steeper
    waveform, especially at low frequencies.

    It's a clock. We don't want to filter out harmonics. Who designs
    digital clocks with low harmonic content?

    A 'digital clock' would usually be square-wave, neither triangle or sine.

    Exactly. Synchronous harmonics add no period jitter. But we want to
    make the square clock *after* the analog filter does its Shannon
    thing.

    The sawtooth defined by the MSBs of the phase accumulator isn't
    intrinsically band-limited but you know you can generate band-limited
    sawtooths directly in software, yeah? You just integrate a band-limited
    impulse train.

    see e.g.

    <https://www.dafx.de/paper-archive/2008/papers/dafx08_05.pdf>

    --- SoupGate-Win32 v1.05
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  • From Ricky@21:1/5 to lang...@fonz.dk on Wed Aug 10 20:19:36 2022
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
    torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >> >
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >> incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or amplitude modulators built in, so the PM/AM inputs can be used to control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if he
    is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters
    for the different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just
    jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate

    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge
    rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO
    truncation.

    Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not
    betting on it.

    --

    Rick C.

    -++ Get 1,000 miles of free Supercharging
    -++ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Klaus Vestergaard Kragelund@21:1/5 to John Larkin on Thu Aug 11 10:13:10 2022
    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a
    trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter. >>>

    The DAC lsb increments rarely at low frequencies, so magically include >>>>> some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice
    so far then one of the cheap and nasty Chinese DDS signal generators
    that has a user defined waveform lookup table would be the way to go.

    Thinking about possibilities is never a waste of time. It may lead to something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default.

    I suppose triangle wave and diode shaping to a sine wave would be an
    option (HP once used it to very good effect and their patent for that
    network has probably long since expired by now). ICL8038 did a crude
    imitation of the same trick in their monolithic function generator chip.

    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in
    the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the
    harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly insisting on making a slow sine into the filter+comparator. At high frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.

    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?

    --- SoupGate-Win32 v1.05
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  • From Ricky@21:1/5 to Klaus Kragelund on Thu Aug 11 02:17:18 2022
    On Thursday, August 11, 2022 at 4:13:20 AM UTC-4, Klaus Kragelund wrote:
    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>
    I want a programmable internal trigger rate for a pulse generator. >>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>> increase the zero-cross slope. The logical end of that is to make a >>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include >>>>> some lower phase accumulator bits to effectively increase the DAC >>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice >> so far then one of the cheap and nasty Chinese DDS signal generators
    that has a user defined waveform lookup table would be the way to go.

    Thinking about possibilities is never a waste of time. It may lead to something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default.

    I suppose triangle wave and diode shaping to a sine wave would be an
    option (HP once used it to very good effect and their patent for that
    network has probably long since expired by now). ICL8038 did a crude
    imitation of the same trick in their monolithic function generator chip. >>>
    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in
    the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the
    harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly insisting on making a slow sine into the filter+comparator. At high frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.
    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?

    The concept of the DDS is to generate a sine wave, which would have some artifacts which could be smoothed by filtering, then a comparator would produce the square wave clock from the sine. This would allow very high resolution of timing, much finer
    than a cycle of the sample rate clock of the DAC.

    However... when producing a sine wave that is much slower than the sample rate clock, the limited resolution of the sine value produces what is essentially a much slower sample rate and the filter doesn't work as well. This can be mitigated by using
    different filters to suit the output sine wave frequency.

    --

    Rick C.

    +-- Get 1,000 miles of free Supercharging
    +-- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Anthony William Sloman@21:1/5 to Klaus Kragelund on Thu Aug 11 04:10:14 2022
    On Thursday, August 11, 2022 at 6:13:20 PM UTC+10, Klaus Kragelund wrote:
    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    <snip>

    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?

    I think the point is that John Larkin wants to generate an infinite number of arbitary frequencies, and can't afford to limit himself to dividing down even a very high frequency clock by a fixed divisor.

    A DDS offers the option of using a DAC to interpolate between fixed divisors. The DAC produces a stair-case waveform approximating to a sine wave, so you have to low pass filter the DAC output so that the zero-crossings do happen between clock edges to
    get the effect you want.

    John doesn't seem to have thought this through.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Klaus Vestergaard Kragelund@21:1/5 to Ricky on Thu Aug 11 16:27:54 2022
    On 11/08/2022 11.17, Ricky wrote:
    On Thursday, August 11, 2022 at 4:13:20 AM UTC-4, Klaus Kragelund wrote:
    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>
    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include >>>>>>> some lower phase accumulator bits to effectively increase the DAC >>>>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice >>>> so far then one of the cheap and nasty Chinese DDS signal generators
    that has a user defined waveform lookup table would be the way to go.

    Thinking about possibilities is never a waste of time. It may lead to
    something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default. >>>>
    I suppose triangle wave and diode shaping to a sine wave would be an
    option (HP once used it to very good effect and their patent for that
    network has probably long since expired by now). ICL8038 did a crude
    imitation of the same trick in their monolithic function generator chip. >>>>>
    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in
    the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the
    harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.
    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?

    The concept of the DDS is to generate a sine wave, which would have some artifacts which could be smoothed by filtering, then a comparator would produce the square wave clock from the sine. This would allow very high resolution of timing, much finer
    than a cycle of the sample rate clock of the DAC.


    Ok, makes good sense. Thanks for the explanation. One could use
    delaylines to get sub cycle resolution, but I guess he must have
    discarded that solution

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to klauskvik@hotmail.com on Thu Aug 11 07:35:14 2022
    On Thu, 11 Aug 2022 10:13:10 +0200, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:

    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to
    increase the zero-cross slope. The logical end of that is to make a >>>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter. >>>>

    The DAC lsb increments rarely at low frequencies, so magically include >>>>>> some lower phase accumulator bits to effectively increase the DAC
    sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice >>> so far then one of the cheap and nasty Chinese DDS signal generators
    that has a user defined waveform lookup table would be the way to go.

    Thinking about possibilities is never a waste of time. It may lead to
    something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default.

    I suppose triangle wave and diode shaping to a sine wave would be an
    option (HP once used it to very good effect and their patent for that
    network has probably long since expired by now). ICL8038 did a crude
    imitation of the same trick in their monolithic function generator chip. >>>>
    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in
    the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the
    harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.

    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    How would that work?


    Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?


    We want a user to be able to program a trigger rate from 15 MHz down
    to milliHz with high resolution and low period jitter. 1 mHz
    resolution is a reasonable goal. We can do that on some instruments
    now, but

    1. If we do classic DDS, phase accumulator and sine lookup table and
    DAC and lowpass filter and comparator, jitter is horrible at low
    frequencies.

    2. If we synthesize an octave or so and divide down after the
    comparator, jitter is good but there can be ugly transients when the
    user changes frequency: the DDS and the divisor both need to be
    changed, and that's tricky using a commercial DDS chip that's slow to reprogram.

    Even the divisor is difficult if it's in an FPGA that has other stuff
    going on. Getting picosecond timing out of an FPGA has hazards, like
    crosstalk, ground bounce, and supply voltage sensitivity, which we
    measure in microvolts per picosecond.


    So, I'm thinking about DDS clock synthesis from basics, and
    particularly thinking in time domain. It's basically a time domain
    problem, so there's nothing magic about sine waves.

    This box does internal clock rate generation to mHz resolution, with
    an RF synthesizer (not a DDS) and post-dividers.

    http://www.highlandtechnology.com/DSS/P500DS.shtml

    but it takes a long time to reprogram the synth (lots of math) so we
    stop triggering while we reprogram. Some customers don't like that;
    their lasers blow up or something.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Klaus Vestergaard Kragelund@21:1/5 to John Larkin on Thu Aug 11 16:51:33 2022
    On 11/08/2022 16.35, John Larkin wrote:
    On Thu, 11 Aug 2022 10:13:10 +0200, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:

    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin:
    On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>
    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include >>>>>>> some lower phase accumulator bits to effectively increase the DAC >>>>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice >>>> so far then one of the cheap and nasty Chinese DDS signal generators
    that has a user defined waveform lookup table would be the way to go.

    Thinking about possibilities is never a waste of time. It may lead to
    something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form

    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima).
    There is a very good reason why people generate sine waves by default. >>>>
    I suppose triangle wave and diode shaping to a sine wave would be an
    option (HP once used it to very good effect and their patent for that
    network has probably long since expired by now). ICL8038 did a crude
    imitation of the same trick in their monolithic function generator chip. >>>>>
    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in
    the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the
    harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.

    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    How would that work?



    A precision clock, high frequency low jitter

    Feeding into the FPGA with say 64bit counter, adding delay line for sub
    clock cycle accuracy

    Compare and lookup on that counter, coupled to the delay line also

    Like standard PWM done in microcontroller timer

    Programming is cycle to cycle, changing just the compare capture word

    Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?


    We want a user to be able to program a trigger rate from 15 MHz down
    to milliHz with high resolution and low period jitter. 1 mHz
    resolution is a reasonable goal. We can do that on some instruments
    now, but

    1. If we do classic DDS, phase accumulator and sine lookup table and
    DAC and lowpass filter and comparator, jitter is horrible at low
    frequencies.

    2. If we synthesize an octave or so and divide down after the
    comparator, jitter is good but there can be ugly transients when the
    user changes frequency: the DDS and the divisor both need to be
    changed, and that's tricky using a commercial DDS chip that's slow to reprogram.

    Even the divisor is difficult if it's in an FPGA that has other stuff
    going on. Getting picosecond timing out of an FPGA has hazards, like crosstalk, ground bounce, and supply voltage sensitivity, which we
    measure in microvolts per picosecond.



    Hazards can be dealt with the correct counter type, right?

    Can you calibrate the FPGA?

    Compare capture with delay line is purly digital, so should have no PDN
    issues pass through

    So, I'm thinking about DDS clock synthesis from basics, and
    particularly thinking in time domain. It's basically a time domain
    problem, so there's nothing magic about sine waves.

    This box does internal clock rate generation to mHz resolution, with
    an RF synthesizer (not a DDS) and post-dividers.

    http://www.highlandtechnology.com/DSS/P500DS.shtml

    but it takes a long time to reprogram the synth (lots of math) so we
    stop triggering while we reprogram. Some customers don't like that;
    their lasers blow up or something.


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to Klaus Kragelund on Thu Aug 11 08:14:21 2022
    On Thursday, August 11, 2022 at 10:51:39 AM UTC-4, Klaus Kragelund wrote:
    On 11/08/2022 16.35, John Larkin wrote:
    On Thu, 11 Aug 2022 10:13:10 +0200, Klaus Vestergaard Kragelund <klau...@hotmail.com> wrote:

    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>
    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC >>>>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice
    so far then one of the cheap and nasty Chinese DDS signal generators >>>> that has a user defined waveform lookup table would be the way to go. >>>
    Thinking about possibilities is never a waste of time. It may lead to >>> something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in >>>> gradient at zero crossing are parabolic or more generally of the form >>>>
    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >>>> There is a very good reason why people generate sine waves by default. >>>>
    I suppose triangle wave and diode shaping to a sine wave would be an >>>> option (HP once used it to very good effect and their patent for that >>>> network has probably long since expired by now). ICL8038 did a crude >>>> imitation of the same trick in their monolithic function generator chip.

    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in >>>> the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the >>>> harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample >>> rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.

    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    How would that work?


    A precision clock, high frequency low jitter

    Feeding into the FPGA with say 64bit counter, adding delay line for sub clock cycle accuracy

    Compare and lookup on that counter, coupled to the delay line also

    Like standard PWM done in microcontroller timer

    Programming is cycle to cycle, changing just the compare capture word

    This is not good for the fast clock rates, not sufficient resolution of the clock rate.

    An NCO can be used directly for the slow clocking, since a clock cycle jitter is good enough. At faster clock rates, the sine lookup is added to the signal path with the attendant DAC and filtering. Actually, no reason to change the signal path in the
    two modes. The DAC will provide consistent drive and timing of the generated signal across the range. The filter will have nearly no impact on the slow clock.

    Or... keep the same concept at all clock speeds and simply use different filters for different ranges. larkin keeps talking about how multiple samples go by with no change in the DAC value, but that's not actually a problem as long as the filter smooths
    the steps, same issue at any clock speed.


    Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter?


    We want a user to be able to program a trigger rate from 15 MHz down
    to milliHz with high resolution and low period jitter. 1 mHz
    resolution is a reasonable goal. We can do that on some instruments
    now, but

    1. If we do classic DDS, phase accumulator and sine lookup table and
    DAC and lowpass filter and comparator, jitter is horrible at low frequencies.

    2. If we synthesize an octave or so and divide down after the
    comparator, jitter is good but there can be ugly transients when the
    user changes frequency: the DDS and the divisor both need to be
    changed, and that's tricky using a commercial DDS chip that's slow to reprogram.

    Even the divisor is difficult if it's in an FPGA that has other stuff going on. Getting picosecond timing out of an FPGA has hazards, like crosstalk, ground bounce, and supply voltage sensitivity, which we
    measure in microvolts per picosecond.


    Hazards can be dealt with the correct counter type, right?

    A hazard is a design failure. Use designers who know what they are doing. Crosstalk is not a significant issue with digital logic, again, as long as the designer is competent. Same for ground bounce, etc.

    All timing issues with digital signals can be resolved by reclocking through your favorite FF outside of the FPGA. That can be as good as a DAC.

    --

    Rick C.

    +-+ Get 1,000 miles of free Supercharging
    +-+ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to klauskvik@hotmail.com on Thu Aug 11 08:54:19 2022
    On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:

    On 11/08/2022 16.35, John Larkin wrote:
    On Thu, 11 Aug 2022 10:13:10 +0200, Klaus Vestergaard Kragelund
    <klauskvik@hotmail.com> wrote:

    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>>
    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include >>>>>>>> some lower phase accumulator bits to effectively increase the DAC >>>>>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice >>>>> so far then one of the cheap and nasty Chinese DDS signal generators >>>>> that has a user defined waveform lookup table would be the way to go. >>>>
    Thinking about possibilities is never a waste of time. It may lead to
    something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form >>>>>
    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >>>>> There is a very good reason why people generate sine waves by default. >>>>>
    I suppose triangle wave and diode shaping to a sine wave would be an >>>>> option (HP once used it to very good effect and their patent for that >>>>> network has probably long since expired by now). ICL8038 did a crude >>>>> imitation of the same trick in their monolithic function generator chip. >>>>>>
    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of
    the sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in >>>>> the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the >>>>> harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.

    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    How would that work?



    A precision clock, high frequency low jitter

    Feeding into the FPGA with say 64bit counter, adding delay line for sub
    clock cycle accuracy

    Compare and lookup on that counter, coupled to the delay line also

    Like standard PWM done in microcontroller timer

    Programming is cycle to cycle, changing just the compare capture word

    That architecture works in theory, and the math isn't bad to do
    on-the-fly in an FPGA. One practical difficulty is building an instantly-programmable glitch-free delay line.

    A second problem is that any output from an FPGA has picoseconds of
    excess jitter.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to klauskvik@hotmail.com on Thu Aug 11 08:46:57 2022
    On Thu, 11 Aug 2022 16:27:54 +0200, Klaus Vestergaard Kragelund <klauskvik@hotmail.com> wrote:

    On 11/08/2022 11.17, Ricky wrote:
    On Thursday, August 11, 2022 at 4:13:20 AM UTC-4, Klaus Kragelund wrote:
    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>>
    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>>>> incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include >>>>>>>> some lower phase accumulator bits to effectively increase the DAC >>>>>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice >>>>> so far then one of the cheap and nasty Chinese DDS signal generators >>>>> that has a user defined waveform lookup table would be the way to go. >>>>
    Thinking about possibilities is never a waste of time. It may lead to
    something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form >>>>>
    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >>>>> There is a very good reason why people generate sine waves by default. >>>>>
    I suppose triangle wave and diode shaping to a sine wave would be an >>>>> option (HP once used it to very good effect and their patent for that >>>>> network has probably long since expired by now). ICL8038 did a crude >>>>> imitation of the same trick in their monolithic function generator chip. >>>>>>
    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in >>>>> the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the >>>>> harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.
    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    Maybe the FPGA has clock jitter, but isn't that as good as the DDS jitter? >>
    The concept of the DDS is to generate a sine wave, which would have some artifacts which could be smoothed by filtering, then a comparator would produce the square wave clock from the sine. This would allow very high resolution of timing, much finer
    than a cycle of the sample rate clock of the DAC.

    That's the tail end of the Shannon Sampling Theorem. A lowpasss filter
    can perfectly reconstruct a bandlimited waveform from periodic
    samples.

    And not just a sine wave.



    Ok, makes good sense. Thanks for the explanation. One could use
    delaylines to get sub cycle resolution, but I guess he must have
    discarded that solution

    One could use a programmable delay to construct an arbitrary-frequency
    clock from a fixed-frequency clock, but then you have the problem of
    computing the delays and reprogramming them every clock.

    I did play with that idea a little. The delay would in fact ramp,
    which works for a while.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to Klaus Vestergaard Kragelund on Thu Aug 11 12:46:21 2022
    Klaus Vestergaard Kragelund wrote:
    On 11/08/2022 11.17, Ricky wrote:
    On Thursday, August 11, 2022 at 4:13:20 AM UTC-4, Klaus Kragelund wrote:
    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>>>> søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd
    <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin >>>>>>>>>>> wrote:

    My question was, why make a sine wave if the final result is >>>>>>>>>>>> a digital
    clock?

    Do you want the digital clock edges to be synchronous with an >>>>>>>>>>> existing source, or
    asynchronous? Mathematically, the creation of an asynchronous >>>>>>>>>>> clock is
    not gonna happen in clocked logic circuitry, it has to have >>>>>>>>>>> an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>>
    I want a programmable internal trigger rate for a pulse
    generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for
    arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the >>>>>>>>>> dac is
    incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only >>>>>>>>> thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave
    a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest >>>>>> jitter.


    The DAC lsb increments rarely at low frequencies, so magically >>>>>>>> include
    some lower phase accumulator bits to effectively increase the DAC >>>>>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how?

    He's trying to intuit a solution by pushing thoughts around,
    rather than reading the knowledge of others. None of this is new
    stuff and he is unlikely to find any "magical" solutions as he
    keeps referring to.

    If he wants to waste his time on this after ignoring all the good
    advice
    so far then one of the cheap and nasty Chinese DDS signal generators >>>>> that has a user defined waveform lookup table would be the way to go. >>>>
    Thinking about possibilities is never a waste of time. It may lead to
    something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment.

    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in
    gradient at zero crossing are parabolic or more generally of the form >>>>>
    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >>>>> There is a very good reason why people generate sine waves by default. >>>>>
    I suppose triangle wave and diode shaping to a sine wave would be an >>>>> option (HP once used it to very good effect and their patent for that >>>>> network has probably long since expired by now). ICL8038 did a crude >>>>> imitation of the same trick in their monolithic function generator
    chip.

    In the end, his enemy is jitter. The effect of various spurs on
    jitter is known. The ones that are hardest to filter are close in
    spurs. Those mostly come from truncation of the phase accumulator. >>>>>> This is not the same thing as truncation of the sine value/DAC
    resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in >>>>> the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the >>>>> harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample
    rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly
    insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.
    I am late into this discussion, so maybe missing something. The aim is
    to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    Maybe the FPGA has clock jitter, but isn't that as good as the DDS
    jitter?

    The concept of the DDS is to generate a sine wave, which would have
    some artifacts which could be smoothed by filtering, then a comparator
    would produce the square wave clock from the sine.  This would allow
    very high resolution of timing, much finer than a cycle of the sample
    rate clock of the DAC.


    Ok, makes good sense. Thanks for the explanation. One could use
    delaylines to get sub cycle resolution, but I guess he must have
    discarded that solution


    Or two DDSes and a mixer. ;)

    Cheers

    Phil Hobbs
    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to Phil Hobbs on Thu Aug 11 13:35:59 2022
    On 8/11/22 12:46 PM, Phil Hobbs wrote:
    Klaus Vestergaard Kragelund wrote:
    On 11/08/2022 11.17, Ricky wrote:
    On Thursday, August 11, 2022 at 4:13:20 AM UTC-4, Klaus Kragelund wrote: >>>> On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk
    wrote:
    søndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt
    Christensen
    <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd
    <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin >>>>>>>>>>>> wrote:

    My question was, why make a sine wave if the final result >>>>>>>>>>>>> is a digital
    clock?

    Do you want the digital clock edges to be synchronous with >>>>>>>>>>>> an existing source, or
    asynchronous? Mathematically, the creation of an
    asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have >>>>>>>>>>>> an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>>>
    I want a programmable internal trigger rate for a pulse
    generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for >>>>>>>>>>> arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the >>>>>>>>>>> dac is
    incremented infrequently and the filter doesn't do much.

    if there is no more timing or amplitude steps to use, the only >>>>>>>>>> thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>>>>>> increase the zero-cross slope. The logical end of that is to >>>>>>>>> make a
    trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave >>>>>>>> a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give
    lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically >>>>>>>>> include
    some lower phase accumulator bits to effectively increase the DAC >>>>>>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how? >>>>>>>
    He's trying to intuit a solution by pushing thoughts around,
    rather than reading the knowledge of others. None of this is new >>>>>>> stuff and he is unlikely to find any "magical" solutions as he
    keeps referring to.

    If he wants to waste his time on this after ignoring all the good
    advice
    so far then one of the cheap and nasty Chinese DDS signal generators >>>>>> that has a user defined waveform lookup table would be the way to go. >>>>>
    Thinking about possibilities is never a waste of time. It may lead to >>>>> something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment. >>>>>
    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest
    waveforms that are steeper at the origin than sin(x) and matched in >>>>>> gradient at zero crossing are parabolic or more generally of the form >>>>>>
    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >>>>>> There is a very good reason why people generate sine waves by
    default.

    I suppose triangle wave and diode shaping to a sine wave would be an >>>>>> option (HP once used it to very good effect and their patent for that >>>>>> network has probably long since expired by now). ICL8038 did a crude >>>>>> imitation of the same trick in their monolithic function generator >>>>>> chip.

    In the end, his enemy is jitter. The effect of various spurs on
    jitter is known. The ones that are hardest to filter are close in >>>>>>> spurs. Those mostly come from truncation of the phase
    accumulator. This is not the same thing as truncation of the sine >>>>>>> value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in >>>>>> the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the >>>>>> harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample >>>>> rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly >>>>> insisting on making a slow sine into the filter+comparator. At high
    frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.
    I am late into this discussion, so maybe missing something. The aim is >>>> to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    Maybe the FPGA has clock jitter, but isn't that as good as the DDS
    jitter?

    The concept of the DDS is to generate a sine wave, which would have
    some artifacts which could be smoothed by filtering, then a
    comparator would produce the square wave clock from the sine.  This
    would allow very high resolution of timing, much finer than a cycle
    of the sample rate clock of the DAC.


    Ok, makes good sense. Thanks for the explanation. One could use
    delaylines to get sub cycle resolution, but I guess he must have
    discarded that solution


    Or two DDSes and a mixer. ;)

    Another approach, sort of like dithering or tape bias, would be to
    compute samples of

    g = epsilon * sin(2*pi*N*f*t) + sin(2*pi*f*t)

    and

    h = epsilon * sin(2*pi*N*f*t)

    for some suitably-chosen values of N(f) and epsilon,

    and use a differential comparator.

    Epsilon would depend fairly strongly on the CMR of the comparator.

    Cheers

    Phil Hobbs


    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    https://hobbs-eo.com

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From whit3rd@21:1/5 to John Larkin on Thu Aug 11 11:55:24 2022
    On Thursday, August 11, 2022 at 8:54:36 AM UTC-7, John Larkin wrote:
    On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund <klau...@hotmail.com> wrote:

    A precision clock, high frequency low jitter

    Feeding into the FPGA with say 64bit counter, adding delay line for sub >clock cycle accuracy

    Compare and lookup on that counter, coupled to the delay line also

    Like standard PWM done in microcontroller timer

    Programming is cycle to cycle, changing just the compare capture word

    That architecture works in theory, and the math isn't bad to do
    on-the-fly in an FPGA. One practical difficulty is building an instantly-programmable glitch-free delay line.

    Or, just fine-tune a cavity oscillator by moving a wall, trombone-style.
    You get continuous frequency control, but it does need a moving part.
    Next step up from that, is a YIG system tuned with magnetic field.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Thu Aug 11 11:55:18 2022
    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
    torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >> >
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide noise power is close to the LSB size, do you need additional dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which accepts 24 bit sample values, but in practice the last few LSB bits are buried in noise.

    If you need better dither control, some DDS chips have phase and/or amplitude modulators built in, so the PM/AM inputs can be used to control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if
    he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters
    for the different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just
    jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the edge
    rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the NCO
    truncation.

    Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not
    betting on it.


    you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
    you want to turn that into a square wave so you stick it into a comparator.

    The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
    so 1uV tresh hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Mike Monett@21:1/5 to whit3rd@gmail.com on Thu Aug 11 19:00:28 2022
    whit3rd <whit3rd@gmail.com> wrote:

    On Thursday, August 11, 2022 at 8:54:36 AM UTC-7, John Larkin wrote:
    On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund
    <klau...@hotmail.com> wrote:

    A precision clock, high frequency low jitter

    Feeding into the FPGA with say 64bit counter, adding delay line for sub
    clock cycle accuracy

    Compare and lookup on that counter, coupled to the delay line also

    Like standard PWM done in microcontroller timer

    Programming is cycle to cycle, changing just the compare capture word

    That architecture works in theory, and the math isn't bad to do
    on-the-fly in an FPGA. One practical difficulty is building an
    instantly-programmable glitch-free delay line.

    Or, just fine-tune a cavity oscillator by moving a wall, trombone-style.
    You get continuous frequency control, but it does need a moving part.
    Next step up from that, is a YIG system tuned with magnetic field.

    Yig's are great, but you have to stabilize the current.



    --
    MRM

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to lang...@fonz.dk on Thu Aug 11 12:36:02 2022
    On Thursday, August 11, 2022 at 2:55:23 PM UTC-4, lang...@fonz.dk wrote:
    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
    torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide noise power is close to the LSB size, do you need additional dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which accepts 24 bit sample values, but in practice the last few LSB bits are buried in noise.

    If you need better dither control, some DDS chips have phase and/or amplitude modulators built in, so the PM/AM inputs can be used to control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of
    this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read,
    if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass
    filters for the different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just
    jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the
    edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the
    NCO truncation.

    Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not
    betting on it.

    you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
    you want to turn that into a square wave so you stick it into a comparator.

    The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
    so 1uV tresh hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    What you are missing is that when you appropriately filter the trapezoid, you get something back that is very much like the sine. If you don't filter, you have the stepped function, so clock periods of jitter. Might as well just produce the clock
    directly from the NCO. The other issues larkin is talking about can be mitigated by running the NCO output through a single, high quality FF external to the logic device.

    --

    Rick C.

    ++- Get 1,000 miles of free Supercharging
    ++- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to langwadt@fonz.dk on Thu Aug 11 15:08:28 2022
    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
    torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >> > > > >> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >> > > > >> >
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >> > > > >>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide >> > > > noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or
    amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of
    this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if
    he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass
    filters for the different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just
    jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the
    edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the
    NCO truncation.

    Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not
    betting on it.


    you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
    you want to turn that into a square wave so you stick it into a comparator.

    The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
    so 1uV tresh hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
    will change about every millisecond. And theoretically one step parks
    at zero volts. So jitter is bad. Gain doesn't improve things.



    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Glen Walpert@21:1/5 to John Larkin on Thu Aug 11 22:53:41 2022
    On Thu, 11 Aug 2022 15:08:28 -0700, John Larkin wrote:

    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk
    wrote:
    torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4,
    upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin
    wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd
    <whi...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin
    wrote:

    My question was, why make a sine wave if the final result
    is a digital clock?

    Do you want the digital clock edges to be synchronous with
    an existing source, or asynchronous? Mathematically, the
    creation of an asynchronous clock is not gonna happen in
    clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse
    generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for
    arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the
    dac is incremented infrequently and the filter doesn't do
    much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the
    wide noise power is close to the LSB size, do you need
    additional dithering?. At low frequencies, there is also the 1/f
    noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB
    bits are buried in noise.

    If you need better dither control, some DDS chips have phase
    and/or amplitude modulators built in, so the PM/AM inputs can be
    used to control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input
    to the DAC. I believe he is talking about much higher sample rates
    than what you can get in audio DACs. He wants to program clock
    rates over a very wide range. Otherwise, none of this is a
    problem. It's also not a problem if multiple filters are switched
    depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock.
    He is trying to view the problem from a very different perspective
    to see if he can gain some insight rather than using the standard,
    well defined approach. From what I've read, if he is looking for
    minimum jitter, there's nothing better than optimizing the length
    of the phase counter, then using any of various means for
    generating a sine waveform with high resolution, then rounding to
    the data width of your DAC. If the clipping/rounding is done at
    the phase word, it introduces close in spurs that can not be
    effectively filtered out. The spurs introduced by rounding or
    truncation of the sine data, tend to be harmonically related to
    the fundamental, and so are much easier to filter.

    The rocket science of NCO/DDS has already been researched and it
    is now more of a cookbook matter, other than the details of
    implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine
    values, but it might have some utility in this case. I think the
    best solution, though, and certainly more likely to produce a good
    result, is to implement different low pass filters for the
    different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS
    output, so the issues is if you have, say just as an example, 1mV of
    noise on where there comparator switches. The slow slewrate of a
    sinewave going through that 1mV can cause more just jitter on the
    resulting squarewave than just hammering through that 1mV window
    with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave
    from the NCO and skipping the filter, that's fine. He will get a
    jitter of one clock period. Adding a filter will do little to clean up
    jitter in the square wave and will slow the edge rate to create the
    noise sensitivity problem again. If the requirements allow this much
    jitter, then there was no need for all the fuss in the first place. If
    he needs low ps level jitter, then he has to mitigate the close in
    spurs created by the NCO truncation.

    Maybe I shouldn't say that. The close in spurs are from phase
    truncation, but maybe they only appear when running that through the
    sine wave generator. If you skip the sine generation, perhaps that
    doesn't produce the unfilterable spurs. I'm not betting on it.


    you are missing the point. Imagine you have a perfect DDS and filter
    combo that makes an absolutely perfect 2Vpp 1Hz sine you want to turn
    that into a square wave so you stick it into a comparator.

    The comparator isn't perfect, the thresh hold varies by, lets say 1uV
    just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s so 1uV tresh
    hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes >>628V/s, the DAC can't make 200V so we'll chop the peaks off since we are >>only interested in the zero crossing so 1uV tresh hold variation is now >>only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC will change about every millisecond. And theoretically one step parks at zero volts. So jitter is bad. Gain doesn't improve things.

    So if I have this right the DDS has lowest jitter at high frequencies and
    a digital clock will have lowest jitter at low frequencies, where you can calculate the optimal crossover frequency between the two for lowest
    jitter across a wide range, and you want to use the phase accumulator? of
    the DDS as your digital clock at lower frequencies, allowing for fast synchronized transition between the two? Been a long time since I used a
    DDS, not at all clear on the details, but is this basically what you are
    trying to do?

    Glen

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From whit3rd@21:1/5 to John Larkin on Thu Aug 11 16:02:42 2022
    On Thursday, August 11, 2022 at 3:08:46 PM UTC-7, John Larkin wrote:
    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
    will change about every millisecond. And theoretically one step parks
    at zero volts. So jitter is bad. Gain doesn't improve things.

    Oh, if your goal is to clock logic, gain certainly DOES improve things; you want
    the fast rise. And, 'one step' is exactly what the filter doesn't pass; your DAC is clocked
    at sub-microsecond intervals complete with some dither, and the microsecond-steps are
    filtered away. You're using the oversampling wrong if you have a millisecond duration zero
    volt output.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Thu Aug 11 16:39:47 2022
    On Thu, 11 Aug 2022 19:00:28 -0000 (UTC), Mike Monett <spamme@not.com>
    wrote:

    whit3rd <whit3rd@gmail.com> wrote:

    On Thursday, August 11, 2022 at 8:54:36 AM UTC-7, John Larkin wrote:
    On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund
    <klau...@hotmail.com> wrote:

    A precision clock, high frequency low jitter

    Feeding into the FPGA with say 64bit counter, adding delay line for sub >>> >clock cycle accuracy

    Compare and lookup on that counter, coupled to the delay line also

    Like standard PWM done in microcontroller timer

    Programming is cycle to cycle, changing just the compare capture word

    That architecture works in theory, and the math isn't bad to do
    on-the-fly in an FPGA. One practical difficulty is building an
    instantly-programmable glitch-free delay line.

    Or, just fine-tune a cavity oscillator by moving a wall, trombone-style.
    You get continuous frequency control, but it does need a moving part.
    Next step up from that, is a YIG system tuned with magnetic field.

    Yig's are great, but you have to stabilize the current.

    It sounds messy to get extreme mag field stability. And a yig won't go
    down to 1 Hz.
    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Thu Aug 11 16:28:32 2022
    On Thu, 11 Aug 2022 22:53:41 GMT, Glen Walpert <nospam@null.void>
    wrote:

    On Thu, 11 Aug 2022 15:08:28 -0700, John Larkin wrote:

    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
    <langwadt@fonz.dk> wrote:

    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk
    wrote:
    torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4,
    upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin
    wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd
    <whi...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin
    wrote:

    My question was, why make a sine wave if the final result
    is a digital clock?

    Do you want the digital clock edges to be synchronous with
    an existing source, or asynchronous? Mathematically, the
    creation of an asynchronous clock is not gonna happen in
    clocked logic circuitry, it has to have an analog component. >>>> > > > >> Of course. The analog components are dac, filter, comparator. >>>> > > > >>
    I want a programmable internal trigger rate for a pulse
    generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for
    arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the >>>> > > > >> dac is incremented infrequently and the filter doesn't do
    much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the
    wide noise power is close to the LSB size, do you need
    additional dithering?. At low frequencies, there is also the 1/f >>>> > > > noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which >>>> > > > accepts 24 bit sample values, but in practice the last few LSB
    bits are buried in noise.

    If you need better dither control, some DDS chips have phase
    and/or amplitude modulators built in, so the PM/AM inputs can be >>>> > > > used to control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input
    to the DAC. I believe he is talking about much higher sample rates >>>> > > than what you can get in audio DACs. He wants to program clock
    rates over a very wide range. Otherwise, none of this is a
    problem. It's also not a problem if multiple filters are switched
    depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. >>>> > > He is trying to view the problem from a very different perspective >>>> > > to see if he can gain some insight rather than using the standard, >>>> > > well defined approach. From what I've read, if he is looking for
    minimum jitter, there's nothing better than optimizing the length
    of the phase counter, then using any of various means for
    generating a sine waveform with high resolution, then rounding to
    the data width of your DAC. If the clipping/rounding is done at
    the phase word, it introduces close in spurs that can not be
    effectively filtered out. The spurs introduced by rounding or
    truncation of the sine data, tend to be harmonically related to
    the fundamental, and so are much easier to filter.

    The rocket science of NCO/DDS has already been researched and it
    is now more of a cookbook matter, other than the details of
    implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine
    values, but it might have some utility in this case. I think the
    best solution, though, and certainly more likely to produce a good >>>> > > result, is to implement different low pass filters for the
    different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS
    output, so the issues is if you have, say just as an example, 1mV of >>>> > noise on where there comparator switches. The slow slewrate of a
    sinewave going through that 1mV can cause more just jitter on the
    resulting squarewave than just hammering through that 1mV window
    with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave
    from the NCO and skipping the filter, that's fine. He will get a
    jitter of one clock period. Adding a filter will do little to clean up >>>> jitter in the square wave and will slow the edge rate to create the
    noise sensitivity problem again. If the requirements allow this much
    jitter, then there was no need for all the fuss in the first place. If >>>> he needs low ps level jitter, then he has to mitigate the close in
    spurs created by the NCO truncation.

    Maybe I shouldn't say that. The close in spurs are from phase
    truncation, but maybe they only appear when running that through the
    sine wave generator. If you skip the sine generation, perhaps that
    doesn't produce the unfilterable spurs. I'm not betting on it.


    you are missing the point. Imagine you have a perfect DDS and filter >>>combo that makes an absolutely perfect 2Vpp 1Hz sine you want to turn >>>that into a square wave so you stick it into a comparator.

    The comparator isn't perfect, the thresh hold varies by, lets say 1uV >>>just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s so 1uV tresh
    hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes >>>628V/s, the DAC can't make 200V so we'll chop the peaks off since we are >>>only interested in the zero crossing so 1uV tresh hold variation is now >>>only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC will
    change about every millisecond. And theoretically one step parks at zero
    volts. So jitter is bad. Gain doesn't improve things.

    So if I have this right the DDS has lowest jitter at high frequencies and
    a digital clock will have lowest jitter at low frequencies, where you can >calculate the optimal crossover frequency between the two for lowest
    jitter across a wide range, and you want to use the phase accumulator? of
    the DDS as your digital clock at lower frequencies, allowing for fast >synchronized transition between the two? Been a long time since I used a >DDS, not at all clear on the details, but is this basically what you are >trying to do?

    Glen

    That's about right. At high frequencies, synthesize a waveform
    (usually a sine) and lowpass filter it into a comparator. At low
    frequencies, just use the MSB of the phase accumulator as the clock. I
    think a glitchless transition can be made between those two modes.

    And next step, do something trickier between the phase accumulator and
    the DAC, trapezoid maybe at a high DAC clock rate where the filter
    still helps.





    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Thu Aug 11 16:33:14 2022
    On Thu, 11 Aug 2022 16:02:42 -0700 (PDT), whit3rd <whit3rd@gmail.com>
    wrote:

    On Thursday, August 11, 2022 at 3:08:46 PM UTC-7, John Larkin wrote:
    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
    will change about every millisecond. And theoretically one step parks
    at zero volts. So jitter is bad. Gain doesn't improve things.

    Oh, if your goal is to clock logic, gain certainly DOES improve things; you want
    the fast rise. And, 'one step' is exactly what the filter doesn't pass; your DAC is clocked
    at sub-microsecond intervals complete with some dither, and the microsecond-steps are
    filtered away. You're using the oversampling wrong if you have a millisecond duration zero
    volt output.

    A comparator makes a fast rise. The problem is at the DAC output.

    Dithering sounds like a jitter generator. I'd rather put some clever
    waveform into the DAC.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Anthony William Sloman@21:1/5 to John Larkin on Thu Aug 11 18:59:05 2022
    On Friday, August 12, 2022 at 1:54:36 AM UTC+10, John Larkin wrote:
    On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund <klau...@hotmail.com> wrote:

    On 11/08/2022 16.35, John Larkin wrote:
    On Thu, 11 Aug 2022 10:13:10 +0200, Klaus Vestergaard Kragelund
    <klau...@hotmail.com> wrote:

    On 10/08/2022 16.47, John Larkin wrote:
    On Wed, 10 Aug 2022 09:50:48 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 08/08/2022 21:17, Ricky wrote:
    On Sunday, August 7, 2022 at 5:06:06 PM UTC-4, lang...@fonz.dk wrote: >>>>>>> sųndag den 7. august 2022 kl. 22.52.07 UTC+2 skrev John Larkin: >>>>>>>> On Sun, 7 Aug 2022 13:27:44 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> <lang...@fonz.dk> wrote:
    s?ndag den 7. august 2022 kl. 21.48.51 UTC+2 skrev John Larkin: >>>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>>
    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much. >>>>>>>>>
    if there is no more timing or amplitude steps to use, the only thing you can do it lower the filter cutoff

    That has problems too.

    We were thinking that you could gain-up and clip the sine wave to >>>>>>>> increase the zero-cross slope. The logical end of that is to make a >>>>>>>> trapezoid with a steep rise.
    keep decreasing the rise time and you get back to a squarewave >>>>>>> a sine is probably some kind of optimum

    It is an optimum in that it is most easily filtered to give lowest jitter.


    The DAC lsb increments rarely at low frequencies, so magically include
    some lower phase accumulator bits to effectively increase the DAC >>>>>>>> sample rate on that steep slope. Digitally interpolate.
    but if the DAC can't run any faster or have any more bits, how? >>>>>>
    He's trying to intuit a solution by pushing thoughts around, rather than reading the knowledge of others. None of this is new stuff and he is unlikely to find any "magical" solutions as he keeps referring to.

    If he wants to waste his time on this after ignoring all the good advice
    so far then one of the cheap and nasty Chinese DDS signal generators >>>>> that has a user defined waveform lookup table would be the way to go. >>>>
    Thinking about possibilities is never a waste of time. It may lead to >>>> something useful now or later, and thinking is good exercise for
    thinking.

    Try it.


    Nothing refutes a daft idea so effectively as practical experiment. >>>>
    The idea shooters here don't need experiments, when insults are
    easier.


    Not knowing exactly why he really wants to do this - the simplest >>>>> waveforms that are steeper at the origin than sin(x) and matched in >>>>> gradient at zero crossing are parabolic or more generally of the form >>>>>
    (1- (|x/pi-1/2|)^N)

    (and that function negated that on alternate half cycles)

    NB gradient of his triangle wave is 1 (or -1) everywhere but the
    gradient of the sine wave is +/-pi/2 at the origin (and 0 at maxima). >>>>> There is a very good reason why people generate sine waves by default. >>>>>
    I suppose triangle wave and diode shaping to a sine wave would be an >>>>> option (HP once used it to very good effect and their patent for that >>>>> network has probably long since expired by now). ICL8038 did a crude >>>>> imitation of the same trick in their monolithic function generator chip.

    In the end, his enemy is jitter. The effect of various spurs on jitter is known. The ones that are hardest to filter are close in spurs. Those mostly come from truncation of the phase accumulator. This is not the same thing as truncation of the
    sine value/DAC resolution.

    Anyone who wishes to research DDS design will find this.

    The low pass filter needs to be frequency matched to the artefacts in >>>>> the fundamental frequency being generated. No point in low pass
    filtering at 1MHz when the output is 10Hz. You need to attenuate the >>>>> harmonics generated by the discrete steps in the DAC waveform.

    And one has to do something about the fact that the DAC code will
    increment infrequently at 1 Hz. That is a time-domain concept.

    I suggested digitally shaping the DAC waveform to increase the sample >>>> rate and slope at low frequencies. Or at all frequencies.
    Interpolation is one approach.

    New idea: at some low frequency, just banging the dac rail-to-rail
    with the phase accumulator MSB will make less jitter than stubbornly >>>> insisting on making a slow sine into the filter+comparator. At high >>>> frequencies, the unfiltered MSB is a horror.

    That idea has interesting offshoots.

    I am late into this discussion, so maybe missing something. The aim is >>> to generate a programmed clock. Why not ditch the DDS and use a
    precision clock into a FPGA that digitally generates the clock

    How would that work?



    A precision clock, high frequency low jitter

    Feeding into the FPGA with say 64bit counter, adding delay line for sub >clock cycle accuracy

    Compare and lookup on that counter, coupled to the delay line also

    Like standard PWM done in microcontroller timer

    Programming is cycle to cycle, changing just the compare capture word
    That architecture works in theory, and the math isn't bad to do
    on-the-fly in an FPGA. One practical difficulty is building an instantly-programmable glitch-free delay line.

    Been done.

    https://www.onsemi.com/pdf/datasheet/mc100ep195-d.pdf

    The 100ep196 has a fine-tune option built in. How fast and accurately you can change the 0 to 60psec continuously variable extra delay isn't specificied

    https://www.onsemi.com/pdf/datasheet/mc100ep196-d.pdf

    The actual delays are slightly temperature dependent, so you either have to thermostat the part or use to two of them and spend half your time measuring what what is actually doing - which needn't take long - while the other is doing the job. I figured
    on generating a pulse-width-modulated waveform and digiitising the average DC level with a fast ADC.

    A second problem is that any output from an FPGA has picoseconds of excess jitter.

    So resynchronise it it a good clock.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Anthony William Sloman@21:1/5 to John Larkin on Thu Aug 11 19:10:16 2022
    On Friday, August 12, 2022 at 9:40:02 AM UTC+10, John Larkin wrote:
    On Thu, 11 Aug 2022 19:00:28 -0000 (UTC), Mike Monett <spa...@not.com> wrote:
    whit3rd <whi...@gmail.com> wrote:

    On Thursday, August 11, 2022 at 8:54:36 AM UTC-7, John Larkin wrote:
    On Thu, 11 Aug 2022 16:51:33 +0200, Klaus Vestergaard Kragelund
    <klau...@hotmail.com> wrote:

    A precision clock, high frequency low jitter

    Feeding into the FPGA with say 64bit counter, adding delay line for sub >>> >clock cycle accuracy

    Compare and lookup on that counter, coupled to the delay line also

    Like standard PWM done in microcontroller timer

    Programming is cycle to cycle, changing just the compare capture word >>
    That architecture works in theory, and the math isn't bad to do
    on-the-fly in an FPGA. One practical difficulty is building an
    instantly-programmable glitch-free delay line.

    Or, just fine-tune a cavity oscillator by moving a wall, trombone-style. >> You get continuous frequency control, but it does need a moving part.
    Next step up from that, is a YIG system tuned with magnetic field.

    Yig's are great, but you have to stabilize the current.
    It sounds messy to get extreme mag field stability. And a yig won't go
    down to 1 Hz.

    It doesn't have to. If you can tune the YIG oscillator over a continuous 2:1 range , a binary divider can get you almost literally any lower frequency - a thirty stage divider get you close to 1Hz. And the YIG oscillation frequency is a pretty accurate
    guide to the magnetic field - monitor that for feedback control of the magnetic field.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Martin Brown@21:1/5 to John Larkin on Fri Aug 12 08:20:50 2022
    On 11/08/2022 23:08, John Larkin wrote:
    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote: >>>> torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>> incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide >>>>>> noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits >>>>>> are buried in noise.

    If you need better dither control, some DDS chips have phase and/or >>>>>> amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if
    he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters
    for the different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just
    jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the
    edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the
    NCO truncation.

    Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not
    betting on it.


    you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
    you want to turn that into a square wave so you stick it into a comparator. >>
    The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
    so 1uV tresh hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
    will change about every millisecond. And theoretically one step parks
    at zero volts. So jitter is bad. Gain doesn't improve things.

    Although that is true if you set your zero crossing high/low by half a
    least significant bit (or half the smallest step in the sine wave table)
    then you can trade lower jitter for a small asymmetry in the waveform.

    Then divide by two in the digital domain and you are done.

    The other option is to integrate the output of the DAC so that you get a
    join the dots piecewise linear waveform much more amenable to comparator thresholding and interpolation in the time domain.

    But then you have new problems - drift/offsets in the integrator,
    variable gain and delay offset as the frequency changes.

    There is no free lunch!

    --
    Regards,
    Martin Brown

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From upsidedown@downunder.com@21:1/5 to gnuarm.deletethisbit@gmail.com on Fri Aug 12 16:54:04 2022
    On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky <gnuarm.deletethisbit@gmail.com> wrote:

    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital >> >> >> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >> >> >not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide
    noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or
    amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.

    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

    If the purpose is to create a variable _timing_ generator (not just
    frequency generator), why mess with the DDS principle at all ?

    Using a divide-by-N counter clocked at say, 1 GHz, you can timing
    intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some
    trickery is needed to avoid running all 48 stages at full ECL speed.

    But the real question is, do you really need nanosecond step size in
    minutes, hours or day time scale ?

    Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
    which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
    might be justified to get 1 ps timing steps. But for longer times,
    say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
    after the DDS ? Combining the DDS and divide-by-N programming, quite
    strange periods can be obtained.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to '''newspam'''@nonad.co.uk on Fri Aug 12 07:02:15 2022
    On Fri, 12 Aug 2022 08:20:50 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 11/08/2022 23:08, John Larkin wrote:
    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen
    <langwadt@fonz.dk> wrote:

    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote: >>>>> torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>>
    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>>> incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide >>>>>>> noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which >>>>>>> accepts 24 bit sample values, but in practice the last few LSB bits >>>>>>> are buried in noise.

    If you need better dither control, some DDS chips have phase and/or >>>>>>> amplitude modulators built in, so the PM/AM inputs can be used to >>>>>>> control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of
    this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if
    he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass
    filters for the different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just
    jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the
    edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the
    NCO truncation.

    Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not
    betting on it.


    you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
    you want to turn that into a square wave so you stick it into a comparator. >>>
    The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
    so 1uV tresh hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
    will change about every millisecond. And theoretically one step parks
    at zero volts. So jitter is bad. Gain doesn't improve things.

    Although that is true if you set your zero crossing high/low by half a
    least significant bit (or half the smallest step in the sine wave table)
    then you can trade lower jitter for a small asymmetry in the waveform.

    The DAC still increments once a millisecond.


    Then divide by two in the digital domain and you are done.

    The other option is to integrate the output of the DAC so that you get a
    join the dots piecewise linear waveform much more amenable to comparator >thresholding and interpolation in the time domain.

    But then you have new problems - drift/offsets in the integrator,
    variable gain and delay offset as the frequency changes.

    There is no free lunch!

    The option is to do digital tricks in the FPGA. Almost free lunch.

    I'm thinking that it's (barely) possible to simulate the DDS in LT
    Spice. The tricky part would then be measuring period jitter.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to upsidedown@downunder.com on Fri Aug 12 07:10:56 2022
    On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote:

    On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky ><gnuarm.deletethisbit@gmail.com> wrote:

    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >>> >> >not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>> >> up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide
    noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or
    amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.

    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

    If the purpose is to create a variable _timing_ generator (not just
    frequency generator), why mess with the DDS principle at all ?

    Most of our customers expect to set an internal trigger frequency.
    There are times when setting it to high resolution is valuable.


    Using a divide-by-N counter clocked at say, 1 GHz, you can timing
    intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some >trickery is needed to avoid running all 48 stages at full ECL speed.

    I can't do that in an FPGA. And resolution is mediocre around 10 MHz.

    It might be interesting to program a 1 GHz SERDES channel (which we
    can do) DDS-sorta waveform that we can filter into a comparator.
    That's hard to think about, which I can delegate.


    But the real question is, do you really need nanosecond step size in
    minutes, hours or day time scale ?

    A straightforward DDS will have tons of period jitter at low
    frequencies, which is ugly. And some customers whine if we stop
    triggering while we reprogram a DDS (or a synth chip) and a divisor.



    Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
    which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
    might be justified to get 1 ps timing steps. But for longer times,
    say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
    after the DDS ? Combining the DDS and divide-by-N programming, quite
    strange periods can be obtained.

    I'll ping the boys about the SERDES idea. That could be cool.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Anthony William Sloman@21:1/5 to John Larkin on Fri Aug 12 07:38:44 2022
    On Saturday, August 13, 2022 at 12:11:15 AM UTC+10, John Larkin wrote:
    On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote:
    On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky <gnuarm.del...@gmail.com> wrote:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote:

    <snip>

    Using a divide-by-N counter clocked at say, 1 GHz, you can timing
    intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some >trickery is needed to avoid running all 48 stages at full ECL speed.

    I can't do that in an FPGA. And resolution is mediocre around 10 MHz.

    Peter Alfke probably could have. Sadly, he is dead.

    https://www.eetimes.com/peter-alfke-remembered-1931-2011/

    There are quite a lot of different sorts of FPGA's around, some of them quite quick

    It might be interesting to program a 1 GHz SERDES channel (which we
    can do) DDS-sorta waveform that we can filter into a comparator.
    That's hard to think about, which I can delegate.

    But the real question is, do you really need nanosecond step size in >minutes, hours or day time scale?

    A straightforward DDS will have tons of period jitter at low frequencies, which is ugly.

    So don't use a "straightforward DDS".

    And some customers whine if we stop triggering while we reprogram a DDS (or a synth chip) and a divisor.

    So ping-pong between two.

    Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
    which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
    might be justified to get 1 ps timing steps. But for longer times,
    say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
    after the DDS ? Combining the DDS and divide-by-N programming, quite >strange periods can be obtained.

    I'll ping the boys about the SERDES idea. That could be cool.

    The last serial data link that I played with was the Taxichip back in 1988. It used an 8-bit to 10-bit recoding scheme to avoid sending troublesome bit patterns.

    Working out what you were actually sending might be a bit tedious.

    --
    Bill Sloman, Sydney

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Mike Monett@21:1/5 to upsidedown@downunder.com on Fri Aug 12 16:08:13 2022
    upsidedown@downunder.com wrote:

    [...]

    If the purpose is to create a variable _timing_ generator (not just
    frequency generator), why mess with the DDS principle at all ?

    Using a divide-by-N counter clocked at say, 1 GHz, you can timing
    intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some trickery is needed to avoid running all 48 stages at full ECL speed.

    But the real question is, do you really need nanosecond step size in
    minutes, hours or day time scale ?

    Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
    which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
    might be justified to get 1 ps timing steps. But for longer times,
    say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
    after the DDS ? Combining the DDS and divide-by-N programming, quite
    strange periods can be obtained.

    The Stanford Research Systems group has introduced a new method of
    frequency generation described below:

    SG380 Series RF Signal Generators

    Introducing the new SG380 Series RF Signal Generators—finally, high performance, affordable RF sources.

    The SG380 Series RF Signal Generators use a unique, innovative architecture (Rational Approximation Frequency Synthesis) to deliver ultra-high
    frequency resolution (1 µHz), excellent phase noise, and versatile
    modulation capabilities (AM, FM, ØM, pulse modulation and sweeps) at a
    fraction of the cost of competing designs.

    The standard models produce sine waves from DC to 2.025 GHz (SG382), 4.05
    GHz (SG384) and 6.075 GHz (SG386).

    A New Frequency Synthesis Technique

    The SG380 Series Signal Generators are based on a new frequency synthesis technique called Rational Approximation Frequency Synthesis (RAFS). RAFS
    uses small integer divisors in a conventional phase-locked loop (PLL) to synthesize a frequency that would be close to the desired frequency
    (typically within ±100 ppm) using the nominal PLL reference frequency. The
    PLL reference frequency, which is sourced by a voltage control crystal oscillator that is phase locked to a dithered direct digital synthesizer,
    is adjusted so that the PLL generates the exact frequency. Doing so
    provides a high phase comparison frequency (typically 25 MHz) yielding low phase noise while moving the PLL reference spurs far from the carrier where they can be easily removed. The end result is an agile RF source with low
    phase noise, essentially infinite frequency resolution, without the spurs
    of fractional-N synthesis or the cost of a YIG oscillator.

    https://www.thinksrs.com/products/sg380.html

    The manual is at

    https://www.thinksrs.com/downloads/pdfs/manuals/SG380m.pdf

    The description of Rational Approximation Synthesis starts on page 151. A
    block diagram is on page 156.





    --
    MRM

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Fri Aug 12 09:43:19 2022
    On Friday, August 12, 2022 at 10:11:15 AM UTC-4, John Larkin wrote:
    On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote:

    On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:

    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>> >> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>> >> >
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>> >>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >>> >> incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide
    noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or
    amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.

    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

    If the purpose is to create a variable _timing_ generator (not just >frequency generator), why mess with the DDS principle at all ?
    Most of our customers expect to set an internal trigger frequency.
    There are times when setting it to high resolution is valuable.

    Using a divide-by-N counter clocked at say, 1 GHz, you can timing >intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some >trickery is needed to avoid running all 48 stages at full ECL speed.
    I can't do that in an FPGA. And resolution is mediocre around 10 MHz.

    It might be interesting to program a 1 GHz SERDES channel (which we
    can do) DDS-sorta waveform that we can filter into a comparator.
    That's hard to think about, which I can delegate.

    But the real question is, do you really need nanosecond step size in >minutes, hours or day time scale ?
    A straightforward DDS will have tons of period jitter at low
    frequencies, which is ugly. And some customers whine if we stop
    triggering while we reprogram a DDS (or a synth chip) and a divisor.

    Admittedly, the 1 ns timing step is quite coarse at short pulses, inn >which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
    might be justified to get 1 ps timing steps. But for longer times,
    say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
    after the DDS ? Combining the DDS and divide-by-N programming, quite >strange periods can be obtained.
    I'll ping the boys about the SERDES idea. That could be cool.

    Cool, but it puts you right back at dealing with all the jitter issues of outputting the timing signal directly from the FPGA.

    --

    Rick C.

    +++ Get 1,000 miles of free Supercharging
    +++ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to John Larkin on Fri Aug 12 13:03:12 2022
    John Larkin wrote:
    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote: >>>> torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>>>> incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide >>>>>> noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits >>>>>> are buried in noise.

    If you need better dither control, some DDS chips have phase and/or >>>>>> amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read, if
    he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass filters
    for the different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just
    jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the
    edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the
    NCO truncation.

    Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not
    betting on it.


    you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
    you want to turn that into a square wave so you stick it into a comparator. >>
    The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
    so 1uV tresh hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
    will change about every millisecond. And theoretically one step parks
    at zero volts. So jitter is bad. Gain doesn't improve things.

    Numerical gain ahead of the DAC does help, though, as somebody pointed
    out upthread.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

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  • From Ricky@21:1/5 to Phil Hobbs on Fri Aug 12 12:26:44 2022
    On Friday, August 12, 2022 at 1:03:24 PM UTC-4, Phil Hobbs wrote:
    John Larkin wrote:
    On Thu, 11 Aug 2022 11:55:18 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    torsdag den 11. august 2022 kl. 05.19.40 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 7:37:31 PM UTC-4, lang...@fonz.dk wrote:
    torsdag den 11. august 2022 kl. 00.42.05 UTC+2 skrev Ricky:
    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator. >>>>>>>>
    I want a programmable internal trigger rate for a pulse generator. >>>>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is
    incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide >>>>>> noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which >>>>>> accepts 24 bit sample values, but in practice the last few LSB bits >>>>>> are buried in noise.

    If you need better dither control, some DDS chips have phase and/or >>>>>> amplitude modulators built in, so the PM/AM inputs can be used to >>>>>> control the high frequency dither more precisely.
    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of
    this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach. From what I've read,
    if he is looking for minimum jitter, there's nothing better than optimizing the length of the phase counter, then using any of various means for generating a sine waveform with high resolution, then rounding to the data width of your DAC. If the clipping/
    rounding is done at the phase word, it introduces close in spurs that can not be effectively filtered out. The spurs introduced by rounding or truncation of the sine data, tend to be harmonically related to the fundamental, and so are much easier to
    filter.

    The rocket science of NCO/DDS has already been researched and it is now more of a cookbook matter, other than the details of implementing the hardware, which has lots of analog gotchas.

    I've never looked at the idea of using dither on the digital sine values, but it might have some utility in this case. I think the best solution, though, and certainly more likely to produce a good result, is to implement different low pass
    filters for the different ranges of clock output rates.

    Don't you agree?
    afaict we are talking about making a square wave from the DDS output, so the issues is if you have, say just as an example, 1mV of noise on where there comparator switches. The slow slewrate of a sinewave going through that 1mV can cause more just
    jitter on the resulting squarewave than just hammering through that 1mV window with some waveform with a high slewrate
    And your point is?

    If larkin is talking about producing a square or "trapezoidal" wave from the NCO and skipping the filter, that's fine. He will get a jitter of one clock period. Adding a filter will do little to clean up jitter in the square wave and will slow the
    edge rate to create the noise sensitivity problem again. If the requirements allow this much jitter, then there was no need for all the fuss in the first place. If he needs low ps level jitter, then he has to mitigate the close in spurs created by the
    NCO truncation.

    Maybe I shouldn't say that. The close in spurs are from phase truncation, but maybe they only appear when running that through the sine wave generator. If you skip the sine generation, perhaps that doesn't produce the unfilterable spurs. I'm not
    betting on it.


    you are missing the point. Imagine you have a perfect DDS and filter combo that makes an absolutely perfect 2Vpp 1Hz sine
    you want to turn that into a square wave so you stick it into a comparator.

    The comparator isn't perfect, the thresh hold varies by, lets say 1uV just to pick a number, due to noise etc.
    At the zero crossing the slewrate is 2*pi*1*1 = 6.28V/s
    so 1uV tresh hold variation turns into a ~16us timing variation

    ok, the lets make the sine wave 200Vpp 1Hz, so the slew rate becomes 628V/s, the DAC can't make 200V so we'll chop
    the peaks off since we are only interested in the zero crossing
    so 1uV tresh hold variation is now only a ~160ns timing variation

    Yes, but if we synthesize a 1 Hz sine wave, the LSB of a 10-bit DAC
    will change about every millisecond. And theoretically one step parks
    at zero volts. So jitter is bad. Gain doesn't improve things.
    Numerical gain ahead of the DAC does help, though, as somebody pointed
    out upthread.

    It's hard to do good work with a 10 bit DAC. A 16 bit DAC would improve the time step to about 16 us.

    https://www.ti.com/data-converters/dac-circuit/high-speed/products.html#p84=16;16&sort=p1130;asc

    This time step does not define the jitter. That's why the sine wave is filtered, to smooth the threshold point to a proper sine function. Different filters are needed for different frequency ranges. That would seem to be pretty obvious.

    --

    Rick C.

    ---- Get 1,000 miles of free Supercharging
    ---- Tesla referral code - https://ts.la/richard11209

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  • From Clifford Heath@21:1/5 to Martin Brown on Sat Aug 13 10:13:41 2022
    On 12/8/22 17:20, Martin Brown wrote:
    Although that is true if you set your zero crossing high/low by half a
    least significant bit (or half the smallest step in the sine wave table)
    then you can trade lower jitter for a small asymmetry in the waveform.

    Wouldn't it be just as good (and symmetrical) to introduce a one-bit hysteresis? And not need to divide?

    The other option is to integrate the output of the DAC so that you get a
    join the dots piecewise linear waveform much more amenable to comparator thresholding and interpolation in the time domain.

    So, a first-order filter? What do you reckon a normal DDS filter is doing?

    Clifford Heath

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  • From Clifford Heath@21:1/5 to upsidedown@downunder.com on Sat Aug 13 10:14:50 2022
    On 12/8/22 23:54, upsidedown@downunder.com wrote:
    On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky <gnuarm.deletethisbit@gmail.com> wrote:

    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com>
    wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>
    My question was, why make a sine wave if the final result is a digital >>>>>>> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator.

    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>> incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide
    noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or
    amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.

    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

    If the purpose is to create a variable _timing_ generator (not just
    frequency generator), why mess with the DDS principle at all ?

    Using a divide-by-N counter clocked at say, 1 GHz, you can timing
    intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some trickery is needed to avoid running all 48 stages at full ECL speed.

    But the real question is, do you really need nanosecond step size in
    minutes, hours or day time scale ?

    Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
    which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
    might be justified to get 1 ps timing steps. But for longer times,
    say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
    after the DDS ? Combining the DDS and divide-by-N programming, quite
    strange periods can be obtained.

    You just described a one-bit DDS. It doesn't need a lookup table, of course.

    CH

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  • From Clifford Heath@21:1/5 to John Larkin on Sat Aug 13 10:17:49 2022
    On 13/8/22 00:10, John Larkin wrote:
    On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote:

    On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
    <gnuarm.deletethisbit@gmail.com> wrote:

    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote:
    On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>
    My question was, why make a sine wave if the final result is a digital >>>>>>>> clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is >>>>>>> not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N, >>>>>> up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>> incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide
    noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits
    are buried in noise.

    If you need better dither control, some DDS chips have phase and/or
    amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.

    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of
    this is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

    If the purpose is to create a variable _timing_ generator (not just
    frequency generator), why mess with the DDS principle at all ?

    Most of our customers expect to set an internal trigger frequency.
    There are times when setting it to high resolution is valuable.


    Using a divide-by-N counter clocked at say, 1 GHz, you can timing
    intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some
    trickery is needed to avoid running all 48 stages at full ECL speed.

    I can't do that in an FPGA. And resolution is mediocre around 10 MHz.

    It might be interesting to program a 1 GHz SERDES channel (which we
    can do) DDS-sorta waveform that we can filter into a comparator.
    That's hard to think about, which I can delegate.


    But the real question is, do you really need nanosecond step size in
    minutes, hours or day time scale ?

    A straightforward DDS will have tons of period jitter at low
    frequencies, which is ugly. And some customers whine if we stop
    triggering while we reprogram a DDS (or a synth chip) and a divisor.

    So use the top bit of the DDS accumulator, but take the next few bits to
    drive a digital delay generator to add 0..1ns of extra delay (or
    0.5..1.5ns, etc). You're good with design of picosecond digital delay generators, I understand?

    Clifford Heath.

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  • From Lasse Langwadt Christensen@21:1/5 to All on Sat Aug 13 04:19:21 2022
    lørdag den 13. august 2022 kl. 02.17.58 UTC+2 skrev Clifford Heath:
    On 13/8/22 00:10, John Larkin wrote:
    On Fri, 12 Aug 2022 16:54:04 +0300, upsid...@downunder.com wrote:

    On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:

    On Wednesday, August 10, 2022 at 3:37:19 PM UTC-4, upsid...@downunder.com wrote:
    On Sun, 7 Aug 2022 13:26:12 -0700 (PDT), Ricky
    <gnuarm.del...@gmail.com> wrote:
    On Sunday, August 7, 2022 at 3:48:51 PM UTC-4, John Larkin wrote: >>>>>> On Sun, 7 Aug 2022 11:09:02 -0700 (PDT), whit3rd <whi...@gmail.com> >>>>>> wrote:
    On Sunday, August 7, 2022 at 10:57:17 AM UTC-7, John Larkin wrote: >>>>>>>
    My question was, why make a sine wave if the final result is a digital
    clock?

    Do you want the digital clock edges to be synchronous with an existing source, or
    asynchronous? Mathematically, the creation of an asynchronous clock is
    not gonna happen in clocked logic circuitry, it has to have an analog component.
    Of course. The analog components are dac, filter, comparator.

    I want a programmable internal trigger rate for a pulse generator. >>>>>>
    A 48-bit DDS will make a frequency of Fclk * N / 2^48 for arbitrary N,
    up to Nyquist. But it gets messy at low frequencies where the dac is >>>>>> incremented infrequently and the filter doesn't do much.

    Sounds like an application for dithering.

    Do you even need explicit dithering ?

    The DAC output has some wide band (thermal) white noise. If the wide >>>> noise power is close to the LSB size, do you need additional
    dithering?. At low frequencies, there is also the 1/f noise.

    For audio frequencies "24 bit" 192 kHz DACs are available, which
    accepts 24 bit sample values, but in practice the last few LSB bits >>>> are buried in noise.

    If you need better dither control, some DDS chips have phase and/or >>>> amplitude modulators built in, so the PM/AM inputs can be used to
    control the high frequency dither more precisely.

    larkin is concerned about what amounts to dead band in the input to the DAC. I believe he is talking about much higher sample rates than what you can get in audio DACs. He wants to program clock rates over a very wide range. Otherwise, none of this
    is a problem. It's also not a problem if multiple filters are switched depending on the frequency of the output clock.

    He's already talked about using octave dividers to slow the clock. He is trying to view the problem from a very different perspective to see if he can gain some insight rather than using the standard, well defined approach.

    If the purpose is to create a variable _timing_ generator (not just
    frequency generator), why mess with the DDS principle at all ?

    Most of our customers expect to set an internal trigger frequency.
    There are times when setting it to high resolution is valuable.


    Using a divide-by-N counter clocked at say, 1 GHz, you can timing
    intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some
    trickery is needed to avoid running all 48 stages at full ECL speed.

    I can't do that in an FPGA. And resolution is mediocre around 10 MHz.

    It might be interesting to program a 1 GHz SERDES channel (which we
    can do) DDS-sorta waveform that we can filter into a comparator.
    That's hard to think about, which I can delegate.


    But the real question is, do you really need nanosecond step size in
    minutes, hours or day time scale ?

    A straightforward DDS will have tons of period jitter at low
    frequencies, which is ugly. And some customers whine if we stop
    triggering while we reprogram a DDS (or a synth chip) and a divisor.
    So use the top bit of the DDS accumulator, but take the next few bits to drive a digital delay generator to add 0..1ns of extra delay (or
    0.5..1.5ns, etc).

    make a square wave with the DAC, into integrator (filter)
    vary the amplitude

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  • From upsidedown@downunder.com@21:1/5 to jjlarkin@highlandtechnology.com on Sat Aug 13 16:48:49 2022
    On Fri, 12 Aug 2022 07:10:56 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:

    On Fri, 12 Aug 2022 16:54:04 +0300, upsidedown@downunder.com wrote:

    On Wed, 10 Aug 2022 15:42:00 -0700 (PDT), Ricky

    <snip>

    If the purpose is to create a variable _timing_ generator (not just >>frequency generator), why mess with the DDS principle at all ?

    Most of our customers expect to set an internal trigger frequency.
    There are times when setting it to high resolution is valuable.


    Using a divide-by-N counter clocked at say, 1 GHz, you can timing
    intervals in 1 ns steps. With a 48 bit synchronous down counter, you
    can get timing intervals of several days with 1 ns timing steps. Some >>trickery is needed to avoid running all 48 stages at full ECL speed.

    I can't do that in an FPGA. And resolution is mediocre around 10 MHz.

    Use a fast 8 bit down counter followed by a slow 40 bit down counter.
    If the fast counter is run at 1 GHz (1 ns), the slow counter only
    runs at 4 MHz. When the slow down counter reaches 0x0000000000, it can
    start reloading the preset value. At that time the fast counter is at
    0xFF and it takes 256 ns before reaching zero and doing the preset. At
    that time the slow counter has already been reloaded and it can start
    counting as soon as the preset fast counter reaches 0 the next time.

    <snip>

    But the real question is, do you really need nanosecond step size in >>minutes, hours or day time scale ?

    A straightforward DDS will have tons of period jitter at low
    frequencies, which is ugly.

    Then do not use DDS directly for very low frequencies.

    And some customers whine if we stop
    triggering while we reprogram a DDS (or a synth chip) and a divisor.

    Reprogramming DDS = loading a new addend value into the DDS. After
    that the phase accumulator increases more or less rapidly, so quite
    hard to even detect in a short time.

    Admittedly, the 1 ns timing step is quite coarse at short pulses, inn
    which only 1 ns, 2 ns, 3 ns, 4 ns and so on is available, so a DDS
    might be justified to get 1 ps timing steps. But for longer times,
    say 1 us (1 MHz) or 1 ms (1 kHz), why not put a divide-by-N divider
    after the DDS ? Combining the DDS and divide-by-N programming, quite >>strange periods can be obtained.

    If you have a DDS for periods shorter than 1 s, you could add a
    divide-by-N for longer periods. Each time the divide-by-N reaches 0,
    you could enable the DDS addend loading, thus the timing would be
    quite clean, even for a time sweep. Of course, this will require
    precalculating the DDS addend and the divide-by-N before the divider
    expires, but a very primitive CPU could do it before a sweep or other predictable sequence.

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  • From John Miles, KE5FX@21:1/5 to Mike Monett on Sat Aug 13 16:42:36 2022
    On Friday, August 12, 2022 at 9:08:27 AM UTC-7, Mike Monett wrote:
    A New Frequency Synthesis Technique
    . . .
    The description of Rational Approximation Synthesis starts on page 151. A block diagram is on page 156.

    Amusing. That wasn't exactly 'new' when I implemented it in 2002 or so.
    ( http://www.ke5fx.com/synth.html ) It was probably still covered
    by one Qualcomm patent or another at the time, in retrospect.

    I used a crystal filter rather than a narrowband VCXO, but same difference.

    -- john, KE5FX

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  • From John Miles, KE5FX@21:1/5 to Mike Monett on Sat Aug 13 20:40:36 2022
    On Saturday, August 13, 2022 at 8:18:00 PM UTC-7, Mike Monett wrote:
    Amazing documentation. Thanks.

    Pretty awful synthesizer design, though. :)

    -- john, KE5FX

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  • From Mike Monett@21:1/5 to jmiles@gmail.com on Sun Aug 14 03:17:52 2022
    "John Miles, KE5FX" <jmiles@gmail.com> wrote:

    On Friday, August 12, 2022 at 9:08:27 AM UTC-7, Mike Monett wrote:
    A New Frequency Synthesis Technique
    . . .
    The description of Rational Approximation Synthesis starts on page 151. A
    block diagram is on page 156.

    Amusing. That wasn't exactly 'new' when I implemented it in 2002 or so.
    ( http://www.ke5fx.com/synth.html ) It was probably still covered
    by one Qualcomm patent or another at the time, in retrospect.

    I used a crystal filter rather than a narrowband VCXO, but same difference.

    -- john, KE5FX

    Amazing documentation. Thanks.

    Mike



    --
    MRM

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  • From Mike Monett@21:1/5 to jmiles@gmail.com on Sun Aug 14 04:24:14 2022
    "John Miles, KE5FX" <jmiles@gmail.com> wrote:

    On Saturday, August 13, 2022 at 8:18:00 PM UTC-7, Mike Monett wrote:
    Amazing documentation. Thanks.

    Pretty awful synthesizer design, though. :)

    -- john, KE5FX

    The performance is clearly superior to the ICOM. Congratulations.

    I am absolutely amazed by the quantity and quality of your documentation.
    This would take a normal human a year to complete.



    --
    MRM

    --- SoupGate-Win32 v1.05
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  • From John Miles, KE5FX@21:1/5 to Mike Monett on Sat Aug 13 22:22:51 2022
    On Saturday, August 13, 2022 at 9:24:21 PM UTC-7, Mike Monett wrote:
    I am absolutely amazed by the quantity and quality of your documentation. This would take a normal human a year to complete.

    Thanks! There was lots of room for improvement (the crystal filter/
    comparator section is just embarrassing) but it performed well
    on a $/dBc/Hz basis. And it did made a very nice article for QEX.

    Nowadays, all that stuff fits on a single IC and provides 20 GHz of
    coverage with far less noise of both white and flicker varieties. Of
    course the best chips are unobtainium TI parts that have to be sourced
    from Chinese scalpers at prices well into the 3-digit range, but that seems
    to be the new way of the world.

    -- john, KE5FX

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  • From Mike Monett@21:1/5 to jmiles@gmail.com on Sun Aug 14 06:04:00 2022
    "John Miles, KE5FX" <jmiles@gmail.com> wrote:

    On Saturday, August 13, 2022 at 9:24:21 PM UTC-7, Mike Monett wrote:
    I am absolutely amazed by the quantity and quality of your
    documentation. This would take a normal human a year to complete.

    Thanks! There was lots of room for improvement (the crystal filter/ comparator section is just embarrassing) but it performed well
    on a $/dBc/Hz basis. And it did made a very nice article for QEX.

    Nowadays, all that stuff fits on a single IC and provides 20 GHz of
    coverage with far less noise of both white and flicker varieties. Of
    course the best chips are unobtainium TI parts that have to be sourced
    from Chinese scalpers at prices well into the 3-digit range, but that
    seems to be the new way of the world.

    -- john, KE5FX

    I'm interested. Can you name some of the best and who sells them?




    --
    MRM

    --- SoupGate-Win32 v1.05
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  • From John Miles, KE5FX@21:1/5 to Mike Monett on Sun Aug 14 00:19:53 2022
    On Saturday, August 13, 2022 at 11:04:08 PM UTC-7, Mike Monett wrote:
    I'm interested. Can you name some of the best and who sells them?

    LMX2820 (TI) and 8V97003 (Renesas) are two of the best integrated
    PLL/VCO parts I've seen. The LMX2595 has similar specs but the
    LMX2820 has some nice advantages, such as lower flicker noise and
    the ability to drive both phase detector inputs externally.

    Look them up on octopart.com and you'll see that they are all
    sitting in Chinese warehouses by the tens of thousands, waiting for
    buyers who don't mind paying 4x-5x MSRP.

    ADF4371 (62.5 MHz - 32 GHz) also looks good. Some stock left at
    Mouser.

    Of all these parts, I've only messed with the LMX2820 in person.
    I have a demo board for the Renesas part but haven't gotten
    around to powering it up and trying it out yet.

    -- john, KE5FX

    --- SoupGate-Win32 v1.05
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  • From Gerhard Hoffmann@21:1/5 to All on Sun Aug 14 13:07:50 2022
    Am 14.08.22 um 09:19 schrieb John Miles, KE5FX:
    On Saturday, August 13, 2022 at 11:04:08 PM UTC-7, Mike Monett wrote:
    I'm interested. Can you name some of the best and who sells them?

    LMX2820 (TI) and 8V97003 (Renesas) are two of the best integrated
    PLL/VCO parts I've seen. The LMX2595 has similar specs but the
    LMX2820 has some nice advantages, such as lower flicker noise and
    the ability to drive both phase detector inputs externally.


    I have published a synthesizer based on LMX2594 (15 GHz) in
    Dubus 1/22. I will put it on my web site sooner or later, but
    the chip is currently vapourware.
    <
    https://www.flickr.com/photos/137684711@N07/51691780129/in/datetaken/ >

    <
    https://www.flickr.com/photos/137684711@N07/51519856398/in/dateposted-public/
    >

    There is 1 hittite HMC-451 output amplifier populated to drive
    a HMC-220 ring mixer. The TI dongle & software cannot tell
    it from an eval board.


    There will be a companion clock generator with either a
    100 MHz crystal oven or a CVHD-950. The oven/VCXO can be locked
    to an external 10 MHz reference. It delivers
    300 MHz for LMX2594 in fractional mode or
    400 MHz for LMX2594 in integer mode.

    400 MHz uses 2 SAW filters after the multiplier,
    300 MHz uses 2*3pole LC, top coupled.
    I could not find a nice 300 MHz SAW filter that is not EOL
    or has less than 10 dB loss.

    A previous version had some 10 MHz spurious from
    the 1/10 prescaler. It also had only 300 MHz.

    < https://www.flickr.com/photos/137684711@N07/52284841519/in/dateposted-public/lightbox/
    >

    It could be used for a DDS also, but currently there is no
    need to rush it because of the 2594.


    Look them up on octopart.com and you'll see that they are all
    sitting in Chinese warehouses by the tens of thousands, waiting for
    buyers who don't mind paying 4x-5x MSRP.

    ADF4371 (62.5 MHz - 32 GHz) also looks good. Some stock left at
    Mouser.

    At least it has some filtering after the output doubler.
    The ADF5356 had a subharmonic that was horrible.

    <
    https://www.flickr.com/photos/137684711@N07/50403778976/in/dateposted-public/
    >

    If someone wants to play with these things, there are enough
    boards. Hot air soldering is required, minimum.

    cheers,
    Gerhard DK4XP

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  • From Mike Monett@21:1/5 to jmiles@gmail.com on Sun Aug 14 13:40:51 2022
    "John Miles, KE5FX" <jmiles@gmail.com> wrote:

    On Saturday, August 13, 2022 at 11:04:08 PM UTC-7, Mike Monett wrote:
    I'm interested. Can you name some of the best and who sells them?

    LMX2820 (TI) and 8V97003 (Renesas) are two of the best integrated
    PLL/VCO parts I've seen. The LMX2595 has similar specs but the
    LMX2820 has some nice advantages, such as lower flicker noise and
    the ability to drive both phase detector inputs externally.

    Look them up on octopart.com and you'll see that they are all
    sitting in Chinese warehouses by the tens of thousands, waiting for
    buyers who don't mind paying 4x-5x MSRP.

    ADF4371 (62.5 MHz - 32 GHz) also looks good. Some stock left at
    Mouser.

    Of all these parts, I've only messed with the LMX2820 in person.
    I have a demo board for the Renesas part but haven't gotten
    around to powering it up and trying it out yet.

    -- john, KE5FX

    Very good info. Thanks



    --
    MRM

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Mike Monett@21:1/5 to Gerhard Hoffmann on Sun Aug 14 13:44:30 2022
    Gerhard Hoffmann <dk4xp@arcor.de> wrote:

    [...]


    If someone wants to play with these things, there are enough
    boards. Hot air soldering is required, minimum.

    cheers,
    Gerhard DK4XP

    Very interesting. Thanks

    Mike VE3BTI




    --
    MRM

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  • From jlarkin@highlandsniptechnology.com@21:1/5 to jmiles@gmail.com on Sun Aug 14 09:21:42 2022
    On Sun, 14 Aug 2022 00:19:53 -0700 (PDT), "John Miles, KE5FX" <jmiles@gmail.com> wrote:

    On Saturday, August 13, 2022 at 11:04:08 PM UTC-7, Mike Monett wrote:
    I'm interested. Can you name some of the best and who sells them?

    LMX2820 (TI) and 8V97003 (Renesas) are two of the best integrated
    PLL/VCO parts I've seen. The LMX2595 has similar specs but the
    LMX2820 has some nice advantages, such as lower flicker noise and
    the ability to drive both phase detector inputs externally.

    Look them up on octopart.com and you'll see that they are all
    sitting in Chinese warehouses by the tens of thousands, waiting for
    buyers who don't mind paying 4x-5x MSRP.

    ADF4371 (62.5 MHz - 32 GHz) also looks good. Some stock left at
    Mouser.

    Of all these parts, I've only messed with the LMX2820 in person.
    I have a demo board for the Renesas part but haven't gotten
    around to powering it up and trying it out yet.

    -- john, KE5FX

    We use the LMX2571 as the internal trigger generator in one product.
    Jitter is great. It was a huge pain to program, as TI doesn't reveal
    the code that they use in the demo kit. Everybody has to figure it out
    for themselves. The data sheet is 62 pages long and the app note is
    another 31.

    We have to suspend triggers while reprogramming the synth, which some
    users don't like.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)