• 6 bit things

    From jlarkin@highlandsniptechnology.com@21:1/5 to All on Wed Aug 3 08:52:08 2022
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Clive Arthur@21:1/5 to jlarkin@highlandsniptechnology.com on Wed Aug 3 16:58:49 2022
    On 03/08/2022 16:52, jlarkin@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.


    The French (and maybe others) use 'octet' for byte, so 'sextet' sounds reasonable.

    I use 'nips' for two bits, don't know if anyone else does.

    --
    Cheers
    Clive

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  • From jlarkin@highlandsniptechnology.com@21:1/5 to martin_riddle@verison.net on Wed Aug 3 09:14:53 2022
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
    <martin_riddle@verison.net> wrote:

    jlarkin@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers

    Maybe "frame" sounds better than "clump."

    --- SoupGate-Win32 v1.05
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  • From Martin Rid@21:1/5 to jlarkin@highlandsniptechnology.com on Wed Aug 3 12:03:11 2022
    jlarkin@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers
    --


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  • From Dan Purgert@21:1/5 to jlarkin@highlandsniptechnology.com on Wed Aug 3 16:51:57 2022
    -----BEGIN PGP SIGNED MESSAGE-----
    Hash: SHA512

    jlarkin@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    As of sometime in the early-mid 1990s ('94?), "Byte" is 8 bits.
    Historically, different terms were used ("word" , "syllable", etc.), and represented some contiguous set of bits that wasn't necessarily 8 -- for example 6, 12, or 18 bits. As far as I am aware, these were not industry-standard terms, and therefore the bit-width would vary between vendors.

    As far as I am aware, the only modern subdivisions of a Byte are

    - bit (1/8 Byte)
    - nybble (1/2 Byte)

    There's probably some ISO standard document somewhere that defines all
    of this these days. :)


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    It is my understanding that an SFP tranceiver is somewhat akin to an
    RS485 tranceiver, in that it doesn't particularly "care" about what
    you're kicking out "over the wire". Rather, it is up to the
    sending/receiving party to agree on a protocol for the data framing.

    That being said; I'm mainly familiar with their use in IEEE 802.3
    (Ethernet) networking, and not really outside of that context; so take
    the above with a grain of salt.

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    |_|O|_|
    |_|_|O| Github: https://github.com/dpurgert
    |O|O|O| PGP: DDAB 23FB 19FA 7D85 1CC1 E067 6D65 70E5 4CE7 2860

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  • From Joe Gwinn@21:1/5 to All on Wed Aug 3 12:35:16 2022
    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com
    wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was
    whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in
    bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in
    size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so
    ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use
    only the DC balanced subset, does that suffice?

    Or, turn it around. Figure out how many DC-balanced patterns you
    need, double it (for growth), and figure out long a word is needed.
    Don't forget to include some control patterns.

    Gigabit Ethernet does something like this, only grander, with two
    patterns for every possible symbol to be sent, and they track current
    DC balance, and choose which pattern to use that will reduce the
    running DC balance.

    Joe Gwinn

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  • From John Walliker@21:1/5 to Dan Purgert on Wed Aug 3 10:12:10 2022
    On Wednesday, 3 August 2022 at 17:52:04 UTC+1, Dan Purgert wrote:

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.
    It is my understanding that an SFP tranceiver is somewhat akin to an
    RS485 tranceiver, in that it doesn't particularly "care" about what
    you're kicking out "over the wire". Rather, it is up to the
    sending/receiving party to agree on a protocol for the data framing.

    SFP transceivers are capacitor coupled on input and output so they do
    care about the dc balance of the signal. I believe that there is also capacitor coupling in the photodetector circuit. They don't care about
    the exact protocol however.

    John

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  • From John Walliker@21:1/5 to jla...@highlandsniptechnology.com on Wed Aug 3 09:57:35 2022
    On Wednesday, 3 August 2022 at 17:15:04 UTC+1, jla...@highlandsniptechnology.com wrote:
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
    <martin...@verison.net> wrote:

    jla...@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers
    Maybe "frame" sounds better than "clump."

    From https://en.wikipedia.org/wiki/Byte

    The size of the byte has historically been hardware-dependent and no definitive standards existed that
    mandated the size. Sizes from 1 to 48 bits have been used.[4][5][6][7] The six-bit character code was an
    often-used implementation in early encoding systems, and computers using six-bit and nine-bit bytes
    were common in the 1960s. These systems often had memory words of 12, 18, 24, 30, 36, 48, or 60 bits,
    corresponding to 2, 3, 4, 5, 6, 8, or 10 six-bit bytes. In this era, bit groupings in the instruction stream were
    often referred to as syllables[a] or slab, before the term byte became common.

    I also like the sound of sextet. Its easy to say out loud and gives a strong hint at the meaning.

    John

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  • From Dimiter_Popoff@21:1/5 to Clive Arthur on Wed Aug 3 20:15:05 2022
    On 8/3/2022 18:58, Clive Arthur wrote:
    On 03/08/2022 16:52, jlarkin@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

        0 1 1 0 d \d   repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.


    The French (and maybe others) use 'octet' for byte, so 'sextet' sounds reasonable.

    I use 'nips' for two bits, don't know if anyone else does.


    And others indeed. All the RFC-s I have read use "octet", apparently
    a byte has not always been used meaning 8 bits. So the IETF have taken
    the decision quite a while ago.

    I'd go with "sextet", although since during programming it will
    typically be part of a byte I'd comment "lowest 6 bits" or something.

    --- SoupGate-Win32 v1.05
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  • From John Larkin@21:1/5 to All on Wed Aug 3 10:19:49 2022
    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com
    wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was
    whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in
    bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in
    size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so
    ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use
    only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and
    receive. I'm thinking about a spare-time thing that I could design
    without an FPGA or uP, all hardware. My digital people are swamped
    with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you
    need, double it (for growth), and figure out long a word is needed.
    Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to
    transport it over fiber, and SFP is the easy way to do that. But SFP
    is intended for telecom, ac coupled, intolerant of dc imbalance. Most
    SFPs won't pass anything below about 1 MHz. But they are crazy fast
    and have great AGC.


    Gigabit Ethernet does something like this, only grander, with two
    patterns for every possible symbol to be sent, and they track current
    DC balance, and choose which pattern to use that will reduce the
    running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work.

    SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
    35% to 65%.


    Joe Gwinn

    --- SoupGate-Win32 v1.05
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  • From Fred Bloggs@21:1/5 to jla...@highlandsniptechnology.com on Wed Aug 3 10:31:48 2022
    On Wednesday, August 3, 2022 at 11:52:21 AM UTC-4, jla...@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    It's a hexad.

    --- SoupGate-Win32 v1.05
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  • From Phil Hobbs@21:1/5 to jlarkin@highlandsniptechnology.com on Wed Aug 3 14:28:30 2022
    jlarkin@highlandsniptechnology.com wrote:
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid <martin_riddle@verison.net> wrote:

    jlarkin@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers

    Maybe "frame" sounds better than "clump."



    Or 'clod'. Alternatives abound. ;)

    I'd go with sextet (or sestet, if you're feeling poetic).

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

    --- SoupGate-Win32 v1.05
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  • From Martin Rid@21:1/5 to jlarkin@highlandsniptechnology.com on Wed Aug 3 16:07:04 2022
    jlarkin@highlandsniptechnology.com Wrote in message:r
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid<martin_riddle@verison.net> wrote:>jlarkin@highlandsniptechnology.com Wrote in message:r>> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link,
    in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.>>I would still consider it a byte, but sixbit.>You could always call it braille. >>CheersMaybe "frame" sounds better than "clump."

    Sixbit packet
    And call it a day.

    Cheers
    --


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  • From John Walliker@21:1/5 to Cydrome Leader on Wed Aug 3 13:15:09 2022
    On Wednesday, 3 August 2022 at 21:09:20 UTC+1, Cydrome Leader wrote:
    jla...@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.
    six bit word.

    After all this discussion it occurs to me that the correct answer is a bit.
    The 0110 is a dc balanced header and the d \d is just a coding scheme
    that ensures dc balance without conveying more than 1 bit of information.

    John

    --- SoupGate-Win32 v1.05
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  • From Cydrome Leader@21:1/5 to jlarkin@highlandsniptechnology.com on Wed Aug 3 20:09:15 2022
    jlarkin@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to martin_riddle@verison.net on Wed Aug 3 13:20:06 2022
    On Wed, 3 Aug 2022 16:07:04 -0400 (EDT), Martin Rid
    <martin_riddle@verison.net> wrote:

    jlarkin@highlandsniptechnology.com Wrote in message:r
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid<martin_riddle@verison.net> wrote:>jlarkin@highlandsniptechnology.com Wrote in message:r>> Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link,
    in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.>>I would still consider it a byte, but sixbit.>You could always call it braille. >>CheersMaybe "frame" sounds better than "clump."

    Sixbit packet
    And call it a day.

    Cheers

    Sixpack.

    --- SoupGate-Win32 v1.05
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  • From John Larkin@21:1/5 to pcdhSpamMeSenseless@electrooptical. on Wed Aug 3 13:29:45 2022
    On Wed, 3 Aug 2022 14:28:30 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    jlarkin@highlandsniptechnology.com wrote:
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
    <martin_riddle@verison.net> wrote:

    jlarkin@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers

    Maybe "frame" sounds better than "clump."



    Or 'clod'. Alternatives abound. ;)

    I'd go with sextet (or sestet, if you're feeling poetic).

    Cheers

    Phil Hobbs

    Now one of my guys claims that all we need is

    1 0 d1 \d1 1 0 d2 \d2 .... etc

    four bits per chunk to recover data d. Which is a nibble. I can still
    call each 4 bits a frame.

    I hate it when people are smarter than I am.

    --- SoupGate-Win32 v1.05
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  • From Joe Gwinn@21:1/5 to jlarkin@highland_atwork_technology. on Wed Aug 3 16:32:53 2022
    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin <jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com >>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in
    bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in
    size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so
    ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use
    only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and
    receive. I'm thinking about a spare-time thing that I could design
    without an FPGA or uP, all hardware. My digital people are swamped
    with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you
    need, double it (for growth), and figure out long a word is needed.
    Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to
    transport it over fiber, and SFP is the easy way to do that. But SFP
    is intended for telecom, ac coupled, intolerant of dc imbalance. Most
    SFPs won't pass anything below about 1 MHz. But they are crazy fast
    and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    What is being digitized? Voice? Data of some kind?

    Is there a maximum latency and latency jitter requirement?

    One-bit delta samples are usually signed, so the minimum is two
    symbols. If the voltage being sent is zero, then we'll get a steady
    +,-,+,-,+, stream, which will have very strong RF spurs and thus
    emissions, so need to break this up.

    A zero symbol makes it three, and an idle symbol, makes it four
    symbols.


    Gigabit Ethernet does something like this, only grander, with two
    patterns for every possible symbol to be sent, and they track current
    DC balance, and choose which pattern to use that will reduce the
    running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work.

    SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
    35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close
    enough.

    For instance, have four tables (one per symbol), with unique random
    patterns, and choose a pattern from the correct table for the symbol
    to be sent. These patterns are all inherently DC balanced, being half
    + and half -, and don't have any long runs.

    On the receive end, use table lookup to recover the sent symbols.

    You will need a sync pattern to establish and maintain symbol framing.
    The key property of sync patterns is a sharp single correlation peak
    against shifted examples of that pattern. A sync preamble may be
    multiple sync symbols concatenated. Sync and idle symbols may be the
    same.


    Joe Gwinn

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  • From Martin Brown@21:1/5 to Cydrome Leader on Wed Aug 3 21:52:43 2022
    On 03/08/2022 21:09, Cydrome Leader wrote:
    jlarkin@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.

    MIX - for the model 1009 Knuth polyunsaturated virtual computer used 6
    bit bytes and 5 bytes to a word in TAOCP. It was partly intended to
    break any algorithm that relied on things being a handy power of two.


    --
    Regards,
    Martin Brown

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  • From John Walliker@21:1/5 to Martin Brown on Wed Aug 3 14:04:06 2022
    On Wednesday, 3 August 2022 at 21:52:50 UTC+1, Martin Brown wrote:
    On 03/08/2022 21:09, Cydrome Leader wrote:
    jla...@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.
    MIX - for the model 1009 Knuth polyunsaturated virtual computer used 6
    bit bytes and 5 bytes to a word in TAOCP. It was partly intended to
    break any algorithm that relied on things being a handy power of two.

    I never had enough bookshelf space - or money at the time - for the complete works of Knuth. I don't know how he managed to do so much!

    John

    --- SoupGate-Win32 v1.05
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  • From Ricky@21:1/5 to John Larkin on Wed Aug 3 14:06:15 2022
    On Wednesday, August 3, 2022 at 4:29:56 PM UTC-4, John Larkin wrote:
    On Wed, 3 Aug 2022 14:28:30 -0400, Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:

    jla...@highlandsniptechnology.com wrote:
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
    <martin...@verison.net> wrote:

    jla...@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers

    Maybe "frame" sounds better than "clump."



    Or 'clod'. Alternatives abound. ;)

    I'd go with sextet (or sestet, if you're feeling poetic).

    Cheers

    Phil Hobbs
    Now one of my guys claims that all we need is

    1 0 d1 \d1 1 0 d2 \d2 .... etc

    four bits per chunk to recover data d. Which is a nibble. I can still
    call each 4 bits a frame.

    I hate it when people are smarter than I am.

    That will only sync if your data changes. If your data stream has a sequence of ones, the data and sync can't be distinguished until a zero is sent. You will need a three bit sync pattern for that, or you don't need to send the sync for every bit.

    If you are ok with data dependencies for aligning to the data, then simply sending d and /d as a pair is easily synchronized to at any data transition. Hmmm.... d,/d,d,/d Where have I seen that before??? I'm picturing a place in the UK.

    Why reinvent the wheel? This doesn't even require a separate clock!

    --

    Rick C.

    + Get 1,000 miles of free Supercharging
    + Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to '''newspam'''@nonad.co.uk on Wed Aug 3 14:35:37 2022
    On Wed, 3 Aug 2022 21:52:43 +0100, Martin Brown
    <'''newspam'''@nonad.co.uk> wrote:

    On 03/08/2022 21:09, Cydrome Leader wrote:
    jlarkin@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.

    MIX - for the model 1009 Knuth polyunsaturated virtual computer used 6
    bit bytes and 5 bytes to a word in TAOCP. It was partly intended to
    break any algorithm that relied on things being a handy power of two.

    There's no point in a challenge to design the worst CPU architecture,
    since it's been done so many times already.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Wed Aug 3 14:48:12 2022
    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin ><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com >>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in
    bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in
    size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so
    ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use
    only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and
    receive. I'm thinking about a spare-time thing that I could design
    without an FPGA or uP, all hardware. My digital people are swamped
    with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you
    need, double it (for growth), and figure out long a word is needed.
    Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to
    transport it over fiber, and SFP is the easy way to do that. But SFP
    is intended for telecom, ac coupled, intolerant of dc imbalance. Most
    SFPs won't pass anything below about 1 MHz. But they are crazy fast
    and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to
    do that. 10M would be plenty.


    What is being digitized? Voice? Data of some kind?

    Some customer's analog voltage. Might be a strain gage load cell, for
    example. We'd have some input ranges.


    Is there a maximum latency and latency jitter requirement?

    Neither, actually. I just want to transport the ADC output correctly.


    One-bit delta samples are usually signed, so the minimum is two
    symbols. If the voltage being sent is zero, then we'll get a steady >+,-,+,-,+, stream, which will have very strong RF spurs and thus
    emissions, so need to break this up.

    The ADC has a one-bit output over +-320 mV input, and averages 50%
    duty cycle at 0 volts in. I just want to transport that bit over a
    fiber link.



    A zero symbol makes it three, and an idle symbol, makes it four
    symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>patterns for every possible symbol to be sent, and they track current
    DC balance, and choose which pattern to use that will reduce the
    running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work.

    SFPs usually tolerate a little DC imbalance. You can send PWM at, say,
    35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >enough.

    I don't want an FPGA or a uP in this box. All my coder-people are too
    busy on other projects now. So, a few gates and flipflops.


    For instance, have four tables (one per symbol), with unique random
    patterns, and choose a pattern from the correct table for the symbol
    to be sent. These patterns are all inherently DC balanced, being half
    + and half -, and don't have any long runs.

    On the receive end, use table lookup to recover the sent symbols.

    You will need a sync pattern to establish and maintain symbol framing.
    The key property of sync patterns is a sharp single correlation peak
    against shifted examples of that pattern. A sync preamble may be
    multiple sync symbols concatenated. Sync and idle symbols may be the
    same.


    Joe Gwinn

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  • From Ricky@21:1/5 to John Larkin on Wed Aug 3 14:58:10 2022
    On Wednesday, August 3, 2022 at 5:48:23 PM UTC-4, John Larkin wrote:
    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin ><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joeg...@comcast.net> >>wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com >>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in >>>bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in >>>size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so >>>ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use >>>only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and
    receive. I'm thinking about a spare-time thing that I could design >>without an FPGA or uP, all hardware. My digital people are swamped
    with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you
    need, double it (for growth), and figure out long a word is needed. >>>Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to >>transport it over fiber, and SFP is the easy way to do that. But SFP
    is intended for telecom, ac coupled, intolerant of dc imbalance. Most >>SFPs won't pass anything below about 1 MHz. But they are crazy fast
    and have great AGC.

    Is it 100 million bits per second, or symbols per second?
    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to
    do that. 10M would be plenty.

    What is being digitized? Voice? Data of some kind?
    Some customer's analog voltage. Might be a strain gage load cell, for example. We'd have some input ranges.

    Is there a maximum latency and latency jitter requirement?
    Neither, actually. I just want to transport the ADC output correctly.

    One-bit delta samples are usually signed, so the minimum is two
    symbols. If the voltage being sent is zero, then we'll get a steady >+,-,+,-,+, stream, which will have very strong RF spurs and thus
    emissions, so need to break this up.
    The ADC has a one-bit output over +-320 mV input, and averages 50%
    duty cycle at 0 volts in. I just want to transport that bit over a
    fiber link.

    A zero symbol makes it three, and an idle symbol, makes it four
    symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>patterns for every possible symbol to be sent, and they track current >>>DC balance, and choose which pattern to use that will reduce the >>>running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work.

    SFPs usually tolerate a little DC imbalance. You can send PWM at, say, >>35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >enough.
    I don't want an FPGA or a uP in this box. All my coder-people are too
    busy on other projects now. So, a few gates and flipflops.

    Manchester encoding is one of the simplest things in the world to decode. It's also very easy to encode. Look it up. You'll be surprised at how easy it is.

    --

    Rick C.

    - Get 1,000 miles of free Supercharging
    - Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From bitrex@21:1/5 to Cydrome Leader on Wed Aug 3 18:27:52 2022
    On 8/3/2022 4:09 PM, Cydrome Leader wrote:
    jlarkin@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.

    Have you heard the song that's just six words long:

    <https://youtu.be/SIIvJkSLSfw>

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  • From Ricky@21:1/5 to bitrex on Wed Aug 3 16:24:06 2022
    On Wednesday, August 3, 2022 at 6:28:11 PM UTC-4, bitrex wrote:
    On 8/3/2022 4:09 PM, Cydrome Leader wrote:
    jla...@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.
    Have you heard the song that's just six words long:

    <https://youtu.be/SIIvJkSLSfw>

    The refrain was seven words actually, so not DC balanced.

    --

    Rick C.

    -- Get 1,000 miles of free Supercharging
    -- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jasen Betts@21:1/5 to jlarkin@highlandsniptechnology.com on Thu Aug 4 06:21:33 2022
    On 2022-08-03, jlarkin@highlandsniptechnology.com <jlarkin@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM

    is DC balanced, which SFP likes.

    seems heavy on clock and light on data. I'd call that a symbol.


    Is there a better term for the code used to control WS2812 leds than
    one bit PWM?
    --
    Jasen.

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  • From Martin Brown@21:1/5 to John Walliker on Thu Aug 4 11:16:01 2022
    On 03/08/2022 22:04, John Walliker wrote:
    On Wednesday, 3 August 2022 at 21:52:50 UTC+1, Martin Brown wrote:
    On 03/08/2022 21:09, Cydrome Leader wrote:
    jla...@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.
    MIX - for the model 1009 Knuth polyunsaturated virtual computer used 6
    bit bytes and 5 bytes to a word in TAOCP. It was partly intended to
    break any algorithm that relied on things being a handy power of two.

    I never had enough bookshelf space - or money at the time - for the complete works of Knuth. I don't know how he managed to do so much!

    You can always add more bookshelves...

    My friend and I got Volume I Fundamental Algorithms as undergraduates
    and worked through most of the problems including implementing a virtual
    Mix machine. We even found a bug in the prime number test example and
    sent it off hoping for 2^N dollars in return. It had already been
    reported so we just got a nice postcard back from him instead.

    Someone borrowed my copy of Seminumerical Algorithms and never gave it
    back. I never did get to Sorting and Searching (my friend did).

    LaTex markup language remains as one of the side effects of Knuth
    finding no suitable markup language for such documents.

    ISTR Roff on Unix or the IBM mainframe was the least unsuitable option
    at the time and later something odd and nearly Wysiwyg (but not quite)
    from Manchester University running on a Sirius PC as a word processor.

    https://en.wikipedia.org/wiki/Sirius_Systems_Technology

    --
    Regards,
    Martin Brown

    --- SoupGate-Win32 v1.05
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  • From John May@21:1/5 to Martin Brown on Thu Aug 4 03:26:23 2022
    On Thursday, August 4, 2022 at 11:16:11 AM UTC+1, Martin Brown wrote:
    On 03/08/2022 22:04, John Walliker wrote:
    On Wednesday, 3 August 2022 at 21:52:50 UTC+1, Martin Brown wrote:
    On 03/08/2022 21:09, Cydrome Leader wrote:
    jla...@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.
    MIX - for the model 1009 Knuth polyunsaturated virtual computer used 6
    bit bytes and 5 bytes to a word in TAOCP. It was partly intended to
    break any algorithm that relied on things being a handy power of two.

    I never had enough bookshelf space - or money at the time - for the complete
    works of Knuth. I don't know how he managed to do so much!
    You can always add more bookshelves...

    My friend and I got Volume I Fundamental Algorithms as undergraduates
    and worked through most of the problems including implementing a virtual
    Mix machine. We even found a bug in the prime number test example and
    sent it off hoping for 2^N dollars in return. It had already been
    reported so we just got a nice postcard back from him instead.

    Someone borrowed my copy of Seminumerical Algorithms and never gave it
    back. I never did get to Sorting and Searching (my friend did).

    LaTex markup language remains as one of the side effects of Knuth
    finding no suitable markup language for such documents.

    ISTR Roff on Unix or the IBM mainframe was the least unsuitable option
    at the time and later something odd and nearly Wysiwyg (but not quite)
    from Manchester University running on a Sirius PC as a word processor.

    https://en.wikipedia.org/wiki/Sirius_Systems_Technology

    --
    Regards,
    Martin Brown

    I think Leslie Lamport deserves a bit of a shout for LaTeX :-)

    I was quite attracted to Knuth's literate programming ideas for a while, but in multi programmer projects the approach was allways rejected.

    --- SoupGate-Win32 v1.05
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  • From TTman@21:1/5 to jlarkin@highlandsniptechnology.com on Thu Aug 4 11:22:57 2022
    On 03/08/2022 16:52, jlarkin@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    A byte with 2 null bits...

    --
    This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus

    --- SoupGate-Win32 v1.05
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  • From Jeroen Belleman@21:1/5 to Martin Brown on Thu Aug 4 14:39:41 2022
    Martin Brown wrote:
    On 03/08/2022 22:04, John Walliker wrote:
    On Wednesday, 3 August 2022 at 21:52:50 UTC+1, Martin Brown wrote:
    On 03/08/2022 21:09, Cydrome Leader wrote:
    jla...@highlandsniptechnology.com wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    six bit word.
    MIX - for the model 1009 Knuth polyunsaturated virtual computer used 6
    bit bytes and 5 bytes to a word in TAOCP. It was partly intended to
    break any algorithm that relied on things being a handy power of two.

    I never had enough bookshelf space - or money at the time - for the
    complete
    works of Knuth. I don't know how he managed to do so much!

    You can always add more bookshelves...

    My friend and I got Volume I Fundamental Algorithms as undergraduates
    and worked through most of the problems including implementing a virtual
    Mix machine. We even found a bug in the prime number test example and
    sent it off hoping for 2^N dollars in return. It had already been
    reported so we just got a nice postcard back from him instead.

    Someone borrowed my copy of Seminumerical Algorithms and never gave it
    back. I never did get to Sorting and Searching (my friend did).

    LaTex markup language remains as one of the side effects of Knuth
    finding no suitable markup language for such documents.

    ISTR Roff on Unix or the IBM mainframe was the least unsuitable option
    at the time and later something odd and nearly Wysiwyg (but not quite)
    from Manchester University running on a Sirius PC as a word processor.

    https://en.wikipedia.org/wiki/Sirius_Systems_Technology


    You can't deny that LaTeX makes beautiful documents, and it will
    never trash your source files, contrary to some other piece of
    $oftware we all love to hate. It sure is weird though.

    And don't believe the statement that you can concentrate on
    contents and forget about the formatting. Still, it's my first
    choice for slides and text documents, if the choice is mine.

    Jeroen Belleman

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  • From Dan Purgert@21:1/5 to Jeroen Belleman on Thu Aug 4 14:37:46 2022
    -----BEGIN PGP SIGNED MESSAGE-----
    Hash: SHA512

    Jeroen Belleman wrote:
    Martin Brown wrote:
    [...]
    LaTex markup language remains as one of the side effects of Knuth
    finding no suitable markup language for such documents.

    You can't deny that LaTeX makes beautiful documents, and it will
    never trash your source files, contrary to some other piece of
    $oftware we all love to hate. It sure is weird though.

    And don't believe the statement that you can concentrate on
    contents and forget about the formatting. Still, it's my first
    choice for slides and text documents, if the choice is mine.

    For the most part, I find that statement to be true. That is not to say
    there are never cases where I'm looking at a page and shifting an image
    or something around; but it always feels more like an aesthetic "last
    step". On the other hand, WYSIWYG editors kind of force one to "format"
    as they go, which can cause some headaches / loss of momentum in the
    writing.


    -----BEGIN PGP SIGNATURE-----

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    --
    |_|O|_|
    |_|_|O| Github: https://github.com/dpurgert
    |O|O|O| PGP: DDAB 23FB 19FA 7D85 1CC1 E067 6D65 70E5 4CE7 2860

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  • From John Larkin@21:1/5 to usenet@revmaps.no-ip.org on Thu Aug 4 10:00:08 2022
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <usenet@revmaps.no-ip.org> wrote:

    On 2022-08-03, jlarkin@highlandsniptechnology.com <jlarkin@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM

    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's terrifyingly clever.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jlarkin@highland_atwork_technology. on Thu Aug 4 16:40:53 2022
    On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin <jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin >><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net> >>>wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com >>>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in >>>>bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in >>>>size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so >>>>ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use >>>>only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and
    receive. I'm thinking about a spare-time thing that I could design >>>without an FPGA or uP, all hardware. My digital people are swamped
    with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you
    need, double it (for growth), and figure out long a word is needed. >>>>Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to >>>transport it over fiber, and SFP is the easy way to do that. But SFP
    is intended for telecom, ac coupled, intolerant of dc imbalance. Most >>>SFPs won't pass anything below about 1 MHz. But they are crazy fast
    and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to
    do that. 10M would be plenty.


    What is being digitized? Voice? Data of some kind?

    Some customer's analog voltage. Might be a strain gage load cell, for >example. We'd have some input ranges.

    All very low bandwidth stuff. Is it required to transmit absolute
    values, or is just the "AC" part enough?

    Sounds like for instance actual strain values are desired.



    Is there a maximum latency and latency jitter requirement?

    Neither, actually. I just want to transport the ADC output correctly.

    OK.



    One-bit delta samples are usually signed, so the minimum is two
    symbols. If the voltage being sent is zero, then we'll get a steady >>+,-,+,-,+, stream, which will have very strong RF spurs and thus >>emissions, so need to break this up.

    The ADC has a one-bit output over +-320 mV input, and averages 50%
    duty cycle at 0 volts in. I just want to transport that bit over a
    fiber link.

    So the ADC output is a signed bit per sample.



    A zero symbol makes it three, and an idle symbol, makes it four
    symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>>patterns for every possible symbol to be sent, and they track current >>>>DC balance, and choose which pattern to use that will reduce the >>>>running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work.

    SFPs usually tolerate a little DC imbalance. You can send PWM at, say, >>>35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >>enough.

    I don't want an FPGA or a uP in this box. All my coder-people are too
    busy on other projects now. So, a few gates and flipflops.

    OK. This too can be done, given a large ratio between optical bit
    rate and ADC bitrate.

    The AGC in the SFP is pretty fast, but the optical bitrate must be
    much faster, or the AGC will flatten the desired signal. The SFP
    datasheet should define the AGC response speed.

    So, pick a convenient optical signaling (flash) rate well above the
    AGC reaction speed, so you will be able to recover the sent pattern at
    the SFP output.

    Here is one possible design:

    Choose a ADC sample rate a fraction of the optical rate. The fraction
    is determined by choosing orthogonal codes to represent +1, zero, or
    -1 ADC outputs to be sent. Also need a frame-start symbol.

    The orthogonal codes are chosen from the standard Gold Codes:

    .<https://en.wikipedia.org/wiki/Gold_code>

    The codes have odd length, and are fairly close to balanced, so one
    ought to be able to find some truncated Gold codes of even length
    (drop last bit) that are exactly balanced. We need only four such
    symbol codes, and a 16-bit code would allow the optical rate to be 16
    times the code (ADC output) rate.

    There must be a steady stream of ADC symbols, even if ADC output is
    zero, to keep the SFP AGC stable.

    Generation. Drive a 16-line demux with the optical clock. Make or
    don't make connections from the demux to an adder, as dictated by the
    symbol to be sent. The adder output is used to drive the SFP TX
    input.

    Reception. Lock a phase-lock loop to the optical flash rate, to
    recover the optical clock.

    Have one correlator per symbol type, all running in parallel. Given
    the near-perfect correlation behavior of Gold codes, the correlator
    output will be roughly one unit amplitude except at the pattern
    center, where the peak will be about 16 units, so a threshold set at 8
    units should enable perfect recovery.

    The frame sync symbol is used if we are switching between a reference
    voltage and the strain-gage output voltage, to mark where reference
    starts. May need an ref-end symbol.

    If no correlator peaks for more than a few symbol periods, complain.
    The SFP will also tell you if any optical power is being received, if
    I recall.

    Design the receiver first, as it's usually the harder of the two, then
    design the transmitter to make the receiver happy.


    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Clifford Heath@21:1/5 to John May on Fri Aug 5 09:24:28 2022
    On 4/8/22 20:26, John May wrote:
    I was quite attracted to Knuth's literate programming ideas for a while, but in multi programmer projects the approach was allways rejected.

    The difficulty with literate programming is that you need to find
    literate programmers.

    Modern programming languages tend to assist the programmer to reveal
    their intentions to a much greater degree that was e.g. the FORTRAN in
    which Knuth wrote TeX.

    But programmers still have to have a sense of which things might or
    might not be already known or become apparent to another human - meaning
    they need to see outside their own heads. That's not very common, and
    even less so in more productive programmers.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John S@21:1/5 to John Larkin on Thu Aug 4 19:52:47 2022
    On 8/3/2022 4:29 PM, John Larkin wrote:
    On Wed, 3 Aug 2022 14:28:30 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    jlarkin@highlandsniptechnology.com wrote:
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
    <martin_riddle@verison.net> wrote:

    jlarkin@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I want to send data over an SFP optical link, in 6-bit things. 0 1 1 0 d \d repeated, roughly 100 Mbits/secis DC balanced, which SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers

    Maybe "frame" sounds better than "clump."



    Or 'clod'. Alternatives abound. ;)

    I'd go with sextet (or sestet, if you're feeling poetic).

    Cheers

    Phil Hobbs

    Now one of my guys claims that all we need is

    1 0 d1 \d1 1 0 d2 \d2 .... etc

    four bits per chunk to recover data d. Which is a nibble. I can still
    call each 4 bits a frame.


    4 bit is a nybble. Or a dollar.


    I hate it when people are smarter than I am.


    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Thu Aug 4 16:40:43 2022
    On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin ><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin >>><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com >>>>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in >>>>>bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in >>>>>size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so >>>>>ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use >>>>>only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and
    receive. I'm thinking about a spare-time thing that I could design >>>>without an FPGA or uP, all hardware. My digital people are swamped
    with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you >>>>>need, double it (for growth), and figure out long a word is needed. >>>>>Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to >>>>transport it over fiber, and SFP is the easy way to do that. But SFP
    is intended for telecom, ac coupled, intolerant of dc imbalance. Most >>>>SFPs won't pass anything below about 1 MHz. But they are crazy fast
    and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to
    do that. 10M would be plenty.


    What is being digitized? Voice? Data of some kind?

    Some customer's analog voltage. Might be a strain gage load cell, for >>example. We'd have some input ranges.

    All very low bandwidth stuff. Is it required to transmit absolute
    values, or is just the "AC" part enough?

    Sounds like for instance actual strain values are desired.



    Is there a maximum latency and latency jitter requirement?

    Neither, actually. I just want to transport the ADC output correctly.

    OK.



    One-bit delta samples are usually signed, so the minimum is two
    symbols. If the voltage being sent is zero, then we'll get a steady >>>+,-,+,-,+, stream, which will have very strong RF spurs and thus >>>emissions, so need to break this up.

    The ADC has a one-bit output over +-320 mV input, and averages 50%
    duty cycle at 0 volts in. I just want to transport that bit over a
    fiber link.

    So the ADC output is a signed bit per sample.

    It's an ADUM7703 delta-sigma a/d converter; it doesn't actually sample
    but runs its stuff continuously. It has a clock input and a single bit
    logic output. The duty cycle of the output reports the analog input:
    0% duty cycle is -320 mV and 100% is +320 mV. It's fully isolated and
    crazy precise. Once we convey that logic level to a destination, we
    "decimate" it into a 16 or 18 or 20 bit value that reflects the input
    voltage. The decimation is typically digital, a sinc3 filter, but I
    might do it all analog in this case. Decimation becomes a lowpass
    filter.






    A zero symbol makes it three, and an idle symbol, makes it four
    symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>>>patterns for every possible symbol to be sent, and they track current >>>>>DC balance, and choose which pattern to use that will reduce the >>>>>running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work.

    SFPs usually tolerate a little DC imbalance. You can send PWM at, say, >>>>35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >>>enough.

    I don't want an FPGA or a uP in this box. All my coder-people are too
    busy on other projects now. So, a few gates and flipflops.

    OK. This too can be done, given a large ratio between optical bit
    rate and ADC bitrate.

    The AGC in the SFP is pretty fast, but the optical bitrate must be
    much faster, or the AGC will flatten the desired signal. The SFP
    datasheet should define the AGC response speed.

    The combination of AGC and AC coupling makes SFPs not work well at
    data rates below about 1 MHz. That varies a lot with specific parts.


    So, pick a convenient optical signaling (flash) rate well above the
    AGC reaction speed, so you will be able to recover the sent pattern at
    the SFP output.

    Here is one possible design:

    Choose a ADC sample rate a fraction of the optical rate. The fraction
    is determined by choosing orthogonal codes to represent +1, zero, or
    -1 ADC outputs to be sent. Also need a frame-start symbol.

    The orthogonal codes are chosen from the standard Gold Codes:

    .<https://en.wikipedia.org/wiki/Gold_code>

    The codes have odd length, and are fairly close to balanced, so one
    ought to be able to find some truncated Gold codes of even length
    (drop last bit) that are exactly balanced. We need only four such
    symbol codes, and a 16-bit code would allow the optical rate to be 16
    times the code (ADC output) rate.

    There must be a steady stream of ADC symbols, even if ADC output is
    zero, to keep the SFP AGC stable.

    Generation. Drive a 16-line demux with the optical clock. Make or
    don't make connections from the demux to an adder, as dictated by the
    symbol to be sent. The adder output is used to drive the SFP TX
    input.

    Reception. Lock a phase-lock loop to the optical flash rate, to
    recover the optical clock.

    Have one correlator per symbol type, all running in parallel. Given
    the near-perfect correlation behavior of Gold codes, the correlator
    output will be roughly one unit amplitude except at the pattern
    center, where the peak will be about 16 units, so a threshold set at 8
    units should enable perfect recovery.

    The frame sync symbol is used if we are switching between a reference
    voltage and the strain-gage output voltage, to mark where reference
    starts. May need an ref-end symbol.

    If no correlator peaks for more than a few symbol periods, complain.
    The SFP will also tell you if any optical power is being received, if
    I recall.

    Design the receiver first, as it's usually the harder of the two, then
    design the transmitter to make the receiver happy.

    It's really simple; just move the 1-bit logic level output of the ADC
    to the destination and recover a clock to know where the bits are.
    We'd clock the ADC at 20 or maybe 10 MHz.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to John S on Thu Aug 4 22:20:18 2022
    John S wrote:
    On 8/3/2022 4:29 PM, John Larkin wrote:
    On Wed, 3 Aug 2022 14:28:30 -0400, Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    jlarkin@highlandsniptechnology.com wrote:
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
    <martin_riddle@verison.net> wrote:

    jlarkin@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I
    want to send data over an SFP optical link, in 6-bit things.   0 1 >>>>>> 1 0 d \d   repeated, roughly 100 Mbits/secis DC balanced, which
    SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers

    Maybe "frame" sounds better than "clump."



    Or 'clod'.   Alternatives abound. ;)

    I'd go with sextet (or sestet, if you're feeling poetic).

    Cheers

    Phil Hobbs

    Now one of my guys claims that all we need is

    1 0 d1 \d1 1 0 d2 \d2 .... etc

    four bits per chunk to recover data d. Which is a nibble. I can still
    call each 4 bits a frame.


    4 bit is a nybble. Or a dollar.

    Nah, two bits is a quarter, so 8 bits is a dollar.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jlarkin@highland_atwork_technology. on Fri Aug 5 11:29:50 2022
    On Thu, 04 Aug 2022 16:40:43 -0700, John Larkin <jlarkin@highland_atwork_technology.com> wrote:

    On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin >><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joegwinn@comcast.net> >>>wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin >>>><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com >>>>>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>>>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in >>>>>>bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in >>>>>>size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so >>>>>>ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use >>>>>>only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and >>>>>receive. I'm thinking about a spare-time thing that I could design >>>>>without an FPGA or uP, all hardware. My digital people are swamped >>>>>with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you >>>>>>need, double it (for growth), and figure out long a word is needed. >>>>>>Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to >>>>>transport it over fiber, and SFP is the easy way to do that. But SFP >>>>>is intended for telecom, ac coupled, intolerant of dc imbalance. Most >>>>>SFPs won't pass anything below about 1 MHz. But they are crazy fast >>>>>and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to
    do that. 10M would be plenty.


    What is being digitized? Voice? Data of some kind?

    Some customer's analog voltage. Might be a strain gage load cell, for >>>example. We'd have some input ranges.

    All very low bandwidth stuff. Is it required to transmit absolute
    values, or is just the "AC" part enough?

    Sounds like for instance actual strain values are desired.



    Is there a maximum latency and latency jitter requirement?

    Neither, actually. I just want to transport the ADC output correctly.

    OK.



    One-bit delta samples are usually signed, so the minimum is two >>>>symbols. If the voltage being sent is zero, then we'll get a steady >>>>+,-,+,-,+, stream, which will have very strong RF spurs and thus >>>>emissions, so need to break this up.

    The ADC has a one-bit output over +-320 mV input, and averages 50%
    duty cycle at 0 volts in. I just want to transport that bit over a
    fiber link.

    So the ADC output is a signed bit per sample.

    It's an ADUM7703 delta-sigma a/d converter; it doesn't actually sample
    but runs its stuff continuously. It has a clock input and a single bit
    logic output. The duty cycle of the output reports the analog input:
    0% duty cycle is -320 mV and 100% is +320 mV. It's fully isolated and
    crazy precise. Once we convey that logic level to a destination, we >"decimate" it into a 16 or 18 or 20 bit value that reflects the input >voltage. The decimation is typically digital, a sinc3 filter, but I
    might do it all analog in this case. Decimation becomes a lowpass
    filter.

    The fact that the ADUM7703 is clocked implies that is samples on the
    clock. Otherwise, why require a clock input? Datasheet page 4 shows
    the relationship.

    More at end.



    A zero symbol makes it three, and an idle symbol, makes it four >>>>symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>>>>patterns for every possible symbol to be sent, and they track current >>>>>>DC balance, and choose which pattern to use that will reduce the >>>>>>running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work. >>>>>
    SFPs usually tolerate a little DC imbalance. You can send PWM at, say, >>>>>35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >>>>enough.

    I don't want an FPGA or a uP in this box. All my coder-people are too >>>busy on other projects now. So, a few gates and flipflops.

    OK. This too can be done, given a large ratio between optical bit
    rate and ADC bitrate.

    The AGC in the SFP is pretty fast, but the optical bitrate must be
    much faster, or the AGC will flatten the desired signal. The SFP
    datasheet should define the AGC response speed.

    The combination of AGC and AC coupling makes SFPs not work well at
    data rates below about 1 MHz. That varies a lot with specific parts.


    So, pick a convenient optical signaling (flash) rate well above the
    AGC reaction speed, so you will be able to recover the sent pattern at
    the SFP output.

    Here is one possible design:

    Choose a ADC sample rate a fraction of the optical rate. The fraction
    is determined by choosing orthogonal codes to represent +1, zero, or
    -1 ADC outputs to be sent. Also need a frame-start symbol.

    The orthogonal codes are chosen from the standard Gold Codes:

    .<https://en.wikipedia.org/wiki/Gold_code>

    The codes have odd length, and are fairly close to balanced, so one
    ought to be able to find some truncated Gold codes of even length
    (drop last bit) that are exactly balanced. We need only four such
    symbol codes, and a 16-bit code would allow the optical rate to be 16
    times the code (ADC output) rate.

    There must be a steady stream of ADC symbols, even if ADC output is
    zero, to keep the SFP AGC stable.

    Generation. Drive a 16-line demux with the optical clock. Make or
    don't make connections from the demux to an adder, as dictated by the >>symbol to be sent. The adder output is used to drive the SFP TX
    input.

    Reception. Lock a phase-lock loop to the optical flash rate, to
    recover the optical clock.

    Have one correlator per symbol type, all running in parallel. Given
    the near-perfect correlation behavior of Gold codes, the correlator
    output will be roughly one unit amplitude except at the pattern
    center, where the peak will be about 16 units, so a threshold set at 8 >>units should enable perfect recovery.

    The frame sync symbol is used if we are switching between a reference >>voltage and the strain-gage output voltage, to mark where reference
    starts. May need an ref-end symbol.

    If no correlator peaks for more than a few symbol periods, complain.
    The SFP will also tell you if any optical power is being received, if
    I recall.

    Design the receiver first, as it's usually the harder of the two, then >>design the transmitter to make the receiver happy.

    It's really simple; just move the 1-bit logic level output of the ADC
    to the destination and recover a clock to know where the bits are.
    We'd clock the ADC at 20 or maybe 10 MHz.

    If I'm understanding the timing diagram on datasheet page 4, one can
    have a long string of ones, or of zeros, depending on the input analog
    voltage, which has fairly low bandwidth and so can linger at a voltage
    for very long durations.

    It's these long rafts of ones or zeros that I worry will baffle the
    SFP's AGC function, causing data-dependent link failures.

    What make and model of SFP are you looking at?


    But one could use two Gold-code symbols, encoding MDATA one and MDATA
    zero, and a pair of correlators at the other end of the fiber-optic
    link to recover the original MDATA stream.

    And, optical SNR matters. If the minimum SNR is high, the tolerance
    for non-zero DC balance, is increased. What is the maximum optical
    cable length contemplated?


    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From upsidedown@downunder.com@21:1/5 to All on Fri Aug 5 19:18:19 2022
    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com
    wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    Since you are transferring only a single (net) bit, why are you
    worrying about the names of the actual frame bits ?

    Compare to the situation with asynchronous serial communication. A
    UART can usually transfer 5-8 (some up to 14) net data bits, but in
    addition to this, the start bit is added, an optional parity bit and
    0, 1, 1.5 or 2 stop bits are added, producing a 75 to 16 bit
    transmitted frame. You really rarely have to worry about the total
    frame size (except for some RS-485 converters).

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Walliker@21:1/5 to Joe Gwinn on Fri Aug 5 09:22:21 2022
    On Friday, 5 August 2022 at 16:30:03 UTC+1, Joe Gwinn wrote:
    On Thu, 04 Aug 2022 16:40:43 -0700, John Larkin <jlarkin@highland_atwork_technology.com> wrote:

    On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin >><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joeg...@comcast.net> >>>wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin >>>><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joeg...@comcast.net> >>>>>wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com >>>>>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>>>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in >>>>>>bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in >>>>>>size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so >>>>>>ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use >>>>>>only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and >>>>>receive. I'm thinking about a spare-time thing that I could design >>>>>without an FPGA or uP, all hardware. My digital people are swamped >>>>>with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you >>>>>>need, double it (for growth), and figure out long a word is needed. >>>>>>Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to >>>>>transport it over fiber, and SFP is the easy way to do that. But SFP >>>>>is intended for telecom, ac coupled, intolerant of dc imbalance. Most >>>>>SFPs won't pass anything below about 1 MHz. But they are crazy fast >>>>>and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to >>>do that. 10M would be plenty.


    What is being digitized? Voice? Data of some kind?

    Some customer's analog voltage. Might be a strain gage load cell, for >>>example. We'd have some input ranges.

    All very low bandwidth stuff. Is it required to transmit absolute
    values, or is just the "AC" part enough?

    Sounds like for instance actual strain values are desired.



    Is there a maximum latency and latency jitter requirement?

    Neither, actually. I just want to transport the ADC output correctly.

    OK.



    One-bit delta samples are usually signed, so the minimum is two >>>>symbols. If the voltage being sent is zero, then we'll get a steady >>>>+,-,+,-,+, stream, which will have very strong RF spurs and thus >>>>emissions, so need to break this up.

    The ADC has a one-bit output over +-320 mV input, and averages 50%
    duty cycle at 0 volts in. I just want to transport that bit over a >>>fiber link.

    So the ADC output is a signed bit per sample.

    It's an ADUM7703 delta-sigma a/d converter; it doesn't actually sample
    but runs its stuff continuously. It has a clock input and a single bit >logic output. The duty cycle of the output reports the analog input:
    0% duty cycle is -320 mV and 100% is +320 mV. It's fully isolated and
    crazy precise. Once we convey that logic level to a destination, we >"decimate" it into a 16 or 18 or 20 bit value that reflects the input >voltage. The decimation is typically digital, a sinc3 filter, but I
    might do it all analog in this case. Decimation becomes a lowpass
    filter.
    The fact that the ADUM7703 is clocked implies that is samples on the
    clock. Otherwise, why require a clock input? Datasheet page 4 shows
    the relationship.

    More at end.

    A zero symbol makes it three, and an idle symbol, makes it four >>>>symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>>>>patterns for every possible symbol to be sent, and they track current >>>>>>DC balance, and choose which pattern to use that will reduce the >>>>>>running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work. >>>>>
    SFPs usually tolerate a little DC imbalance. You can send PWM at, say, >>>>>35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >>>>enough.

    I don't want an FPGA or a uP in this box. All my coder-people are too >>>busy on other projects now. So, a few gates and flipflops.

    OK. This too can be done, given a large ratio between optical bit
    rate and ADC bitrate.

    The AGC in the SFP is pretty fast, but the optical bitrate must be
    much faster, or the AGC will flatten the desired signal. The SFP >>datasheet should define the AGC response speed.

    The combination of AGC and AC coupling makes SFPs not work well at
    data rates below about 1 MHz. That varies a lot with specific parts.


    So, pick a convenient optical signaling (flash) rate well above the
    AGC reaction speed, so you will be able to recover the sent pattern at >>the SFP output.

    Here is one possible design:

    Choose a ADC sample rate a fraction of the optical rate. The fraction
    is determined by choosing orthogonal codes to represent +1, zero, or
    -1 ADC outputs to be sent. Also need a frame-start symbol.

    The orthogonal codes are chosen from the standard Gold Codes:

    .<https://en.wikipedia.org/wiki/Gold_code>

    The codes have odd length, and are fairly close to balanced, so one
    ought to be able to find some truncated Gold codes of even length
    (drop last bit) that are exactly balanced. We need only four such
    symbol codes, and a 16-bit code would allow the optical rate to be 16 >>times the code (ADC output) rate.

    There must be a steady stream of ADC symbols, even if ADC output is
    zero, to keep the SFP AGC stable.

    Generation. Drive a 16-line demux with the optical clock. Make or
    don't make connections from the demux to an adder, as dictated by the >>symbol to be sent. The adder output is used to drive the SFP TX
    input.

    Reception. Lock a phase-lock loop to the optical flash rate, to
    recover the optical clock.

    Have one correlator per symbol type, all running in parallel. Given
    the near-perfect correlation behavior of Gold codes, the correlator >>output will be roughly one unit amplitude except at the pattern
    center, where the peak will be about 16 units, so a threshold set at 8 >>units should enable perfect recovery.

    The frame sync symbol is used if we are switching between a reference >>voltage and the strain-gage output voltage, to mark where reference >>starts. May need an ref-end symbol.

    If no correlator peaks for more than a few symbol periods, complain.
    The SFP will also tell you if any optical power is being received, if
    I recall.

    Design the receiver first, as it's usually the harder of the two, then >>design the transmitter to make the receiver happy.

    It's really simple; just move the 1-bit logic level output of the ADC
    to the destination and recover a clock to know where the bits are.
    We'd clock the ADC at 20 or maybe 10 MHz.
    If I'm understanding the timing diagram on datasheet page 4, one can
    have a long string of ones, or of zeros, depending on the input analog voltage, which has fairly low bandwidth and so can linger at a voltage
    for very long durations.

    It's these long rafts of ones or zeros that I worry will baffle the
    SFP's AGC function, causing data-dependent link failures.

    What make and model of SFP are you looking at?


    But one could use two Gold-code symbols, encoding MDATA one and MDATA
    zero, and a pair of correlators at the other end of the fiber-optic
    link to recover the original MDATA stream.

    And, optical SNR matters. If the minimum SNR is high, the tolerance
    for non-zero DC balance, is increased. What is the maximum optical
    cable length contemplated?

    With optical fibre losses of a few tenths of a dB/km and a likely link
    margin of well over 10dB I don't think optical cable length will be an
    issue here.
    The originally proposed 6-bit encoding scheme included the data bit
    followed by its complement, so that will have removed any dc baseline fluctuation issues.
    SFPs are remarkable tolerant of optical abuse. I have tried using
    multimode fibre with single mode SFPs and single mode SFPs with
    multimode fibre over lengths of around 50m at 1 and 10Gbit/s. Every combination works fine despite the optical losses in some of those configurations.

    John

    --- SoupGate-Win32 v1.05
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  • From John Larkin@21:1/5 to All on Fri Aug 5 10:15:20 2022
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Thu, 04 Aug 2022 16:40:43 -0700, John Larkin ><jlarkin@highland_atwork_technology.com> wrote:

    On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin >>><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin >>>>><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>>wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com >>>>>>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>>>>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in >>>>>>>bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in >>>>>>>size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so >>>>>>>ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use >>>>>>>only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and >>>>>>receive. I'm thinking about a spare-time thing that I could design >>>>>>without an FPGA or uP, all hardware. My digital people are swamped >>>>>>with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you >>>>>>>need, double it (for growth), and figure out long a word is needed. >>>>>>>Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to >>>>>>transport it over fiber, and SFP is the easy way to do that. But SFP >>>>>>is intended for telecom, ac coupled, intolerant of dc imbalance. Most >>>>>>SFPs won't pass anything below about 1 MHz. But they are crazy fast >>>>>>and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to >>>>do that. 10M would be plenty.


    What is being digitized? Voice? Data of some kind?

    Some customer's analog voltage. Might be a strain gage load cell, for >>>>example. We'd have some input ranges.

    All very low bandwidth stuff. Is it required to transmit absolute >>>values, or is just the "AC" part enough?

    Sounds like for instance actual strain values are desired.



    Is there a maximum latency and latency jitter requirement?

    Neither, actually. I just want to transport the ADC output correctly.

    OK.



    One-bit delta samples are usually signed, so the minimum is two >>>>>symbols. If the voltage being sent is zero, then we'll get a steady >>>>>+,-,+,-,+, stream, which will have very strong RF spurs and thus >>>>>emissions, so need to break this up.

    The ADC has a one-bit output over +-320 mV input, and averages 50%
    duty cycle at 0 volts in. I just want to transport that bit over a >>>>fiber link.

    So the ADC output is a signed bit per sample.

    It's an ADUM7703 delta-sigma a/d converter; it doesn't actually sample
    but runs its stuff continuously. It has a clock input and a single bit >>logic output. The duty cycle of the output reports the analog input:
    0% duty cycle is -320 mV and 100% is +320 mV. It's fully isolated and
    crazy precise. Once we convey that logic level to a destination, we >>"decimate" it into a 16 or 18 or 20 bit value that reflects the input >>voltage. The decimation is typically digital, a sinc3 filter, but I
    might do it all analog in this case. Decimation becomes a lowpass
    filter.

    The fact that the ADUM7703 is clocked implies that is samples on the
    clock. Otherwise, why require a clock input? Datasheet page 4 shows
    the relationship.

    More at end.



    A zero symbol makes it three, and an idle symbol, makes it four >>>>>symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>>>>>patterns for every possible symbol to be sent, and they track current >>>>>>>DC balance, and choose which pattern to use that will reduce the >>>>>>>running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work. >>>>>>
    SFPs usually tolerate a little DC imbalance. You can send PWM at, say, >>>>>>35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >>>>>enough.

    I don't want an FPGA or a uP in this box. All my coder-people are too >>>>busy on other projects now. So, a few gates and flipflops.

    OK. This too can be done, given a large ratio between optical bit
    rate and ADC bitrate.

    The AGC in the SFP is pretty fast, but the optical bitrate must be
    much faster, or the AGC will flatten the desired signal. The SFP >>>datasheet should define the AGC response speed.

    The combination of AGC and AC coupling makes SFPs not work well at
    data rates below about 1 MHz. That varies a lot with specific parts.


    So, pick a convenient optical signaling (flash) rate well above the
    AGC reaction speed, so you will be able to recover the sent pattern at >>>the SFP output.

    Here is one possible design:

    Choose a ADC sample rate a fraction of the optical rate. The fraction
    is determined by choosing orthogonal codes to represent +1, zero, or
    -1 ADC outputs to be sent. Also need a frame-start symbol.

    The orthogonal codes are chosen from the standard Gold Codes:

    .<https://en.wikipedia.org/wiki/Gold_code>

    The codes have odd length, and are fairly close to balanced, so one
    ought to be able to find some truncated Gold codes of even length
    (drop last bit) that are exactly balanced. We need only four such
    symbol codes, and a 16-bit code would allow the optical rate to be 16 >>>times the code (ADC output) rate.

    There must be a steady stream of ADC symbols, even if ADC output is
    zero, to keep the SFP AGC stable.

    Generation. Drive a 16-line demux with the optical clock. Make or
    don't make connections from the demux to an adder, as dictated by the >>>symbol to be sent. The adder output is used to drive the SFP TX
    input.

    Reception. Lock a phase-lock loop to the optical flash rate, to
    recover the optical clock.

    Have one correlator per symbol type, all running in parallel. Given
    the near-perfect correlation behavior of Gold codes, the correlator >>>output will be roughly one unit amplitude except at the pattern
    center, where the peak will be about 16 units, so a threshold set at 8 >>>units should enable perfect recovery.

    The frame sync symbol is used if we are switching between a reference >>>voltage and the strain-gage output voltage, to mark where reference >>>starts. May need an ref-end symbol.

    If no correlator peaks for more than a few symbol periods, complain.
    The SFP will also tell you if any optical power is being received, if
    I recall.

    Design the receiver first, as it's usually the harder of the two, then >>>design the transmitter to make the receiver happy.

    It's really simple; just move the 1-bit logic level output of the ADC
    to the destination and recover a clock to know where the bits are.
    We'd clock the ADC at 20 or maybe 10 MHz.

    If I'm understanding the timing diagram on datasheet page 4, one can
    have a long string of ones, or of zeros, depending on the input analog >voltage, which has fairly low bandwidth and so can linger at a voltage
    for very long durations.

    Of course voltages near the negative rail have to get close to 0% duty
    cycle, low bit density. I can avoid that by not allowing more than,
    say, +-250 mV.

    Delta-sigma "noise shapes" to push the data spectrum up, namely avoid
    low frequency components in the duty cycle.


    It's these long rafts of ones or zeros that I worry will baffle the
    SFP's AGC function, causing data-dependent link failures.

    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    What make and model of SFP are you looking at?

    I've evaluated a bunch of them. I'll have to look that up.



    But one could use two Gold-code symbols, encoding MDATA one and MDATA
    zero, and a pair of correlators at the other end of the fiber-optic
    link to recover the original MDATA stream.

    And, optical SNR matters. If the minimum SNR is high, the tolerance
    for non-zero DC balance, is increased. What is the maximum optical
    cable length contemplated?

    A couple of km, maybe. Singlemode can go 10s of km.




    Joe Gwinn

    --- SoupGate-Win32 v1.05
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  • From Gerhard Hoffmann@21:1/5 to All on Fri Aug 5 19:20:08 2022
    Am 05.08.22 um 19:15 schrieb John Larkin:

    And, optical SNR matters. If the minimum SNR is high, the tolerance
    for non-zero DC balance, is increased. What is the maximum optical
    cable length contemplated?

    A couple of km, maybe. Singlemode can go 10s of km.

    I think the limit is dispersion, not attenuation.

    Chees, Gerhard

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to upsidedown@downunder.com on Fri Aug 5 10:20:33 2022
    On Fri, 05 Aug 2022 19:18:19 +0300, upsidedown@downunder.com wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com
    wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    Since you are transferring only a single (net) bit, why are you
    worrying about the names of the actual frame bits ?

    Names?


    Compare to the situation with asynchronous serial communication. A
    UART can usually transfer 5-8 (some up to 14) net data bits, but in
    addition to this, the start bit is added, an optional parity bit and
    0, 1, 1.5 or 2 stop bits are added, producing a 75 to 16 bit
    transmitted frame. You really rarely have to worry about the total
    frame size (except for some RS-485 converters).

    I can get 10 Gbit SFPs cheap, so channel rate isn't an issue. But we
    need DC balance and circuit simplicity. The new 4-bit thing looks
    good, 1 0 d \d per frame.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Fri Aug 5 10:53:34 2022
    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to Gerhard Hoffmann on Fri Aug 5 14:21:14 2022
    Gerhard Hoffmann wrote:
    Am 05.08.22 um 19:15 schrieb John Larkin:

    And, optical SNR matters.  If the minimum SNR is high, the tolerance
    for non-zero DC balance, is increased.  What is the maximum optical
    cable length contemplated?

    A couple of km, maybe. Singlemode can go 10s of km.

    I think the limit is dispersion, not attenuation.

    Chees, Gerhard



    Step-index multimode can be as bad as 20 ns/km iirc. Good graded-index
    fibre is more than a factor of 10 better (400 MHz * km is a number I've
    seen).

    Single-mode fibre is good for a really long distance--it's just the
    optical bandwidth that sets the dispersion.

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

    --- SoupGate-Win32 v1.05
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  • From John Larkin@21:1/5 to langwadt@fonz.dk on Fri Aug 5 13:20:46 2022
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010



    Cute. But pattern 1010 1010

    has an embedded 1010

    which means that a simple running decoder can mis-frame
    the clumps.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Fri Aug 5 13:27:10 2022
    On Fri, 5 Aug 2022 19:20:08 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
    wrote:

    Am 05.08.22 um 19:15 schrieb John Larkin:

    And, optical SNR matters. If the minimum SNR is high, the tolerance
    for non-zero DC balance, is increased. What is the maximum optical
    cable length contemplated?

    A couple of km, maybe. Singlemode can go 10s of km.

    I think the limit is dispersion, not attenuation.

    Chees, Gerhard


    Right. Multimode has bad time dispersion.

    The Guinness record for an un-repeatered fiber link is 10,358.16 km.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Mike Monett@21:1/5 to Lasse Langwadt Christensen on Fri Aug 5 21:02:06 2022
    Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero deadband
    PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234
    patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102 34.pdf





    --
    MRM

    --- SoupGate-Win32 v1.05
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  • From Lasse Langwadt Christensen@21:1/5 to All on Fri Aug 5 13:41:31 2022
    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame
    the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From a a@21:1/5 to Mike Monett on Fri Aug 5 14:55:25 2022
    On Friday, 5 August 2022 at 23:02:14 UTC+2, Mike Monett wrote:
    Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?
    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero deadband
    PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234 patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102 34.pdf





    --
    MRM
    <Error>
    <Code>AccessDenied</Code>
    <Message>Access denied.</Message>
    <Details>
    Anonymous caller does not have storage.objects.get access to the Google Cloud Storage object.
    </Details>
    </Error>

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jrwalliker@gmail.com on Fri Aug 5 18:12:29 2022
    On Fri, 5 Aug 2022 09:22:21 -0700 (PDT), John Walliker
    <jrwalliker@gmail.com> wrote:

    On Friday, 5 August 2022 at 16:30:03 UTC+1, Joe Gwinn wrote:
    [snip]

    And, optical SNR matters. If the minimum SNR is high, the tolerance
    for non-zero DC balance, is increased. What is the maximum optical
    cable length contemplated?

    With optical fibre losses of a few tenths of a dB/km and a likely link
    margin of well over 10dB I don't think optical cable length will be an
    issue here.

    Yes. It turns out that the max reach is one km, and singlemode will
    go five km.


    The originally proposed 6-bit encoding scheme included the data bit
    followed by its complement, so that will have removed any dc baseline >fluctuation issues.

    It should, but the two-bit and four-bit schemes may be challenged. And
    also suffer from framing errors.


    SFPs are remarkable tolerant of optical abuse. I have tried using
    multimode fibre with single mode SFPs and single mode SFPs with
    multimode fibre over lengths of around 50m at 1 and 10Gbit/s. Every >combination works fine despite the optical losses in some of those >configurations.

    At 50 meters, basically anything will work.

    With signals sent by RS422 over wire, the standard observation/joke
    was that one could sent this signal on a two-strand barbed wire fence
    -- so long as the cows didn't use the fence as a back scratchier.

    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jlarkin@highland_atwork_technology. on Fri Aug 5 18:05:27 2022
    On Fri, 05 Aug 2022 10:15:20 -0700, John Larkin <jlarkin@highland_atwork_technology.com> wrote:

    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Thu, 04 Aug 2022 16:40:43 -0700, John Larkin >><jlarkin@highland_atwork_technology.com> wrote:

    On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joegwinn@comcast.net> >>>wrote:

    On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin >>>><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin >>>>>><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>>>wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jlarkin@highlandsniptechnology.com >>>>>>>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump? >>>>>>>>
    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>>>>>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in >>>>>>>>bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in >>>>>>>>size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so >>>>>>>>ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things. >>>>>>>>>
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use >>>>>>>>only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and >>>>>>>receive. I'm thinking about a spare-time thing that I could design >>>>>>>without an FPGA or uP, all hardware. My digital people are swamped >>>>>>>with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you >>>>>>>>need, double it (for growth), and figure out long a word is needed. >>>>>>>>Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to >>>>>>>transport it over fiber, and SFP is the easy way to do that. But SFP >>>>>>>is intended for telecom, ac coupled, intolerant of dc imbalance. Most >>>>>>>SFPs won't pass anything below about 1 MHz. But they are crazy fast >>>>>>>and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to >>>>>do that. 10M would be plenty.


    What is being digitized? Voice? Data of some kind?

    Some customer's analog voltage. Might be a strain gage load cell, for >>>>>example. We'd have some input ranges.

    All very low bandwidth stuff. Is it required to transmit absolute >>>>values, or is just the "AC" part enough?

    Sounds like for instance actual strain values are desired.



    Is there a maximum latency and latency jitter requirement?

    Neither, actually. I just want to transport the ADC output correctly.

    OK.



    One-bit delta samples are usually signed, so the minimum is two >>>>>>symbols. If the voltage being sent is zero, then we'll get a steady >>>>>>+,-,+,-,+, stream, which will have very strong RF spurs and thus >>>>>>emissions, so need to break this up.

    The ADC has a one-bit output over +-320 mV input, and averages 50% >>>>>duty cycle at 0 volts in. I just want to transport that bit over a >>>>>fiber link.

    So the ADC output is a signed bit per sample.

    It's an ADUM7703 delta-sigma a/d converter; it doesn't actually sample >>>but runs its stuff continuously. It has a clock input and a single bit >>>logic output. The duty cycle of the output reports the analog input:
    0% duty cycle is -320 mV and 100% is +320 mV. It's fully isolated and >>>crazy precise. Once we convey that logic level to a destination, we >>>"decimate" it into a 16 or 18 or 20 bit value that reflects the input >>>voltage. The decimation is typically digital, a sinc3 filter, but I
    might do it all analog in this case. Decimation becomes a lowpass
    filter.

    The fact that the ADUM7703 is clocked implies that is samples on the
    clock. Otherwise, why require a clock input? Datasheet page 4 shows
    the relationship.

    More at end.



    A zero symbol makes it three, and an idle symbol, makes it four >>>>>>symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>>>>>>patterns for every possible symbol to be sent, and they track current >>>>>>>>DC balance, and choose which pattern to use that will reduce the >>>>>>>>running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work. >>>>>>>
    SFPs usually tolerate a little DC imbalance. You can send PWM at, say, >>>>>>>35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >>>>>>enough.

    I don't want an FPGA or a uP in this box. All my coder-people are too >>>>>busy on other projects now. So, a few gates and flipflops.

    OK. This too can be done, given a large ratio between optical bit
    rate and ADC bitrate.

    The AGC in the SFP is pretty fast, but the optical bitrate must be
    much faster, or the AGC will flatten the desired signal. The SFP >>>>datasheet should define the AGC response speed.

    The combination of AGC and AC coupling makes SFPs not work well at
    data rates below about 1 MHz. That varies a lot with specific parts.


    So, pick a convenient optical signaling (flash) rate well above the
    AGC reaction speed, so you will be able to recover the sent pattern at >>>>the SFP output.

    Here is one possible design:

    Choose a ADC sample rate a fraction of the optical rate. The fraction >>>>is determined by choosing orthogonal codes to represent +1, zero, or
    -1 ADC outputs to be sent. Also need a frame-start symbol.

    The orthogonal codes are chosen from the standard Gold Codes:

    .<https://en.wikipedia.org/wiki/Gold_code>

    The codes have odd length, and are fairly close to balanced, so one >>>>ought to be able to find some truncated Gold codes of even length
    (drop last bit) that are exactly balanced. We need only four such >>>>symbol codes, and a 16-bit code would allow the optical rate to be 16 >>>>times the code (ADC output) rate.

    There must be a steady stream of ADC symbols, even if ADC output is >>>>zero, to keep the SFP AGC stable.

    Generation. Drive a 16-line demux with the optical clock. Make or >>>>don't make connections from the demux to an adder, as dictated by the >>>>symbol to be sent. The adder output is used to drive the SFP TX
    input.

    Reception. Lock a phase-lock loop to the optical flash rate, to >>>>recover the optical clock.

    Have one correlator per symbol type, all running in parallel. Given >>>>the near-perfect correlation behavior of Gold codes, the correlator >>>>output will be roughly one unit amplitude except at the pattern
    center, where the peak will be about 16 units, so a threshold set at 8 >>>>units should enable perfect recovery.

    The frame sync symbol is used if we are switching between a reference >>>>voltage and the strain-gage output voltage, to mark where reference >>>>starts. May need an ref-end symbol.

    If no correlator peaks for more than a few symbol periods, complain. >>>>The SFP will also tell you if any optical power is being received, if
    I recall.

    Design the receiver first, as it's usually the harder of the two, then >>>>design the transmitter to make the receiver happy.

    It's really simple; just move the 1-bit logic level output of the ADC
    to the destination and recover a clock to know where the bits are.
    We'd clock the ADC at 20 or maybe 10 MHz.

    If I'm understanding the timing diagram on datasheet page 4, one can
    have a long string of ones, or of zeros, depending on the input analog >>voltage, which has fairly low bandwidth and so can linger at a voltage
    for very long durations.

    Of course voltages near the negative rail have to get close to 0% duty
    cycle, low bit density. I can avoid that by not allowing more than,
    say, +-250 mV.

    I'd assume that you would prefer not to do that.

    If both zero and one MDATA samples are each coded with a DC balanced
    pattern, there is no need to restrict the voltage range.


    Delta-sigma "noise shapes" to push the data spectrum up, namely avoid
    low frequency components in the duty cycle.

    This MDATA signal seems to be pulse-width modulated,not sigma-delta
    (despite the name), sampled at the ADC clock rate. What is being
    transmitted is in fact an absolute voltage value, with some
    quantization noise added. See datasheet page 16.

    No idea why they talk of sigma-delta. Certainly was confusing me.

    Maybe the sigma-delta stuff is buried in the front half of the "ADC".
    There was talk of an internal 16-bit register somewhere. It could be accumulating the up/down change pulses, the current value of this
    register being what is pulse-width modulated and transmitted back to
    earth.


    It's these long rafts of ones or zeros that I worry will baffle the
    SFP's AGC function, causing data-dependent link failures.

    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    Yes. Basically, what we are discussing here is how long the symbol
    pattern should be. You still need a way to decode that isn't
    vulnerable to frame-shift errors.

    For which you need long strings of either kind of symbol (zero or one)
    to decode in exactly one way, not using the end of one symbol and the
    start of the next to declare an ADC sample. So the pattern cannot be
    too short or too simple.

    Digital correlation receivers are pretty simple, basically a shift
    register with outputs being summed, half being direct and half being
    inverted.

    When the sought-for pattern is centered in the shift register, the
    summer emits a peak of amplitude N. Otherwise, the output amplitude
    is roughly zero, max unity, where N is the length of the pattern (and
    thus shift register) in bits. No computer needed.


    What make and model of SFP are you looking at?

    I've evaluated a bunch of them. I'll have to look that up.

    If they all claim the enet PHY mentioned later, the AGC time constant
    ought to be about the same, most likely being specified in the
    relevant enet standard, to ensure that SFP modules are
    interchangeable.



    But one could use two Gold-code symbols, encoding MDATA one and MDATA
    zero, and a pair of correlators at the other end of the fiber-optic
    link to recover the original MDATA stream.

    And, optical SNR matters. If the minimum SNR is high, the tolerance
    for non-zero DC balance, is increased. What is the maximum optical
    cable length contemplated?

    A couple of km, maybe. Singlemode can go 10s of km.

    Singlemode fiber is cheap, and will certainly do the job. The
    Ethernet PHY you want for this is "1000BASE-LX", as defined in IEEE
    802.3 Clause 38. This is a common Gigabit Ethernet via optical fiber
    PHY.

    Going one-fifth the max reach should yield ample optical SNR, so long
    ate there are few optical connectors


    Joe Gwinn

    --- SoupGate-Win32 v1.05
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  • From Jasen Betts@21:1/5 to John Larkin on Fri Aug 5 22:56:57 2022
    On 2022-08-04, John Larkin <jlarkin@highland_atwork_technology.com> wrote:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <usenet@revmaps.no-ip.org> wrote:

    On 2022-08-03, jlarkin@highlandsniptechnology.com <jlarkin@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM

    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    And also vise-versa but only then.

    still the above looks the same as manchester( 0 1 d )

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    So now it's manchester( 1 d ) what does idle look like?

    to get a DC balanced form that is easy to generate and decode. It's terrifyingly clever.

    FM coding seems easier

    --
    Jasen.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to langwadt@fonz.dk on Fri Aug 5 17:09:39 2022
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?

    The decoder is a 3-bit shift register and a 2-input xnor gate.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jasen Betts@21:1/5 to John Larkin on Fri Aug 5 23:13:37 2022
    On 2022-08-05, John Larkin <jlarkin@highland_atwork_technology.com> wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    Of course voltages near the negative rail have to get close to 0% duty
    cycle, low bit density. I can avoid that by not allowing more than,
    say, +-250 mV.

    Delta-sigma "noise shapes" to push the data spectrum up, namely avoid
    low frequency components in the duty cycle.


    It's these long rafts of ones or zeros that I worry will baffle the
    SFP's AGC function, causing data-dependent link failures.

    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    Biphase-M code (FM) does that for 2 slots per data bit instead of 4

    It seems like you're reinventing the wheel, and having rejected the
    triangular wheel for the square wheel are impressed by the
    improvement it gives.

    --
    Jasen.

    --- SoupGate-Win32 v1.05
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  • From John Larkin@21:1/5 to usenet@revmaps.no-ip.org on Fri Aug 5 17:03:46 2022
    On Fri, 5 Aug 2022 23:13:37 -0000 (UTC), Jasen Betts
    <usenet@revmaps.no-ip.org> wrote:

    On 2022-08-05, John Larkin <jlarkin@highland_atwork_technology.com> wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    Of course voltages near the negative rail have to get close to 0% duty
    cycle, low bit density. I can avoid that by not allowing more than,
    say, +-250 mV.

    Delta-sigma "noise shapes" to push the data spectrum up, namely avoid
    low frequency components in the duty cycle.


    It's these long rafts of ones or zeros that I worry will baffle the
    SFP's AGC function, causing data-dependent link failures.

    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    Biphase-M code (FM) does that for 2 slots per data bit instead of 4


    A long string of 0s is ambiguous. Harder to decode.


    It seems like you're reinventing the wheel, and having rejected the >triangular wheel for the square wheel are impressed by the
    improvement it gives.

    I didn't invent the 4-bit version. I wish I had.

    But thank you for your polite and constructive assistance.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to Mike Monett on Fri Aug 5 21:19:27 2022
    Mike Monett wrote:
    Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero deadband
    PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234 patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102 34.pdf
    The schematics redrawn by the patent artist are fun, if not super
    intelligible. Before I go trying to follow them, did the artist get
    them right?

    Cheers

    Phil Hobbs




    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Mike Monett@21:1/5 to Mike Monett on Sat Aug 6 04:06:03 2022
    Mike Monett <spamme@not.com> wrote:

    [...]

    Of course, there are much simpler ways of coupling a pair of d-flops to
    a loop filter, but I won't go through them now. Maybe later. The key is
    to make the circuit fast enough to follow the short pulses from the
    d-flops around zero phase error.

    I forgot - I included one method in FASTDIOD.ASC in https://tinyurl.com/2p97vht8


    --
    MRM

    --- SoupGate-Win32 v1.05
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  • From Mike Monett@21:1/5 to Phil Hobbs on Sat Aug 6 03:56:37 2022
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    Mike Monett wrote:
    Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >>>>>> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >>>>>> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero
    deadband PFD in 1970, and Memorex patented it. It is shown on page 3 of
    my '234 patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38
    102 34.pdf
    The schematics redrawn by the patent artist are fun, if not super intelligible. Before I go trying to follow them, did the artist get
    them right?

    Cheers

    Phil Hobbs

    I don't know. I never checked them. As you well know yourself, Patent
    attorneys take the most well layed out schematics and turn them into
    scrambled spaghetti. There were 5 pages of this crap and I didn't have time
    to go through them all. I had left Memorex by that time and was working for Diablo Corporation (now extinct), so all I did was sign the papers and take
    the mandantory $1.00 to transfer ownership.

    Trying to follow the schematic may be difficult. The circuit had to switch between full phase/frequency detection to MFM decoding, as well as
    synchronize the loop as quickly as possible after the address mark. This is a short section of erased data to signify an area of all data bits (all ones)
    to get the loop locked up on the correct data separator window.

    The essential part of the circuit is what happens after the pair of d-flops that form the PFD. By nature, PFD's cannot have deadband. Deadband occurs
    when either the pullup or pulldown digital to analog conversion has a long propagation delay so it does not respond to short pulses around zero phase error.

    The critical area is the quad pairs of 2N4209/2N5851 differential pairs arranged so they cannot saturate.

    This is what I-forget-his-name did in the MC4044. The ASC file is located in https://tinyurl.com/2p97vht8

    His input transistor for the pullup side, Q1, saturated as soon as the DATA d-flop, U1, was clocked. Consequently, it did not come out of saturation for
    a long time after both d-flops were reset. This produced the deadband. He
    could easily have avoided this problem by adding a Baker clamp at the input
    of Q1:

    https://en.wikipedia.org/wiki/Baker_clamp

    I avoided this problem by setting the current through the input differential pair to 20ma and 10mA. When driving 50 Ohms, this produces 1V and 0.5V that drives the output pair of differential amplifiers. I could have dropped the pulldown emitter resistor to 510 ohms, but there were so many other issues
    with trying to get foreign parts through Memorex purchasing that I was simply swamped. It worked, time for refinement later.

    Anyway, the critical thing is the input differential pair did not saturate,
    and there was no deadband. I verified this with countless hours under the
    scope hood. If you have ever spent time under a scope hood, you know about
    the band it etches around your eyes. I wore that band for 9 months while I
    was developing this circuit. The deadband problem was solved.

    Of course, there are much simpler ways of coupling a pair of d-flops to a
    loop filter, but I won't go through them now. Maybe later. The key is to make the circuit fast enough to follow the short pulses from the d-flops around
    zero phase error.





    --
    MRM

    --- SoupGate-Win32 v1.05
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  • From Clifford Heath@21:1/5 to Jasen Betts on Sat Aug 6 16:35:13 2022
    On 6/8/22 09:13, Jasen Betts wrote:
    It seems like you're reinventing the wheel, and having rejected the triangular wheel for the square wheel are impressed by the
    improvement it gives.
    Well, at least a Reuleux Triangle rolls with constant width! <https://en.wikipedia.org/wiki/Reuleaux_triangle>

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sat Aug 6 02:26:16 2022
    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John S@21:1/5 to Phil Hobbs on Sat Aug 6 06:03:03 2022
    On 8/4/2022 10:20 PM, Phil Hobbs wrote:
    John S wrote:
    On 8/3/2022 4:29 PM, John Larkin wrote:
    On Wed, 3 Aug 2022 14:28:30 -0400, Phil Hobbs
    <pcdhSpamMeSenseless@electrooptical.net> wrote:

    jlarkin@highlandsniptechnology.com wrote:
    On Wed, 3 Aug 2022 12:03:11 -0400 (EDT), Martin Rid
    <martin_riddle@verison.net> wrote:

    jlarkin@highlandsniptechnology.com Wrote in message:r
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?I >>>>>>> want to send data over an SFP optical link, in 6-bit things.   0 >>>>>>> 1 1 0 d \d   repeated, roughly 100 Mbits/secis DC balanced, which >>>>>>> SFP likes.

    I would still consider it a byte, but sixbit.
    You could always call it braille.

    Cheers

    Maybe "frame" sounds better than "clump."



    Or 'clod'.   Alternatives abound. ;)

    I'd go with sextet (or sestet, if you're feeling poetic).

    Cheers

    Phil Hobbs

    Now one of my guys claims that all we need is

    1 0 d1 \d1 1 0 d2 \d2 .... etc

    four bits per chunk to recover data d. Which is a nibble. I can still
    call each 4 bits a frame.


    4 bit is a nybble. Or a dollar.

    Nah, two bits is a quarter, so 8 bits is a dollar.

    Cheers

    Phil Hobbs


    Oh! You're right! Thanks.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From jlarkin@highlandsniptechnology.com@21:1/5 to langwadt@fonz.dk on Sat Aug 6 08:08:26 2022
    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010




    Try it. Draw a string of such 4-bit frames, with some 1s and 0s
    encoded, as if they were in a long shift register.

    Make a 3-bit wide "caliper" with one xnor gate, namely xnor bits n and
    n+2. Slide it along the string of bits and see what comes out.

    Actually, it's easier to think about using 1 0 \d d encoding and use
    an xor gate. My guy did it the first way.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Sat Aug 6 08:08:47 2022
    On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's terrifyingly clever.

    This sequence is also pathological for continuous one data. You end up with 10101010 with no way to distinguish the frame bits from the data.

    With Manchester data you get alignment anytime there is a change in polarity of the data, either 1>0 or 0>1, because you end up with a single transition in the bit time, rather than two that you get with continuous data.

    There is nothing magical about the pattern 1 0 d \d.

    --

    Rick C.

    -+ Get 1,000 miles of free Supercharging
    -+ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
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  • From jlarkin@highlandsniptechnology.com@21:1/5 to All on Sat Aug 6 07:29:20 2022
    On Sat, 6 Aug 2022 16:35:13 +1000, Clifford Heath <no_spam@please.net>
    wrote:

    On 6/8/22 09:13, Jasen Betts wrote:
    It seems like you're reinventing the wheel, and having rejected the
    triangular wheel for the square wheel are impressed by the
    improvement it gives.
    Well, at least a Reuleux Triangle rolls with constant width! ><https://en.wikipedia.org/wiki/Reuleaux_triangle>

    That, for some weird reason, reminds me of a DDS frequency synthesizer
    variant that we invented on Friday. Maybe I'll post that and see how
    much hostility that one inspires.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Sat Aug 6 08:16:12 2022
    On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's terrifyingly clever.

    Here's a simple and effective data pattern, d \d \d d. Now you have Manchester encoding of a stream which consists of the data and the inverted data, d \d. Very easy to modulate and demodulate along with data redundancy for error checking. No need for
    wasteful formatting overhead.

    Encoding is blindingly simple. The output is the XOR of the data and a two bit, binary counter. The decode is the usual Manchester decode giving two bits, d and \d which you may use as you choose. It literally doesn't get much simpler than this.

    --

    Rick C.

    +- Get 1,000 miles of free Supercharging
    +- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Sat Aug 6 08:20:28 2022
    On Thursday, August 4, 2022 at 7:40:51 PM UTC-4, John Larkin wrote:
    On Thu, 04 Aug 2022 16:40:53 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Wed, 03 Aug 2022 14:48:12 -0700, John Larkin ><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 16:32:53 -0400, Joe Gwinn <joeg...@comcast.net> >>wrote:

    On Wed, 03 Aug 2022 10:19:49 -0700, John Larkin >>><jlarkin@highland_atwork_technology.com> wrote:

    On Wed, 03 Aug 2022 12:35:16 -0400, Joe Gwinn <joeg...@comcast.net> >>>>wrote:

    On Wed, 03 Aug 2022 08:52:08 -0700, jla...@highlandsniptechnology.com >>>>>wrote:

    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    It would still be a byte. Univac 1108, with 36-bit words.

    A byte was always a fraction of a word, but the length of a word was >>>>>whatever the computer was designed for. All sizes were tried.

    I've worked on digital computers with the following word sizes (in >>>>>bits): 12, 16, 24, 32, 36, 48, 64.

    There were just as many floating-point formats.

    Now days, it has settled down, and words are multiples of 8 bits in >>>>>size, usually a power of two. And all FP is IEEE.

    The standards folk came up with "octet" because byte was so >>>>>ill-defined.

    Half an octet was sometimes called a nybble. And so on.


    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.

    If you use 8-bit patterns (best for component availability), but use >>>>>only the DC balanced subset, does that suffice?

    We could do 8b10b, but that would need an FPGA to generate and >>>>receive. I'm thinking about a spare-time thing that I could design >>>>without an FPGA or uP, all hardware. My digital people are swamped >>>>with big projects and I need something fun to design.


    Or, turn it around. Figure out how many DC-balanced patterns you >>>>>need, double it (for growth), and figure out long a word is needed. >>>>>Don't forget to include some control patterns.


    The data is a 1-bit steam from a delta-sigma ADC. I just want to >>>>transport it over fiber, and SFP is the easy way to do that. But SFP >>>>is intended for telecom, ac coupled, intolerant of dc imbalance. Most >>>>SFPs won't pass anything below about 1 MHz. But they are crazy fast >>>>and have great AGC.

    Is it 100 million bits per second, or symbols per second?

    The ADUM7703 can be clocked up to 20 MHz, but we really don't need to
    do that. 10M would be plenty.


    What is being digitized? Voice? Data of some kind?

    Some customer's analog voltage. Might be a strain gage load cell, for >>example. We'd have some input ranges.

    All very low bandwidth stuff. Is it required to transmit absolute
    values, or is just the "AC" part enough?

    Sounds like for instance actual strain values are desired.



    Is there a maximum latency and latency jitter requirement?

    Neither, actually. I just want to transport the ADC output correctly.

    OK.



    One-bit delta samples are usually signed, so the minimum is two >>>symbols. If the voltage being sent is zero, then we'll get a steady >>>+,-,+,-,+, stream, which will have very strong RF spurs and thus >>>emissions, so need to break this up.

    The ADC has a one-bit output over +-320 mV input, and averages 50%
    duty cycle at 0 volts in. I just want to transport that bit over a
    fiber link.

    So the ADC output is a signed bit per sample.
    It's an ADUM7703 delta-sigma a/d converter; it doesn't actually sample
    but runs its stuff continuously. It has a clock input and a single bit
    logic output. The duty cycle of the output reports the analog input:
    0% duty cycle is -320 mV and 100% is +320 mV. It's fully isolated and
    crazy precise. Once we convey that logic level to a destination, we "decimate" it into a 16 or 18 or 20 bit value that reflects the input voltage. The decimation is typically digital, a sinc3 filter, but I
    might do it all analog in this case. Decimation becomes a lowpass
    filter.



    A zero symbol makes it three, and an idle symbol, makes it four >>>symbols.


    Gigabit Ethernet does something like this, only grander, with two >>>>>patterns for every possible symbol to be sent, and they track current >>>>>DC balance, and choose which pattern to use that will reduce the >>>>>running DC balance.

    8b10b does elaborate long-term DC balancing like that. Too much work. >>>>
    SFPs usually tolerate a little DC imbalance. You can send PWM at, say, >>>>35% to 65%.

    Yes, too much trouble. But if you use table lookup, you can get close >>>enough.

    I don't want an FPGA or a uP in this box. All my coder-people are too >>busy on other projects now. So, a few gates and flipflops.

    OK. This too can be done, given a large ratio between optical bit
    rate and ADC bitrate.

    The AGC in the SFP is pretty fast, but the optical bitrate must be
    much faster, or the AGC will flatten the desired signal. The SFP
    datasheet should define the AGC response speed.
    The combination of AGC and AC coupling makes SFPs not work well at
    data rates below about 1 MHz. That varies a lot with specific parts.

    So, pick a convenient optical signaling (flash) rate well above the
    AGC reaction speed, so you will be able to recover the sent pattern at
    the SFP output.

    Here is one possible design:

    Choose a ADC sample rate a fraction of the optical rate. The fraction
    is determined by choosing orthogonal codes to represent +1, zero, or
    -1 ADC outputs to be sent. Also need a frame-start symbol.

    The orthogonal codes are chosen from the standard Gold Codes:

    .<https://en.wikipedia.org/wiki/Gold_code>

    The codes have odd length, and are fairly close to balanced, so one
    ought to be able to find some truncated Gold codes of even length
    (drop last bit) that are exactly balanced. We need only four such
    symbol codes, and a 16-bit code would allow the optical rate to be 16
    times the code (ADC output) rate.

    There must be a steady stream of ADC symbols, even if ADC output is
    zero, to keep the SFP AGC stable.

    Generation. Drive a 16-line demux with the optical clock. Make or
    don't make connections from the demux to an adder, as dictated by the >symbol to be sent. The adder output is used to drive the SFP TX
    input.

    Reception. Lock a phase-lock loop to the optical flash rate, to
    recover the optical clock.

    Have one correlator per symbol type, all running in parallel. Given
    the near-perfect correlation behavior of Gold codes, the correlator
    output will be roughly one unit amplitude except at the pattern
    center, where the peak will be about 16 units, so a threshold set at 8 >units should enable perfect recovery.

    The frame sync symbol is used if we are switching between a reference >voltage and the strain-gage output voltage, to mark where reference
    starts. May need an ref-end symbol.

    If no correlator peaks for more than a few symbol periods, complain.
    The SFP will also tell you if any optical power is being received, if
    I recall.

    Design the receiver first, as it's usually the harder of the two, then >design the transmitter to make the receiver happy.
    It's really simple; just move the 1-bit logic level output of the ADC
    to the destination and recover a clock to know where the bits are.
    We'd clock the ADC at 20 or maybe 10 MHz.

    Or you can use Manchester encoding to encode the clock and easily recover it at the other end. Data bits with the clock for free! I guess some people don't like free.

    --

    Rick C.

    ++ Get 1,000 miles of free Supercharging
    ++ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to lang...@fonz.dk on Sat Aug 6 08:54:30 2022
    On Friday, August 5, 2022 at 4:41:35 PM UTC-4, lang...@fonz.dk wrote:
    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010
    isn't that what you get with 1 0 d \d and d = 1 ?

    which means that a simple running decoder can mis-frame
    the clumps.
    won't you have that problem with all possible ways of using 4 bit?

    I was thinking of sending d \d \d d, and that lets you align at a first level, but still leaves room for misalignment so the recovered data is \d rather than d.

    What is wrong with sending a frame that is DC balanced over multiple data bits, even if not each one? 1 1 d0 \d0 0 0 d1 \d1 should be easy to sync to, is DC balanced and has unambiguous alignment. Any given data bit will be the middle two bits of 0011,
    0101, 1010 or 1100. Because the frame bits are 11 or 00, they can't be confused with data in these 4 bit sequences.

    Encoding is just a 3 bit counter and a few gates. Decoding can be done with a 4 bit shift register, an inverter and an 8 to 1 multiplexer, three SSI devices. That's pretty simple.

    --

    Rick C.

    --- Get 1,000 miles of free Supercharging
    --- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to Ricky on Sat Aug 6 09:09:34 2022
    On Saturday, August 6, 2022 at 11:54:35 AM UTC-4, Ricky wrote:
    On Friday, August 5, 2022 at 4:41:35 PM UTC-4, lang...@fonz.dk wrote:
    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010
    isn't that what you get with 1 0 d \d and d = 1 ?

    which means that a simple running decoder can mis-frame
    the clumps.
    won't you have that problem with all possible ways of using 4 bit?
    I was thinking of sending d \d \d d, and that lets you align at a first level, but still leaves room for misalignment so the recovered data is \d rather than d.

    What is wrong with sending a frame that is DC balanced over multiple data bits, even if not each one? 1 1 d0 \d0 0 0 d1 \d1 should be easy to sync to, is DC balanced and has unambiguous alignment. Any given data bit will be the middle two bits of 0011,
    0101, 1010 or 1100. Because the frame bits are 11 or 00, they can't be confused with data in these 4 bit sequences.

    Encoding is just a 3 bit counter and a few gates. Decoding can be done with a 4 bit shift register, an inverter and an 8 to 1 multiplexer, three SSI devices. That's pretty simple.

    Or, decode can be done with the shift register and a pair of 2-input XOR gates and an AND gate. I almost missed that.

    --

    Rick C.

    --+ Get 1,000 miles of free Supercharging
    --+ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sat Aug 6 09:36:42 2022
    lørdag den 6. august 2022 kl. 17.08.37 UTC+2 skrev jla...@highlandsniptechnology.com:
    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >> >> >> >
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >> >> >> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit >> >> >> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >> >> >> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010



    Try it. Draw a string of such 4-bit frames, with some 1s and 0s
    encoded, as if they were in a long shift register.

    Make a 3-bit wide "caliper" with one xnor gate, namely xnor bits n and
    n+2. Slide it along the string of bits and see what comes out.

    Actually, it's easier to think about using 1 0 \d d encoding and use
    an xor gate. My guy did it the first way.

    but you still need to use 1010, in a long string of those you can't tell where the 4 bit start

    1010101010
    xx10101010

    what are you going to clock the shift with?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sat Aug 6 10:52:29 2022
    On Fri, 5 Aug 2022 21:02:06 -0000 (UTC), Mike Monett <spamme@not.com>
    wrote:

    Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero deadband
    PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234 >patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102 >34.pdf

    My favorite phase detector is a single d-flop. Clock from received
    data, poke the local VCXO square wave into D.

    It makes an early/late decision every data rising edge, and can
    produce picosecond time alignment and picosecond jitter.

    It's basically infinite gain and immune to analog errors. A
    differential ECL flop is best, like NB7V52.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to langwadt@fonz.dk on Sat Aug 6 10:44:05 2022
    On Sat, 6 Aug 2022 09:36:42 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 17.08.37 UTC+2 skrev jla...@highlandsniptechnology.com:
    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >> >> >> >> >
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >> >> >> >> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit >> >> >> >> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >> >> >> >> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010



    Try it. Draw a string of such 4-bit frames, with some 1s and 0s
    encoded, as if they were in a long shift register.

    Make a 3-bit wide "caliper" with one xnor gate, namely xnor bits n and
    n+2. Slide it along the string of bits and see what comes out.

    Actually, it's easier to think about using 1 0 \d d encoding and use
    an xor gate. My guy did it the first way.

    but you still need to use 1010, in a long string of those you can't tell where the 4 bit start

    1010101010
    xx10101010

    what are you going to clock the shift with?

    Of course we need an 80 MHz PLL on the receive end to clock the bits;
    that's easy. If I clock the ADC at 10 MHz, the bit rate and PLL are 40
    MHz, which is handy because we stock a nice 40 MHz VCXO.

    I don't care where a bit "starts", I just need to recover a 20 Mbps
    delta-sigma stream to poke into a decimator.

    Try it.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sat Aug 6 11:00:50 2022
    lørdag den 6. august 2022 kl. 19.44.16 UTC+2 skrev John Larkin:
    On Sat, 6 Aug 2022 09:36:42 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 17.08.37 UTC+2 skrev jla...@highlandsniptechnology.com:
    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >> >> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >> >> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >> >> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >> >> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010



    Try it. Draw a string of such 4-bit frames, with some 1s and 0s
    encoded, as if they were in a long shift register.

    Make a 3-bit wide "caliper" with one xnor gate, namely xnor bits n and
    n+2. Slide it along the string of bits and see what comes out.

    Actually, it's easier to think about using 1 0 \d d encoding and use
    an xor gate. My guy did it the first way.

    but you still need to use 1010, in a long string of those you can't tell where the 4 bit start

    1010101010
    xx10101010

    what are you going to clock the shift with?
    Of course we need an 80 MHz PLL on the receive end to clock the bits;
    that's easy. If I clock the ADC at 10 MHz, the bit rate and PLL are 40
    MHz, which is handy because we stock a nice 40 MHz VCXO.

    I don't care where a bit "starts", I just need to recover a 20 Mbps delta-sigma stream to poke into a decimator.

    but you said:
    "
    Cute. But pattern 1010 1010

    has an embedded 1010

    which means that a simple running decoder can mis-frame
    the clumps.
    "

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to langwadt@fonz.dk on Sat Aug 6 14:19:10 2022
    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse
    whenever the desired pattern is in the shift register, even if it
    happens to find the pattern between two correctly-framed instances of
    the pattern.

    What's needed is to choose a pattern that will also ensure correct
    framing in an arbitrary random string of one and zero symbols. This
    is a slightly stronger requirement than orthogonal: The symbols must
    be a good synch pattern as well. With only two kinds of symbol, it
    ought to be possible, given a sufficiently long pattern.

    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Phil Hobbs@21:1/5 to John Larkin on Sat Aug 6 14:28:10 2022
    John Larkin wrote:
    On Fri, 5 Aug 2022 21:02:06 -0000 (UTC), Mike Monett <spamme@not.com>
    wrote:

    Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >>>>>> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >>>>>> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero deadband
    PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234
    patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102 >> 34.pdf

    My favorite phase detector is a single d-flop. Clock from received
    data, poke the local VCXO square wave into D.

    It makes an early/late decision every data rising edge, and can
    produce picosecond time alignment and picosecond jitter.

    It's basically infinite gain and immune to analog errors. A
    differential ECL flop is best, like NB7V52.


    $18 in hundreds. Got a second fave for us picosecond proles? ;)

    Cheers

    Phil Hobbs

    --
    Dr Philip C D Hobbs
    Principal Consultant
    ElectroOptical Innovations LLC / Hobbs ElectroOptics
    Optics, Electro-optics, Photonics, Analog Electronics
    Briarcliff Manor NY 10510

    http://electrooptical.net
    http://hobbs-eo.com

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Mike Monett@21:1/5 to Phil Hobbs on Sat Aug 6 19:47:02 2022
    Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    John Larkin wrote:

    [...]

    My favorite phase detector is a single d-flop. Clock from received
    data, poke the local VCXO square wave into D.

    It makes an early/late decision every data rising edge, and can
    produce picosecond time alignment and picosecond jitter.

    It's basically infinite gain and immune to analog errors. A
    differential ECL flop is best, like NB7V52.


    $18 in hundreds. Got a second fave for us picosecond proles? ;)

    Cheers

    Phil Hobbs

    I disagree with the claims. However, a MC100EP52DT is CAD$3.47 at
    Rochester, and a MC100EP52DTG is CAD$4.13 at Arrow, QTY 1:

    https://octopart.com/search?q=100ep52&currency=CAD&specs=0





    --
    MRM

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jeroen Belleman@21:1/5 to John Larkin on Sat Aug 6 22:32:11 2022
    On 2022-08-06 19:52, John Larkin wrote:
    On Fri, 5 Aug 2022 21:02:06 -0000 (UTC), Mike Monett <spamme@not.com>
    wrote:

    Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >>>>>> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >>>>>> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero deadband
    PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234
    patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102 >> 34.pdf

    My favorite phase detector is a single d-flop. Clock from received
    data, poke the local VCXO square wave into D.

    It makes an early/late decision every data rising edge, and can
    produce picosecond time alignment and picosecond jitter.

    It's basically infinite gain and immune to analog errors. A
    differential ECL flop is best, like NB7V52.


    Infinite (OK, very large) gain around the lock target and zero
    gain elsewhere. Not something you really want in a well behaved
    loop. You really want constant loop gain.

    Jeroen Belleman

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to langwadt@fonz.dk on Sat Aug 6 17:07:20 2022
    On Sat, 6 Aug 2022 11:00:50 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 19.44.16 UTC+2 skrev John Larkin:
    On Sat, 6 Aug 2022 09:36:42 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 17.08.37 UTC+2 skrev jla...@highlandsniptechnology.com:
    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >> >> >> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >> >> >> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >> >> >> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >> >> >> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010



    Try it. Draw a string of such 4-bit frames, with some 1s and 0s
    encoded, as if they were in a long shift register.

    Make a 3-bit wide "caliper" with one xnor gate, namely xnor bits n and
    n+2. Slide it along the string of bits and see what comes out.

    Actually, it's easier to think about using 1 0 \d d encoding and use
    an xor gate. My guy did it the first way.

    but you still need to use 1010, in a long string of those you can't tell where the 4 bit start

    1010101010
    xx10101010

    what are you going to clock the shift with?
    Of course we need an 80 MHz PLL on the receive end to clock the bits;
    that's easy. If I clock the ADC at 10 MHz, the bit rate and PLL are 40
    MHz, which is handy because we stock a nice 40 MHz VCXO.

    I don't care where a bit "starts", I just need to recover a 20 Mbps
    delta-sigma stream to poke into a decimator.

    but you said:
    "
    Cute. But pattern 1010 1010

    has an embedded 1010

    which means that a simple running decoder can mis-frame
    the clumps.
    "

    As I said, try it.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sat Aug 6 17:08:55 2022
    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen ><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >>> >> >> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >>> >> >> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse
    whenever the desired pattern is in the shift register, even if it
    happens to find the pattern between two correctly-framed instances of
    the pattern.

    A 2-input xnor is not a correlation receiver.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Mike Monett@21:1/5 to Jeroen Belleman on Sun Aug 7 00:49:42 2022
    Jeroen Belleman <jeroen@nospam.please> wrote:

    On 2022-08-06 19:52, John Larkin wrote:

    [...]

    My favorite phase detector is a single d-flop. Clock from received
    data, poke the local VCXO square wave into D.

    It makes an early/late decision every data rising edge, and can
    produce picosecond time alignment and picosecond jitter.

    It's basically infinite gain and immune to analog errors. A
    differential ECL flop is best, like NB7V52.


    Infinite (OK, very large) gain around the lock target and zero
    gain elsewhere. Not something you really want in a well behaved
    loop. You really want constant loop gain.

    Jeroen Belleman

    A single d-flop is a phase detector, not a frequency detector. It shares
    the same lock characteristic with an XOR and a double balanced mixer,
    although the XOR and DBM are quadrature detectors, where the d-flop is in phase.

    It has the highly desirable property of retaining the same gain on
    harmonics, where the XOR and double balanced mixer both lose gain.

    It takes the addition of a second d-flop and a feedback gate to create a frequency/phase detector. However, it will no longer work on harmonics.

    For more information on quadrature detectors, see "Operation of Phase Comparator PC1" on page 9 of

    https://www.ti.com/lit/an/scha003b/scha003b.pdf





    --
    MRM

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to Joe Gwinn on Sat Aug 6 18:59:21 2022
    On Saturday, August 6, 2022 at 2:19:21 PM UTC-4, Joe Gwinn wrote:
    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >> >> >> >
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >> >> >> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit >> >> >> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >> >> >> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010
    Will that even work? A correlation receiver with emit a pulse
    whenever the desired pattern is in the shift register, even if it
    happens to find the pattern between two correctly-framed instances of
    the pattern.

    What's needed is to choose a pattern that will also ensure correct
    framing in an arbitrary random string of one and zero symbols. This
    is a slightly stronger requirement than orthogonal: The symbols must
    be a good synch pattern as well. With only two kinds of symbol, it
    ought to be possible, given a sufficiently long pattern.

    No, the pattern Larkin describes will provide accurate data at all times. While the PLL will produce the 4x clock, there is no data clock without examining the recovered data using the XOR gate, as he describes. By monitoring the output of that "
    detector", there will be a transition when the data changes.

    So with initially, all 1 data, the decode will produce 1s on all 4x clock transitions. However, there is no way to detect the data clock, until the data changes yielding an edge in the data output, showing the data boundary in the 4x clock domain, and
    showing the alignment of the 1x data.

    This is not really an advantage over other schemes which also depend on the data changing to obtain alignment, such as simple Manchester.

    The method I described previously, with the pattern of 1 1 d0 \d0 0 0 d1 \d1 provides the same data density, and will synchronize unambiguously without regard to the data, because of the changing sync pattern. It also provides a data clock.

    --

    Rick C.

    -+- Get 1,000 miles of free Supercharging
    -+- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to jeroen@nospam.please on Sat Aug 6 20:09:33 2022
    On Sat, 06 Aug 2022 22:32:11 +0200, Jeroen Belleman
    <jeroen@nospam.please> wrote:

    On 2022-08-06 19:52, John Larkin wrote:
    On Fri, 5 Aug 2022 21:02:06 -0000 (UTC), Mike Monett <spamme@not.com>
    wrote:

    Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>>>>>>
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>>>>>> "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >>>>>>>>
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >>>>>>> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit >>>>>>> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >>>>>>> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero deadband >>> PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234
    patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102 >>> 34.pdf

    My favorite phase detector is a single d-flop. Clock from received
    data, poke the local VCXO square wave into D.

    It makes an early/late decision every data rising edge, and can
    produce picosecond time alignment and picosecond jitter.

    It's basically infinite gain and immune to analog errors. A
    differential ECL flop is best, like NB7V52.


    Infinite (OK, very large) gain around the lock target and zero
    gain elsewhere. Not something you really want in a well behaved
    loop. You really want constant loop gain.

    Jeroen Belleman

    What I want is a PLL that is time locked to a few picoseconds
    long-term and has about a ps of RMS jitter.

    https://www.highlandtechnology.com/DSS/V880DS.shtml

    https://www.dropbox.com/s/rb0fasr1flvvk51/NIF_Award.jpg?raw=1

    The d-flop phase detector annoys some people, but nothing else comes
    close.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to pcdhSpamMeSenseless@electrooptical. on Sat Aug 6 19:52:07 2022
    On Sat, 6 Aug 2022 14:28:10 -0400, Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

    John Larkin wrote:
    On Fri, 5 Aug 2022 21:02:06 -0000 (UTC), Mike Monett <spamme@not.com>
    wrote:

    Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com
    <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>>>>>>
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>>>>>> "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >>>>>>>>
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >>>>>>> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit >>>>>>> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >>>>>>> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?


    which means that a simple running decoder can mis-frame the clumps.

    won't you have that problem with all possible ways of using 4 bit?

    MFM coding is DC balanced and easy to encode. It is hard to decode:

    https://en.wikipedia.org/wiki/Modified_frequency_modulation

    It requires a PLL with zero deadband. I invented the first zero deadband >>> PFD in 1970, and Memorex patented it. It is shown on page 3 of my '234
    patent:

    https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US38102 >>> 34.pdf

    My favorite phase detector is a single d-flop. Clock from received
    data, poke the local VCXO square wave into D.

    It makes an early/late decision every data rising edge, and can
    produce picosecond time alignment and picosecond jitter.

    It's basically infinite gain and immune to analog errors. A
    differential ECL flop is best, like NB7V52.


    $18 in hundreds. Got a second fave for us picosecond proles? ;)

    Cheers

    Phil Hobbs

    Well, you can use a pokey flop like MC10EP51, or degrade yourself and
    use a 1 ns cmos flop, like NC7SV74, which will set you back about 13
    cents. But give up diff data+diff clock.





    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sat Aug 6 20:13:46 2022
    On Sun, 7 Aug 2022 00:49:42 -0000 (UTC), Mike Monett <spamme@not.com>
    wrote:

    Jeroen Belleman <jeroen@nospam.please> wrote:

    On 2022-08-06 19:52, John Larkin wrote:

    [...]

    My favorite phase detector is a single d-flop. Clock from received
    data, poke the local VCXO square wave into D.

    It makes an early/late decision every data rising edge, and can
    produce picosecond time alignment and picosecond jitter.

    It's basically infinite gain and immune to analog errors. A
    differential ECL flop is best, like NB7V52.


    Infinite (OK, very large) gain around the lock target and zero
    gain elsewhere. Not something you really want in a well behaved
    loop. You really want constant loop gain.

    Jeroen Belleman

    A single d-flop is a phase detector, not a frequency detector.

    Yes. PLL.

    It shares
    the same lock characteristic with an XOR and a double balanced mixer, >although the XOR and DBM are quadrature detectors, where the d-flop is in >phase.

    But the dflop gain is absurdly higher than an XOR or a mixer. An XOR
    with microvolt offsets makes picoseconds of time error and 1/f noise.

    Diode tempco in a mixer is worse.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jjlarkin@highlandtechnology.com on Sun Aug 7 12:17:54 2022
    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >>>> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >>>> >> >> >
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >>>> >> >> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit >>>> >> >> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >>>> >> >> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse
    whenever the desired pattern is in the shift register, even if it
    happens to find the pattern between two correctly-framed instances of
    the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Sun Aug 7 09:52:59 2022
    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin ><jjlarkin@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >>>>> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>>> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>>> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >>>>> >> >> >
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of >>>>> >> >> 1s.

    One of my guys, on his ferry ride, figured out how to add two bit >>>>> >> >> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's >>>>> >> >> terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse
    whenever the desired pattern is in the shift register, even if it
    happens to find the pattern between two correctly-framed instances of
    the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn

    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
    an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
    Any 0 sees a \d.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to John Larkin on Sun Aug 7 10:31:39 2022
    On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin ><jjla...@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net> >>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>><lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >>>>> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>>> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>>> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse
    whenever the desired pattern is in the shift register, even if it >>>happens to find the pattern between two correctly-framed instances of >>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn
    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
    an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
    Any 0 sees a \d.

    This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use.
    Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010
    while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a "good" reference to align the 1x clock to.

    Using the pattern 1 1 d1 \d1 0 0 d2 \d2 gets around this limitation and is still easy to generate, easy to decode and provides references to align the clock no matter what the data is or whether it changes. This decoder doesn't even require a separate
    PLL, clock timing being embedded in the data stream. A <2x clock will be able to provide a clock enable for data samples.

    --

    Rick C.

    -++ Get 1,000 miles of free Supercharging
    -++ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 7 11:12:46 2022
    søndag den 7. august 2022 kl. 18.18.07 UTC+2 skrev Joe Gwinn:
    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin <jjla...@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >><lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >>>> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >>>> >> >> >
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit >>>> >> >> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse
    whenever the desired pattern is in the shift register, even if it >>happens to find the pattern between two correctly-framed instances of >>the pattern.

    A 2-input xnor is not a correlation receiver.
    I guess I'm not visualizing the specific circuit used.

    I was bored so I drew it up in spice, the missing bit is generating you receiver clock from the data and resolving the half bit timing uncertainty that you can't tell where a the 4 bit 1010 starts in a long string of 1010101010101, so you'll need at
    least one 1001 to sync up
    and that was what discussion was mostly about

    Version 4
    SHEET 1 3268 680
    WIRE -544 -448 -592 -448
    WIRE -544 -352 -544 -368
    WIRE -592 -256 -592 -448
    WIRE -416 -256 -592 -256
    WIRE 496 -256 -256 -256
    WIRE 560 -256 496 -256
    WIRE -416 -208 -464 -208
    WIRE 528 -208 -240 -208
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    WIRE 640 64 640 0
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    WIRE 2720 64 2560 64
    WIRE 96 80 96 16
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    WIRE 688 80 656 80
    WIRE 1648 80 1648 -112
    WIRE 448 96 96 96
    WIRE 2880 96 2800 96
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    WIRE 1648 160 1280 160
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    WIRE 2080 160 2080 48
    WIRE 2080 160 2048 160
    WIRE 2128 160 2080 160
    WIRE 2352 160 2288 160
    WIRE 2560 160 2560 64
    WIRE 2560 160 2512 160
    WIRE 96 176 96 96
    WIRE 160 176 96 176
    WIRE 416 176 416 80
    WIRE 416 176 320 176
    WIRE 480 176 416 176
    WIRE 496 208 496 -256
    WIRE 544 208 496 208
    WIRE 656 208 656 80
    WIRE 656 208 608 208
    WIRE 864 208 800 208
    WIRE 1888 208 1840 208
    WIRE 2128 208 2096 208
    WIRE 2352 208 2336 208
    WIRE 160 224 80 224
    WIRE 448 224 448 96
    WIRE 448 224 336 224
    WIRE 480 224 480 176
    WIRE 544 224 480 224
    WIRE 80 288 80 224
    WIRE 800 288 800 208
    WIRE 800 288 80 288
    WIRE 80 304 80 288
    WIRE 1840 320 1840 208
    WIRE 2096 320 2096 208
    WIRE 2096 320 1840 320
    WIRE 2336 320 2336 208
    WIRE 2336 320 2096 320
    FLAG 80 384 0
    FLAG -544 -352 0
    FLAG 1840 400 0
    FLAG 1712 -32 0
    FLAG 400 -144 ADC_CLK
    FLAG 560 -256 ADC_Dp
    FLAG 560 -208 ADC_Dn
    FLAG 2880 96 DATA_OUT
    SYMBOL Digital\\dflop 240 128 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A1
    SYMBOL voltage 80 288 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value SINE(.5 .5 80e6)
    SYMBOL bv -544 -464 R0
    WINDOW 3 52 61 Left 2
    SYMATTR Value V=RAND(time*1e8)+0.25
    SYMATTR InstName B1
    SYMBOL Digital\\dflop 240 -80 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A2
    SYMBOL Digital\\dflop -336 -304 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A3
    SYMBOL Digital\\dflop 944 112 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A4
    SYMBOL Digital\\and 576 128 R0
    SYMATTR InstName A5
    SYMBOL Digital\\and 576 -80 R0
    SYMATTR InstName A6
    SYMBOL Digital\\dflop 1968 112 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A8
    SYMBOL Digital\\dflop 2208 112 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A9
    SYMBOL Digital\\dflop 2432 112 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A10
    SYMBOL Digital\\xor 2768 16 R0
    SYMATTR InstName A11
    SYMBOL voltage 1840 304 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V2
    SYMATTR Value SINE(.5 .5 80e6 15n 0)
    SYMBOL Digital\\and 720 32 R0
    SYMATTR InstName A7
    SYMBOL cap 1280 144 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 10p
    SYMBOL voltage 1712 -128 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V3
    SYMATTR Value 0.5
    SYMBOL res 1632 64 R0
    SYMATTR InstName R2
    SYMATTR Value 1k
    TEXT 1200 -504 Left 2 !.tran 10u
    TEXT -400 -472 Left 2 ;ADC sim
    TEXT 880 -440 Left 2 ;Transmitter
    TEXT 1480 -448 Left 2 ;Reciever
    RECTANGLE Normal 1088 432 -64 -496 2
    RECTANGLE Normal -624 -496 -144 -144 2
    RECTANGLE Normal 3040 432 1440 -496 2

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 7 11:22:18 2022
    søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin ><jjla...@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net> >>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>><lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin: >>>>> >> On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>whenever the desired pattern is in the shift register, even if it >>>happens to find the pattern between two correctly-framed instances of >>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn
    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
    an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
    Any 0 sees a \d.
    This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use.
    Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010
    while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a "good" reference to align the 1x clock to.


    Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then timing
    doesn't really matter

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to lang...@fonz.dk on Sun Aug 7 11:49:07 2022
    On Sunday, August 7, 2022 at 2:22:22 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net> wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin ><jjla...@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net> >>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>><lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin: >>>>> On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin: >>>>> >> On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate. >>>>
    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>whenever the desired pattern is in the shift register, even if it >>>happens to find the pattern between two correctly-framed instances of >>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn
    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
    Any 0 sees a \d.
    This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use.
    Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010
    while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a "good" reference to align the 1x clock to.

    Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then timing
    doesn't really matter

    That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \d1 0 0 d2 \d2 pattern doesn't have this problem and is still
    simple to encode and decode.

    --

    Rick C.

    +-- Get 1,000 miles of free Supercharging
    +-- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 7 12:09:27 2022
    søndag den 7. august 2022 kl. 20.49.12 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 2:22:22 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net> wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin ><jjla...@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net> >>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>><lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin: >>>>> On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin: >>>>> >> On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate. >>>>
    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>whenever the desired pattern is in the shift register, even if it >>>happens to find the pattern between two correctly-framed instances of
    the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn
    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d. Any 0 sees a \d.
    This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use.
    Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010
    while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a "good" reference to align the 1x clock to.

    Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then
    timing doesn't really matter
    That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \d1 0 0 d2 \d2 pattern doesn't have this problem and is still simple
    to encode and decode.


    stutter or even syncing might not even be an important, the uncertainty is 25ns at 20MHz and after decimation by 256 as in the datasheet
    the sample rate is 78.125kHz or 128us

    25ns is ~8m at the speed of light

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to lang...@fonz.dk on Sun Aug 7 13:12:52 2022
    On Sunday, August 7, 2022 at 3:09:31 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 20.49.12 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 2:22:22 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net> wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin ><jjla...@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin: >>>>> On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts >>>>> >> >> <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate. >>>>
    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>whenever the desired pattern is in the shift register, even if it >>>happens to find the pattern between two correctly-framed instances of
    the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn
    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
    an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d. Any 0 sees a \d.
    This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use.
    Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010
    while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a "good" reference to align the 1x clock to.

    Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then
    timing doesn't really matter
    That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \d1 0 0 d2 \d2 pattern doesn't have this problem and is still simple
    to encode and decode.

    stutter or even syncing might not even be an important, the uncertainty is 25ns at 20MHz and after decimation by 256 as in the datasheet
    the sample rate is 78.125kHz or 128us

    25ns is ~8m at the speed of light

    But sampling data when it is changing can cause missed bits and inserted bits, neither very useful.

    That's why the 1x clock has to see the data changes, to know to sample on other edges of the 4x clock.

    As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

    --

    Rick C.

    +-+ Get 1,000 miles of free Supercharging
    +-+ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 7 13:40:13 2022
    søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 3:09:31 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 20.49.12 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 2:22:22 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 19.31.43 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 12:53:12 PM UTC-4, John Larkin wrote:
    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin ><jjla...@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    lørdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts >>>>> >> >> <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>whenever the desired pattern is in the shift register, even if it
    happens to find the pattern between two correctly-framed instances of
    the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn
    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
    an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
    Any 0 sees a \d.
    This circuit requires a clock which will be 4x the actual data rate. It then produces a data stream and a 1x clock still needs to be generated. If the data is not changing, there are no edges to find an appropriate phase of the 4x clock to use.
    Guessing at a phase will result in setup and hold times that are defined by the logic delays, i.e. a race condition. As Lasse Langwadt Christensen has pointed out repeatedly, Larkin rejected a method because it would produce the pattern 101010101010
    while now choosing a scheme which has the same limitation. As long as this pattern is being sent, there is no way to find a "good" reference to align the 1x clock to.

    Johns circuit will work, but have a half bit timing uncertainty until you get a 1001 to sync the 4x divider up to, but since the data is from a delta sigma converter long strings of 10101010 will only happening when the input is railed and then
    timing doesn't really matter
    That is only true at that time. You still have to sync up the clock at some point. The result is you can get a stutter from the timing when it does finally sync up. Using the 1 1 d1 \d1 0 0 d2 \d2 pattern doesn't have this problem and is still
    simple to encode and decode.

    stutter or even syncing might not even be an important, the uncertainty is 25ns at 20MHz and after decimation by 256 as in the datasheet
    the sample rate is 78.125kHz or 128us

    25ns is ~8m at the speed of light
    But sampling data when it is changing can cause missed bits and inserted bits, neither very useful.

    That's why the 1x clock has to see the data changes, to know to sample on other edges of the 4x clock.

    as long as the 4x is PLL'ed to the data that's not an issue


    As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.


    so like this ?

    d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
    d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

    what edge would you use?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to lang...@fonz.dk on Sun Aug 7 14:32:08 2022
    On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
    As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

    so like this ?

    d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010

    When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?


    d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

    Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are
    the only indicators of valid data. Any other pattern is misalignment.

    This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.

    what edge would you use?

    Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock enable is generated. I would need to know more about the circuit receiving the data to give details. It'
    s not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don't recall what the data is being used for. I think Larkin finally explained some portion of
    that, but rather than give it up front, it's buried in the thread somewhere.

    --

    Rick C.

    ++- Get 1,000 miles of free Supercharging
    ++- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 7 15:02:14 2022
    søndag den 7. august 2022 kl. 23.32.13 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
    As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

    so like this ?

    d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
    When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?

    yes


    d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

    Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are the
    only indicators of valid data. Any other pattern is misalignment.

    This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.

    yes that should work, encoding is a bit more effort if you have to do it in discrete logic

    what edge would you use?
    Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock
    enable is generated.

    ah, I wrongly assumed you'd some how skip the pll and use the data as clock


    I would need to know more about the circuit receiving the data to give details. It's not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don't
    recall what the data is being used for. I think Larkin finally explained some portion of that, but rather than give it up front, it's buried in the thread somewhere.


    afaict it goes into a decimator, so the whole thing could run on the pll clock, or the much slower output could be synchronized

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to lang...@fonz.dk on Sun Aug 7 16:20:01 2022
    On Sunday, August 7, 2022 at 6:02:18 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 23.32.13 UTC+2 skrev Ricky:
    On Sunday, August 7, 2022 at 4:40:17 PM UTC-4, lang...@fonz.dk wrote:
    søndag den 7. august 2022 kl. 22.12.56 UTC+2 skrev Ricky:
    As I've said any number of times, using a pattern of 1 1 d1 \d1 0 0 d2 \d2 gives a transition which can be aligned to no matter what the data pattern is and has the same overhead. No worries of picking a wrong clock edge to collect data.

    so like this ?

    d=1,1,1,1,1: 11100010.11100010.11100010.11100010.11100010
    When the pattern 1100 appears, that is good data, value = 1. Then we also see 0101 which is also good data, value = 1. This is repeated five times for ten bits of valid data. You do understand that you send two data bits in each 8 bits of signal?

    yes

    d=0,0,0,0,0: 11010001.11010001.11010001.11010001.11010001

    Similar to before matching to 1010 gives valid data, value = 0. Matching to 0011 gives valid data, value = 0. As before, 2 data bits for every 8 bits transmitted. In this case, 10 bits of data in 40 bits of signal. These four specific patterns are
    the only indicators of valid data. Any other pattern is misalignment.

    This is easy to detect with a pair of xor gates (bit(0) xor bit (3)) and (bit(1) xor bit(2)). Or you can do it with an 8 to 1 mux and an inverter which allows any binary function of 4 inputs to be implemented.
    yes that should work, encoding is a bit more effort if you have to do it in discrete logic

    Encode is idiot simple. A 3 bit counter is decoded to send the appropriate bits at the appropriate time. Again, an 8 to 1 mux and an inverter does the job. Of course, the clock is 4x the actual data rate. In gates, I think an xor, and three, 2-input
    NANDs, will do the job. Might need an inverter, so four, 2-input NAND gates.


    what edge would you use?
    Edge? This data is already being clocked by the PLL. The data is captured when one of the four above patterns is detected and an appropriate clock
    enable is generated.
    ah, I wrongly assumed you'd some how skip the pll and use the data as clock

    You can. You have to use the logic output and watch for the enable to be asserted. However, because the logic is not race free, you need to design a circuit to reject glitches. But you have to have a clock to drive the shift register. If you use an
    arbitrary rate clock, it can be done, but the logic is a bit more. It's essentially a digital PLL.


    I would need to know more about the circuit receiving the data to give details. It's not often the receiving circuit is clocked by the data transmission clock, so the data and clock enable would need to cross a clock boundary most likely. I don't
    recall what the data is being used for. I think Larkin finally explained some portion of that, but rather than give it up front, it's buried in the thread somewhere.

    afaict it goes into a decimator, so the whole thing could run on the pll clock, or the much slower output could be synchronized

    Ok.

    --

    Rick C.

    +++ Get 1,000 miles of free Supercharging
    +++ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jjlarkin@highlandtechnology.com on Mon Aug 8 18:47:13 2022
    On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:

    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin >><jjlarkin@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net> >>>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>>><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >>>>>> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>>>> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>>>> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >>>>>> >> >> >
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit >>>>>> >> >> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse
    whenever the desired pattern is in the shift register, even if it >>>>happens to find the pattern between two correctly-framed instances of >>>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn

    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Meaning the outputs of stages 1 and 3, for a separation of two bits?


    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
    an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
    Any 0 sees a \d.

    XNOR will emit a One if the two inputs are the same, and Zero
    otherwise. So either matched Zeros or matched Ones will yield a One. .<https://en.wikipedia.org/wiki/XNOR_gate>

    I have been playing with it, and I'm not getting useful detection of
    the sent MDATA bits. Perhaps I'm doing something wrong?

    This approach does not yield only one output bit per 4-bit input
    symbol, instead getting large rafts of output bits, so it seems that
    we still need to find the framing somehow to achieve the 4:1 bitrate
    reduction.


    More generally, the basic topology of a correlation receiver is a
    tapped delay line feeding a pattern-matching function of some kind.

    So a shift register feeding a XNOR gate is in fact a kind of
    correlation receiver. Because it's implemented using purely digital
    logic, it will not have much tolerance of noise.

    However, in the proposed application, scattered decode errors probably
    have little effect on the low-passed analog signal being transmitted,
    which should be the case so long as the optical SNR is large.


    However, if the same thing is instead implemented using an analog integrate-and-dump scheme (or sampled equivalent), the tolerance of
    noise is dramatically increased, and can approach matched-filter
    optimum. Which is why it's done that way for Ethernet.

    There is also a complicated tradeoff between dispersion (various
    kinds) and attenuation with distance in the fiber. Basically, up to a
    point, one can overcome distortion by providing added optical power or
    more sensitive optical receivers. In Ethernet, transmit optical power
    is limited to ensure eye safety, so the action is largely in receiver
    design. (In telcomms, transmit power may be far larger.)




    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Mon Aug 8 16:40:46 2022
    On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin ><jjlarkin@highlandtechnology.com> wrote:

    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin >>><jjlarkin@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>>>><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>>>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin: >>>>>>> >> On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >>>>>>> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>>>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>>>>> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>>>>> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things. >>>>>>> >> >> >
    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit >>>>>>> >> >> times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>>>whenever the desired pattern is in the shift register, even if it >>>>>happens to find the pattern between two correctly-framed instances of >>>>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn

    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Meaning the outputs of stages 1 and 3, for a separation of two bits?


    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
    an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
    Any 0 sees a \d.

    XNOR will emit a One if the two inputs are the same, and Zero
    otherwise. So either matched Zeros or matched Ones will yield a One. >.<https://en.wikipedia.org/wiki/XNOR_gate>

    I have been playing with it, and I'm not getting useful detection of
    the sent MDATA bits. Perhaps I'm doing something wrong?

    This approach does not yield only one output bit per 4-bit input
    symbol, instead getting large rafts of output bits, so it seems that
    we still need to find the framing somehow to achieve the 4:1 bitrate >reduction.


    I intend to lowpass filter it. I don't need a bit rate reduction.

    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jasen Betts@21:1/5 to Ricky on Tue Aug 9 08:27:59 2022
    On 2022-08-06, Ricky <gnuarm.deletethisbit@gmail.com> wrote:
    On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    This sequence is also pathological for continuous one data. You end up with 10101010 with no way to distinguish the frame bits from the data.

    How would that matter? eventually it will resolve, and until then it
    is all ones anyway, you might be off by a count of one, but coming
    into the signal mid stream you are already starting from a bad position,
    and this hasn't made it any worse than it would be if you could find
    the frame start immediately. So just guess, if it turns out you were
    wrong there's only one other choice.

    This is raw delta-sigma data, so all bits are least signifigant, and
    if you receive, missed, extra, or corrupted single bits it prpbably
    won't have noticeable effect.

    There is nothing magical about the pattern 1 0 d \d.

    Yeah, for example FM coding gets you the same features in half as many timeslots.

    --
    Jasen.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to Jasen Betts on Tue Aug 9 05:57:22 2022
    On Tuesday, August 9, 2022 at 4:30:56 AM UTC-4, Jasen Betts wrote:
    On 2022-08-06, Ricky <gnuarm.del...@gmail.com> wrote:
    On Thursday, August 4, 2022 at 1:00:18 PM UTC-4, John Larkin wrote:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    This sequence is also pathological for continuous one data. You end up with 10101010 with no way to distinguish the frame bits from the data.

    How would that matter? eventually it will resolve, and until then it
    is all ones anyway, you might be off by a count of one, but coming
    into the signal mid stream you are already starting from a bad position,
    and this hasn't made it any worse than it would be if you could find
    the frame start immediately. So just guess, if it turns out you were
    wrong there's only one other choice.

    This is raw delta-sigma data, so all bits are least signifigant, and
    if you receive, missed, extra, or corrupted single bits it prpbably
    won't have noticeable effect.

    There is nothing magical about the pattern 1 0 d \d.

    Yeah, for example FM coding gets you the same features in half as many timeslots.



    On Friday, August 5, 2022 at 4:20:58 PM UTC-4, John Larkin wrote:
    On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:


    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    which means that a simple running decoder can mis-frame
    the clumps.

    I'm not the one defining the problem. Clearly, framing is important or Larkin would not have brought up the concern. He seems to shoot down solutions with a wide bore shotgun, the sort of shot that would bring down his own solution, if he simply
    looked at it through the same sights.

    Either mis-alignment will or will not matter. Hard to have it both ways.

    --

    Rick C.

    ---- Get 1,000 miles of free Supercharging
    ---- Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jjlarkin@highlandtechnology.com on Wed Aug 10 14:19:46 2022
    On Mon, 08 Aug 2022 16:40:46 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:

    On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin >><jjlarkin@highlandtechnology.com> wrote:

    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net> >>>wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin >>>><jjlarkin@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>>>>><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin:
    On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin: >>>>>>>> >> On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>> >> <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>>>>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead >>>>>>>> >> >> >
    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel. >>>>>>>> >> >> >"Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate.

    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>>>>whenever the desired pattern is in the shift register, even if it >>>>>>happens to find the pattern between two correctly-framed instances of >>>>>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn

    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Meaning the outputs of stages 1 and 3, for a separation of two bits?


    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get
    an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d.
    Any 0 sees a \d.

    XNOR will emit a One if the two inputs are the same, and Zero
    otherwise. So either matched Zeros or matched Ones will yield a One. >>.<https://en.wikipedia.org/wiki/XNOR_gate>

    I have been playing with it, and I'm not getting useful detection of
    the sent MDATA bits. Perhaps I'm doing something wrong?

    This approach does not yield only one output bit per 4-bit input
    symbol, instead getting large rafts of output bits, so it seems that
    we still need to find the framing somehow to achieve the 4:1 bitrate >>reduction.


    I intend to lowpass filter it. I don't need a bit rate reduction.

    So I modeled that (in Mathematica), and it does appear to work,
    extrapolating to four times the pattern rate in the process, making
    low-pass filtering easier.

    Basically, this approach replicates the PWM waveform that MDATA is
    carrying, and has nothing to do with sigma-delta coding. (The 4:1
    bitrate extrapolation above is not quite the same thing as sigma-delta
    noise shaping, but a similar effect.)

    I also modeled 4-bit symbols, which don't work - no balanced 4-bit
    pattern is self-orthogonal (so the correlation receiver will
    automatically frame correctly), so I didn't look for mutually
    orthogonal pattern sets.

    I'm working on 6-bit patterns, where there are many more candidates.

    Such things do exist, and the question is only how large the patterns
    must be. Pattern lengths that are powers of two are usually most
    convenient.

    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Wed Aug 10 13:57:11 2022
    On Wed, 10 Aug 2022 14:19:46 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Mon, 08 Aug 2022 16:40:46 -0700, John Larkin ><jjlarkin@highlandtechnology.com> wrote:

    On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin >>><jjlarkin@highlandtechnology.com> wrote:

    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin >>>>><jjlarkin@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>>>>>><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin: >>>>>>>>> On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin: >>>>>>>>> >> On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>>>>>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts
    <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate. >>>>>>>>
    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>>>>>whenever the desired pattern is in the shift register, even if it >>>>>>>happens to find the pattern between two correctly-framed instances of >>>>>>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn

    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Meaning the outputs of stages 1 and 3, for a separation of two bits?


    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get >>>>an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d. >>>>Any 0 sees a \d.

    XNOR will emit a One if the two inputs are the same, and Zero
    otherwise. So either matched Zeros or matched Ones will yield a One. >>>.<https://en.wikipedia.org/wiki/XNOR_gate>

    I have been playing with it, and I'm not getting useful detection of
    the sent MDATA bits. Perhaps I'm doing something wrong?

    This approach does not yield only one output bit per 4-bit input
    symbol, instead getting large rafts of output bits, so it seems that
    we still need to find the framing somehow to achieve the 4:1 bitrate >>>reduction.


    I intend to lowpass filter it. I don't need a bit rate reduction.

    So I modeled that (in Mathematica), and it does appear to work,
    extrapolating to four times the pattern rate in the process, making
    low-pass filtering easier.

    It just replicates the original 20 Mbps data at the adc output.

    I'd resync it after the xor gate to get clean complementary CMOS logic
    levels and then use a differential filter and amp on the q and /q flop
    outputs. 50% duty cycle is zero volts out.



    Basically, this approach replicates the PWM waveform that MDATA is
    carrying, and has nothing to do with sigma-delta coding. (The 4:1
    bitrate extrapolation above is not quite the same thing as sigma-delta
    noise shaping, but a similar effect.)

    The d \d data from the ADC is delta-sigma. The encoding and
    transmission process doesn't care.


    I also modeled 4-bit symbols, which don't work - no balanced 4-bit
    pattern is self-orthogonal (so the correlation receiver will
    automatically frame correctly), so I didn't look for mutually
    orthogonal pattern sets.

    I'm working on 6-bit patterns, where there are many more candidates.

    Such things do exist, and the question is only how large the patterns
    must be. Pattern lengths that are powers of two are usually most
    convenient.

    Joe Gwinn
    --

    John Larkin Highland Technology, Inc trk

    The cork popped merrily, and Lord Peter rose to his feet.
    "Bunter", he said, "I give you a toast. The triumph of Instinct over Reason"

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Joe Gwinn@21:1/5 to jjlarkin@highlandtechnology.com on Fri Aug 12 16:48:54 2022
    On Wed, 10 Aug 2022 13:57:11 -0700, John Larkin <jjlarkin@highlandtechnology.com> wrote:

    On Wed, 10 Aug 2022 14:19:46 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Mon, 08 Aug 2022 16:40:46 -0700, John Larkin >><jjlarkin@highlandtechnology.com> wrote:

    On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net> >>>wrote:

    On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin >>>><jjlarkin@highlandtechnology.com> wrote:

    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin >>>>>><jjlarkin@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>>>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin: >>>>>>>>>> On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin: >>>>>>>>>> >> On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin: >>>>>>>>>> >> >> On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts >>>>>>>>>> >> >> <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate. >>>>>>>>>
    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>>>>>>whenever the desired pattern is in the shift register, even if it >>>>>>>>happens to find the pattern between two correctly-framed instances of >>>>>>>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn

    The decoder is a 3-bit shift register. Xnor the first and last bits.

    Meaning the outputs of stages 1 and 3, for a separation of two bits?


    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get >>>>>an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d. >>>>>Any 0 sees a \d.

    XNOR will emit a One if the two inputs are the same, and Zero >>>>otherwise. So either matched Zeros or matched Ones will yield a One. >>>>.<https://en.wikipedia.org/wiki/XNOR_gate>

    I have been playing with it, and I'm not getting useful detection of >>>>the sent MDATA bits. Perhaps I'm doing something wrong?

    This approach does not yield only one output bit per 4-bit input >>>>symbol, instead getting large rafts of output bits, so it seems that
    we still need to find the framing somehow to achieve the 4:1 bitrate >>>>reduction.


    I intend to lowpass filter it. I don't need a bit rate reduction.

    So I modeled that (in Mathematica), and it does appear to work, >>extrapolating to four times the pattern rate in the process, making >>low-pass filtering easier.

    It just replicates the original 20 Mbps data at the adc output.

    So you're clocking the SFP input faster than the MDATA rate, as for
    every MDAT bit there are four SFP bits, "1 0 d /d".

    I recall some discussion of this, but I've lost the thread on that in
    all the back-and-forth. I may not be alone. Probably time for a
    re-baseline of the discussion.


    I'd resync it after the xor gate to get clean complementary CMOS logic
    levels and then use a differential filter and amp on the q and /q flop >outputs. 50% duty cycle is zero volts out.

    OK.


    Basically, this approach replicates the PWM waveform that MDATA is >>carrying, and has nothing to do with sigma-delta coding. (The 4:1
    bitrate extrapolation above is not quite the same thing as sigma-delta >>noise shaping, but a similar effect.)

    The d \d data from the ADC is delta-sigma. The encoding and
    transmission process doesn't care.

    Well I see the problem now. One can describe this in either way, and
    the datasheet is a bit ambiguous on the subject.

    While it makes a whole lot of sense for the ADC (in the isolated side)
    to be delta-sigma, the MDAT interface (spanning the gap between
    isolated and grounded) can be seen as PWM or delta-sigma.

    From datasheet page 1:

    "The analog input is continuously sampled by a high performance analog modulator and converted to a ones density digital output stream with a
    data rate of up to 21 MHz."

    Note the talk of "ones density".


    From datasheet page 16:

    "The time average single-bit data from the modulator is directly
    proportional to the input signal. "

    Note the talk of averaged (versus integrated).

    "A differential signal of 0 mV ideally results in a stream of
    alternating 1s and 0s at the MDAT output pin. This output is high 50%
    of the time and low 50% of the time. A differential input of 250 mV
    produces a stream of 1s and 0s that are high 89.06% of the time. A
    differential input of -250 mV produces a stream of 1s and 0s that are
    high 10.94% of the time.

    A differential input of 320 mV ideally results in a stream of all 1s.
    A differential input of -320 mV ideally results in a stream of all 0s.
    The ADuM7703 absolute full-scale range is 320 mV, and the specified
    full-scale performance range is 250 mV, as shown in Table 13."

    The above describes quantized pulse duty-cycle or fixed-frame
    pulse-width modulation, as also shown in Figure 26 on the same page.
    This very much implies a PWM kind of waveform.


    From datasheet page 17, figure 27 (and associated text) make the
    input-voltage to output-average-voltage mapping more precise.


    From <https://en.wikipedia.org/wiki/Delta-sigma_modulation>:

    Motivation section: "Delta-sigma modulation converts an analog
    voltage signal into a pulse frequency, or pulse density, which can be understood as pulse-density modulation (PDM)."

    In the asynchronous case, the pulse positions are more or less random.

    In Figure 3, we see a sampled delta-sigma ADC output, with varying
    pulse density.

    The ADuM7703 may go farther, collecting all the One bits to one side
    and all the Zero bits to the other in a frame of short duration, so
    while it is still the bit density that varies, it now does so in the
    form of PWM modulation.

    It will take a scope trace or two to nail this down.


    Joe Gwinn

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Fri Aug 12 14:42:18 2022
    On Fri, 12 Aug 2022 16:48:54 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Wed, 10 Aug 2022 13:57:11 -0700, John Larkin ><jjlarkin@highlandtechnology.com> wrote:

    On Wed, 10 Aug 2022 14:19:46 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:

    On Mon, 08 Aug 2022 16:40:46 -0700, John Larkin >>><jjlarkin@highlandtechnology.com> wrote:

    On Mon, 08 Aug 2022 18:47:13 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>wrote:

    On Sun, 07 Aug 2022 09:52:59 -0700, John Larkin >>>>><jjlarkin@highlandtechnology.com> wrote:

    On Sun, 07 Aug 2022 12:17:54 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>>wrote:

    On Sat, 06 Aug 2022 17:08:55 -0700, John Larkin >>>>>>><jjlarkin@highlandtechnology.com> wrote:

    On Sat, 06 Aug 2022 14:19:10 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>>>>>wrote:

    On Sat, 6 Aug 2022 02:26:16 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>>><langwadt@fonz.dk> wrote:

    lrdag den 6. august 2022 kl. 02.09.50 UTC+2 skrev John Larkin: >>>>>>>>>>> On Fri, 5 Aug 2022 13:41:31 -0700 (PDT), Lasse Langwadt Christensen >>>>>>>>>>> <lang...@fonz.dk> wrote:

    fredag den 5. august 2022 kl. 22.20.58 UTC+2 skrev John Larkin: >>>>>>>>>>> >> On Fri, 5 Aug 2022 10:53:34 -0700 (PDT), Lasse Langwadt Christensen
    <lang...@fonz.dk> wrote:

    torsdag den 4. august 2022 kl. 19.00.18 UTC+2 skrev John Larkin:
    On Thu, 4 Aug 2022 06:21:33 -0000 (UTC), Jasen Betts >>>>>>>>>>> >> >> <use...@revmaps.no-ip.org> wrote:

    On 2022-08-03, jla...@highlandsniptechnology.com <jla...@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits?

    no, this is why internet standards use the term "Octet" instead

    What can I call a 6-bit byte? A clump?

    sixpence? Nintendo called 5 bits of their 10 bit word a nickel.
    "Sextet" would work also.

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    looks like manchester encoded one bit PWM
    Manchester is ambiguous. A string of 0s looks just like a string of
    1s.

    One of my guys, on his ferry ride, figured out how to add two bit
    times

    1 0 d \d

    to get a DC balanced form that is easy to generate and decode. It's
    terrifyingly clever.

    move the bits around and it is FSK; F and 2F

    1100
    1010


    Cute. But pattern 1010 1010

    has an embedded 1010

    isn't that what you get with 1 0 d \d and d = 1 ?
    The decoder is a 3-bit shift register and a 2-input xnor gate. >>>>>>>>>>
    and how does that help? you still need to use 1010

    Will that even work? A correlation receiver with emit a pulse >>>>>>>>>whenever the desired pattern is in the shift register, even if it >>>>>>>>>happens to find the pattern between two correctly-framed instances of >>>>>>>>>the pattern.

    A 2-input xnor is not a correlation receiver.

    I guess I'm not visualizing the specific circuit used.

    Joe Gwinn

    The decoder is a 3-bit shift register. Xnor the first and last bits. >>>>>
    Meaning the outputs of stages 1 and 3, for a separation of two bits?


    Or draw a long string of 4-bit frames, encoding various 1s and 0s. Get >>>>>>an xnor that spans 3 bits, and slide it along the pattern.

    Any D sees a 1 in either direction. Any \d sees a 0. Any 1 sees a d. >>>>>>Any 0 sees a \d.

    XNOR will emit a One if the two inputs are the same, and Zero >>>>>otherwise. So either matched Zeros or matched Ones will yield a One. >>>>>.<https://en.wikipedia.org/wiki/XNOR_gate>

    I have been playing with it, and I'm not getting useful detection of >>>>>the sent MDATA bits. Perhaps I'm doing something wrong?

    This approach does not yield only one output bit per 4-bit input >>>>>symbol, instead getting large rafts of output bits, so it seems that >>>>>we still need to find the framing somehow to achieve the 4:1 bitrate >>>>>reduction.


    I intend to lowpass filter it. I don't need a bit rate reduction.

    So I modeled that (in Mathematica), and it does appear to work, >>>extrapolating to four times the pattern rate in the process, making >>>low-pass filtering easier.

    It just replicates the original 20 Mbps data at the adc output.

    So you're clocking the SFP input faster than the MDATA rate, as for
    every MDAT bit there are four SFP bits, "1 0 d /d".

    I recall some discussion of this, but I've lost the thread on that in
    all the back-and-forth. I may not be alone. Probably time for a
    re-baseline of the discussion.


    I'd resync it after the xor gate to get clean complementary CMOS logic >>levels and then use a differential filter and amp on the q and /q flop >>outputs. 50% duty cycle is zero volts out.

    OK.


    Basically, this approach replicates the PWM waveform that MDATA is >>>carrying, and has nothing to do with sigma-delta coding. (The 4:1 >>>bitrate extrapolation above is not quite the same thing as sigma-delta >>>noise shaping, but a similar effect.)

    The d \d data from the ADC is delta-sigma. The encoding and
    transmission process doesn't care.

    Well I see the problem now. One can describe this in either way, and
    the datasheet is a bit ambiguous on the subject.

    While it makes a whole lot of sense for the ADC (in the isolated side)
    to be delta-sigma, the MDAT interface (spanning the gap between
    isolated and grounded) can be seen as PWM or delta-sigma.

    From datasheet page 1:

    "The analog input is continuously sampled by a high performance analog >modulator and converted to a ones density digital output stream with a
    data rate of up to 21 MHz."

    Note the talk of "ones density".


    That's American for "duty cycle." But random.


    From datasheet page 16:

    "The time average single-bit data from the modulator is directly
    proportional to the input signal. "

    Note the talk of averaged (versus integrated).

    We usually decimate the delta-sigma ADC data into an 18 or 20-bit
    integer in an FPGA. My guys like to use a sinc3 lowpass filter, which
    looks like it shouldn't work but it does.

    But I'm considering an analog-to-analog link, no FPGA, with data sent
    over fiber SFP.


    "A differential signal of 0 mV ideally results in a stream of
    alternating 1s and 0s at the MDAT output pin. This output is high 50%
    of the time and low 50% of the time. A differential input of 250 mV
    produces a stream of 1s and 0s that are high 89.06% of the time. A >differential input of -250 mV produces a stream of 1s and 0s that are
    high 10.94% of the time.

    A differential input of 320 mV ideally results in a stream of all 1s.
    A differential input of -320 mV ideally results in a stream of all 0s.
    The ADuM7703 absolute full-scale range is 320 mV, and the specified >full-scale performance range is 250 mV, as shown in Table 13."

    It's a great chip. The isolation lets the input hang across, say, a
    current shunt with some giant common-mode voltage.



    The above describes quantized pulse duty-cycle or fixed-frame
    pulse-width modulation, as also shown in Figure 26 on the same page.
    This very much implies a PWM kind of waveform.


    From datasheet page 17, figure 27 (and associated text) make the >input-voltage to output-average-voltage mapping more precise.


    From <https://en.wikipedia.org/wiki/Delta-sigma_modulation>:

    Motivation section: "Delta-sigma modulation converts an analog
    voltage signal into a pulse frequency, or pulse density, which can be >understood as pulse-density modulation (PDM)."

    In the asynchronous case, the pulse positions are more or less random.

    The genius of delta-sigma is that it randomizes the duty cycle and
    pushes the spectrum up. Unlike classic PWM, it's much easier to
    process and filter.


    In Figure 3, we see a sampled delta-sigma ADC output, with varying
    pulse density.

    The ADuM7703 may go farther, collecting all the One bits to one side
    and all the Zero bits to the other in a frame of short duration, so
    while it is still the bit density that varies, it now does so in the
    form of PWM modulation.

    It will take a scope trace or two to nail this down.


    Joe Gwinn

    I actually have an LT Spice model of a delta-sigma ADC, if anyone
    wants to play with it.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Les Cargill@21:1/5 to John Larkin on Fri Aug 12 20:15:19 2022
    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    You could send the bit and its 1's complement right after for less than
    half the cost.

    <snip>

    --
    Les Cargill

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Larkin@21:1/5 to All on Fri Aug 12 20:17:13 2022
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcargil99@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    You could send the bit and its 1's complement right after for less than
    half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sat Aug 13 05:17:07 2022
    lørdag den 13. august 2022 kl. 05.17.29 UTC+2 skrev John Larkin:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com>
    wrote:
    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    You could send the bit and its 1's complement right after for less than >half the cost.

    <snip>
    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.

    you can't, but since it is a DSM stream you'll have lot of transitions unless something is wrong
    so it could still work since 00 means the data changed from 1 to 0 and 11 means data changed from 0 to 1

    Version 4
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    WIRE -544 -448 -592 -448
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    WIRE 2080 160 2080 -304
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    WIRE 1840 320 1840 208
    WIRE 2096 320 2096 208
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    FLAG 80 384 0
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    FLAG 1840 400 0
    FLAG 1712 -32 0
    FLAG 400 -144 ADC_CLK
    FLAG -192 -256 ADC_Dp
    FLAG 2880 96 DATA_OUT
    FLAG 560 -256 MDATA
    SYMBOL voltage 80 288 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value SINE(.5 .5 80e6)
    SYMBOL bv -544 -464 R0
    WINDOW 3 52 61 Left 2
    SYMATTR Value V=RAND(time*1e8)
    SYMATTR InstName B1
    SYMBOL Digital\\dflop 240 -80 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A2
    SYMBOL Digital\\dflop -336 -304 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A3
    SYMBOL Digital\\dflop 944 112 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A4
    SYMBOL Digital\\dflop 1968 112 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A8
    SYMBOL Digital\\dflop 2208 112 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A9
    SYMBOL Digital\\dflop 2496 112 R0
    WINDOW 3 8 12 Left 2
    SYMATTR Value td=1n
    SYMATTR InstName A10
    SYMBOL voltage 1840 304 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V2
    SYMATTR Value SINE(.5 .5 80e6 200n 0)
    SYMBOL cap 1280 144 R90
    WINDOW 0 0 32 VBottom 2
    WINDOW 3 32 32 VTop 2
    SYMATTR InstName C1
    SYMATTR Value 10p
    SYMBOL voltage 1712 -128 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V3
    SYMATTR Value 0.5
    SYMBOL res 1632 64 R0
    SYMATTR InstName R2
    SYMATTR Value 1k
    SYMBOL Digital\\xor 704 112 R0
    SYMATTR InstName A1
    SYMBOL Digital\\and 2192 -336 R0
    SYMATTR InstName A5
    SYMBOL Digital\\and 2192 -176 R0
    SYMATTR InstName A6
    TEXT 1200 -504 Left 2 !.tran 1u
    TEXT -400 -472 Left 2 ;ADC sim
    TEXT 880 -440 Left 2 ;Transmitter
    TEXT 1480 -448 Left 2 ;Reciever
    TEXT 2288 -304 Left 2 ;11 = 0->1
    TEXT 2288 -152 Left 2 ;00= 1->0
    RECTANGLE Normal 1088 432 -64 -496 2
    RECTANGLE Normal -624 -496 -144 -144 2
    RECTANGLE Normal 3040 432 1440 -496 2

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Les Cargill@21:1/5 to Lasse Langwadt Christensen on Sat Aug 13 18:20:08 2022
    Lasse Langwadt Christensen wrote:
    lørdag den 13. august 2022 kl. 05.17.29 UTC+2 skrev John Larkin:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com>
    wrote:
    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep >>>> the SFP data balanced.

    You could send the bit and its 1's complement right after for less than
    half the cost.

    <snip>
    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.

    you can't, but since it is a DSM stream you'll have lot of transitions unless something is wrong
    so it could still work since 00 means the data changed from 1 to 0 and 11 means data changed from 0 to 1


    Bits are always paired as 01 or 10, meaning 0 and 1 respectively.


    <snip>

    --
    Les Cargill

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Les Cargill@21:1/5 to John Larkin on Sat Aug 13 18:18:30 2022
    John Larkin wrote:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcargil99@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    You could send the bit and its 1's complement right after for less than
    half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.



    You'd need a sync pattern for start of frame, 16 zeros followed by 16
    ones, say. Maybe 4 instead of 16.

    then just 10,01,01,10... an agreed number of times.

    Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

    Wild arse guess is 50 lines of C for the encoder and 50 more
    for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
    or two.

    PIC16 might be big enough. Should be close to bit times
    in latency.

    --
    Les Cargill

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 14 00:52:06 2022
    søndag den 14. august 2022 kl. 01.20.17 UTC+2 skrev Les Cargill:
    Lasse Langwadt Christensen wrote:
    lørdag den 13. august 2022 kl. 05.17.29 UTC+2 skrev John Larkin:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com>
    wrote:
    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net> >>>> wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep >>>> the SFP data balanced.

    You could send the bit and its 1's complement right after for less than >>> half the cost.

    <snip>
    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.

    you can't, but since it is a DSM stream you'll have lot of transitions unless something is wrong
    so it could still work since 00 means the data changed from 1 to 0 and 11 means data changed from 0 to 1

    Bits are always paired as 01 or 10, meaning 0 and 1 respectively.

    yes so every time there's a change in data you get a 00 or 11 in the stream

    eg data = 00101100 -> stream = 01.01:10:01:10.10:01.01

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 14 00:53:00 2022
    søndag den 14. august 2022 kl. 01.18.39 UTC+2 skrev Les Cargill:
    John Larkin wrote:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep >>> the SFP data balanced.

    You could send the bit and its 1's complement right after for less than >> half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.

    You'd need a sync pattern for start of frame, 16 zeros followed by 16
    ones, say. Maybe 4 instead of 16.

    then just 10,01,01,10... an agreed number of times.

    Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

    Wild arse guess is 50 lines of C for the encoder and 50 more
    for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
    or two.

    PIC16 might be big enough. Should be close to bit times
    in latency.

    with 20MHz data rate?

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Jasen Betts@21:1/5 to Joe Gwinn on Sun Aug 14 10:59:56 2022
    On 2022-08-12, Joe Gwinn <joegwinn@comcast.net> wrote:

    "The analog input is continuously sampled by a high performance analog modulator and converted to a ones density digital output stream with a
    data rate of up to 21 MHz."

    Note the talk of "ones density".


    as opposed to what?


    From datasheet page 16:

    "The time average single-bit data from the modulator is directly
    proportional to the input signal. "

    Note the talk of averaged (versus integrated).

    This is merely the difference between the destination and the route.

    "A differential signal of 0 mV ideally results in a stream of
    alternating 1s and 0s at the MDAT output pin. This output is high 50%
    of the time and low 50% of the time. A differential input of 250 mV
    produces a stream of 1s and 0s that are high 89.06% of the time. A differential input of -250 mV produces a stream of 1s and 0s that are
    high 10.94% of the time.

    Note above the 101010 pattern for 0V is characteristic of delta-sigma,
    but that that doesn't match the picture in figure 26.

    A differential input of 320 mV ideally results in a stream of all 1s.
    A differential input of -320 mV ideally results in a stream of all 0s.
    The ADuM7703 absolute full-scale range is ±320 mV, and the specified full-scale performance range is ±250 mV, as shown in Table 13."

    The above describes quantized pulse duty-cycle or fixed-frame
    pulse-width modulation, as also shown in Figure 26 on the same page.
    This very much implies a PWM kind of waveform.

    Seems fairly ambiguous to me.

    Jasen.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From jlarkin@highlandsniptechnology.com@21:1/5 to All on Sun Aug 14 06:32:49 2022
    On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcargil99@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcargil99@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net>
    wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep >>>> the SFP data balanced.

    You could send the bit and its 1's complement right after for less than
    half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.



    You'd need a sync pattern for start of frame, 16 zeros followed by 16
    ones, say. Maybe 4 instead of 16.

    then just 10,01,01,10... an agreed number of times.

    Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

    Wild arse guess is 50 lines of C for the encoder and 50 more
    for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
    or two.

    PIC16 might be big enough. Should be close to bit times
    in latency.

    My premise was that I'd build both ends with no code, no c and no
    VHDL. Just small-scale cmos logic chips.

    And I want to ship 20 Mbps, kinda fast for 50 lines of c.

    I guess that biphase, 01 and 10 with detection of 11 as a bit framing
    error, could be done with a bit of discrete logic. A delta-sigma adc
    would provide lots of opportunities to test that.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Sun Aug 14 06:51:30 2022
    søndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev jla...@highlandsniptechnology.com:
    On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcar...@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net> >>>> wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep >>>> the SFP data balanced.

    You could send the bit and its 1's complement right after for less than >>> half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.



    You'd need a sync pattern for start of frame, 16 zeros followed by 16 >ones, say. Maybe 4 instead of 16.

    then just 10,01,01,10... an agreed number of times.

    Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

    Wild arse guess is 50 lines of C for the encoder and 50 more
    for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
    or two.

    PIC16 might be big enough. Should be close to bit times
    in latency.
    My premise was that I'd build both ends with no code, no c and no
    VHDL. Just small-scale cmos logic chips.

    And I want to ship 20 Mbps, kinda fast for 50 lines of c.

    I guess that biphase, 01 and 10 with detection of 11 as a bit framing
    error, could be done with a bit of discrete logic. A delta-sigma adc
    would provide lots of opportunities to test that.

    not need to mess with frames,
    just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

    I guess you didn't see the spice sim

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Les Cargill@21:1/5 to jlarkin@highlandsniptechnology.com on Sun Aug 14 14:05:32 2022
    jlarkin@highlandsniptechnology.com wrote:
    On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcargil99@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcargil99@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joegwinn@comcast.net> >>>>> wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep >>>>> the SFP data balanced.

    You could send the bit and its 1's complement right after for less than >>>> half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.



    You'd need a sync pattern for start of frame, 16 zeros followed by 16
    ones, say. Maybe 4 instead of 16.

    then just 10,01,01,10... an agreed number of times.

    Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

    Wild arse guess is 50 lines of C for the encoder and 50 more
    for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
    or two.

    PIC16 might be big enough. Should be close to bit times
    in latency.

    My premise was that I'd build both ends with no code, no c and no
    VHDL. Just small-scale cmos logic chips.

    And I want to ship 20 Mbps, kinda fast for 50 lines of c.


    Fair enough. I was estimating complexity really. I don't recall an
    expected data rate being called out although "optical" would imply
    something like 20 Mpbs.

    I guess that biphase, 01 and 10 with detection of 11 as a bit framing
    error, could be done with a bit of discrete logic. A delta-sigma adc
    would provide lots of opportunities to test that.




    --
    Les Cargill

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From John Walliker@21:1/5 to Les Cargill on Sun Aug 14 15:23:01 2022
    On Sunday, 14 August 2022 at 20:05:39 UTC+1, Les Cargill wrote:

    That's the reason to send 4 bits for every actual payload bit, to keep >>>>> the SFP data balanced.
    ...
    Fair enough. I was estimating complexity really. I don't recall an
    expected data rate being called out although "optical" would imply
    something like 20 Mpbs.

    Cheap SFPs will happily run at 10Gbit/s.

    John

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Lasse Langwadt Christensen@21:1/5 to All on Mon Aug 15 08:08:29 2022
    søndag den 14. august 2022 kl. 15.51.33 UTC+2 skrev Lasse Langwadt Christensen:
    søndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev jla...@highlandsniptechnology.com:
    On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcar...@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net> >>>> wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    You could send the bit and its 1's complement right after for less than
    half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream >> of 0s? They look alike.



    You'd need a sync pattern for start of frame, 16 zeros followed by 16 >ones, say. Maybe 4 instead of 16.

    then just 10,01,01,10... an agreed number of times.

    Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

    Wild arse guess is 50 lines of C for the encoder and 50 more
    for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA >or two.

    PIC16 might be big enough. Should be close to bit times
    in latency.
    My premise was that I'd build both ends with no code, no c and no
    VHDL. Just small-scale cmos logic chips.

    And I want to ship 20 Mbps, kinda fast for 50 lines of c.

    I guess that biphase, 01 and 10 with detection of 11 as a bit framing error, could be done with a bit of discrete logic. A delta-sigma adc
    would provide lots of opportunities to test that.
    not need to mess with frames,
    just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

    I guess you didn't see the spice sim

    you could even skip all the PLL stuff, just set a FF on the falling edge after >1.5period high, clear FF on rising edge after >~1.5period low

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From jlarkin@highlandsniptechnology.com@21:1/5 to langwadt@fonz.dk on Mon Aug 15 09:07:57 2022
    On Mon, 15 Aug 2022 08:08:29 -0700 (PDT), Lasse Langwadt Christensen <langwadt@fonz.dk> wrote:

    sndag den 14. august 2022 kl. 15.51.33 UTC+2 skrev Lasse Langwadt Christensen:
    sndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev jla...@highlandsniptechnology.com:
    On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcar...@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net> >> > >>>> wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    You could send the bit and its 1's complement right after for less than
    half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream >> > >> of 0s? They look alike.



    You'd need a sync pattern for start of frame, 16 zeros followed by 16
    ones, say. Maybe 4 instead of 16.

    then just 10,01,01,10... an agreed number of times.

    Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

    Wild arse guess is 50 lines of C for the encoder and 50 more
    for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA
    or two.

    PIC16 might be big enough. Should be close to bit times
    in latency.
    My premise was that I'd build both ends with no code, no c and no
    VHDL. Just small-scale cmos logic chips.

    And I want to ship 20 Mbps, kinda fast for 50 lines of c.

    I guess that biphase, 01 and 10 with detection of 11 as a bit framing
    error, could be done with a bit of discrete logic. A delta-sigma adc
    would provide lots of opportunities to test that.
    not need to mess with frames,
    just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

    I guess you didn't see the spice sim

    you could even skip all the PLL stuff, just set a FF on the falling edge after >1.5period high, clear FF on rising edge after >~1.5period low

    Biphase always has a transition mid-bit. So a transition detector and
    a 0.75t non-retriggerable one-shot soon syncs up.

    I knew that decades ago and sort of forgot.

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From Ricky@21:1/5 to jla...@highlandsniptechnology.com on Mon Aug 15 10:09:19 2022
    On Monday, August 15, 2022 at 12:08:05 PM UTC-4, jla...@highlandsniptechnology.com wrote:
    On Mon, 15 Aug 2022 08:08:29 -0700 (PDT), Lasse Langwadt Christensen <lang...@fonz.dk> wrote:

    sųndag den 14. august 2022 kl. 15.51.33 UTC+2 skrev Lasse Langwadt Christensen:
    sųndag den 14. august 2022 kl. 15.33.00 UTC+2 skrev jla...@highlandsniptechnology.com:
    On Sat, 13 Aug 2022 18:18:30 -0500, Les Cargill <lcar...@gmail.com>
    wrote:

    John Larkin wrote:
    On Fri, 12 Aug 2022 20:15:19 -0500, Les Cargill <lcar...@gmail.com> >> > >> wrote:

    John Larkin wrote:
    On Fri, 05 Aug 2022 11:29:50 -0400, Joe Gwinn <joeg...@comcast.net>
    wrote:
    <snip>
    That's the reason to send 4 bits for every actual payload bit, to keep
    the SFP data balanced.

    You could send the bit and its 1's complement right after for less than
    half the cost.

    <snip>

    How would the receiver distinguish between a stream of 1s and a stream
    of 0s? They look alike.



    You'd need a sync pattern for start of frame, 16 zeros followed by 16 >> > >ones, say. Maybe 4 instead of 16.

    then just 10,01,01,10... an agreed number of times.

    Might ECC it; Hamming, others. It's optical so maybe a YAGNI.

    Wild arse guess is 50 lines of C for the encoder and 50 more
    for the decoder ( sans ECC ) . Maybe a smidge more for operating a DMA >> > >or two.

    PIC16 might be big enough. Should be close to bit times
    in latency.
    My premise was that I'd build both ends with no code, no c and no
    VHDL. Just small-scale cmos logic chips.

    And I want to ship 20 Mbps, kinda fast for 50 lines of c.

    I guess that biphase, 01 and 10 with detection of 11 as a bit framing >> > error, could be done with a bit of discrete logic. A delta-sigma adc
    would provide lots of opportunities to test that.
    not need to mess with frames,
    just one flop, if you see 11 set the output, if you see 00 clear the output else leave it as is

    I guess you didn't see the spice sim

    you could even skip all the PLL stuff, just set a FF on the falling edge after >1.5period high, clear FF on rising edge after >~1.5period low
    Biphase always has a transition mid-bit. So a transition detector and
    a 0.75t non-retriggerable one-shot soon syncs up.

    Only if you have non-constant data. You already rejected several suggestions based on the fact that they required non-constant data to sync up.

    Sometimes I wonder if you know what you want.

    --

    Rick C.

    ---+ Get 1,000 miles of free Supercharging
    ---+ Tesla referral code - https://ts.la/richard11209

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)
  • From none) (albert@21:1/5 to jlarkin@highlandsniptechnology.com on Thu Sep 1 14:42:58 2022
    In article <646leh1gtvttuk4j1e7169atubleetvbct@4ax.com>,
    <jlarkin@highlandsniptechnology.com> wrote:
    Is a byte always 8 bits? What can I call a 6-bit byte? A clump?

    I want to send data over an SFP optical link, in 6-bit things.

    0 1 1 0 d \d repeated, roughly 100 Mbits/sec

    is DC balanced, which SFP likes.


    Last time I looked I can buy 8-bit bytes by the Giga.
    Never encountered a company that sold 6-bit bytes.

    Groetjes Albert
    --
    "in our communism country Viet Nam, people are forced to be
    alive and in the western country like US, people are free to
    die from Covid 19 lol" duc ha
    albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)