• MUN5333DW1T1G surge current

    From Piotr Wyderski@21:1/5 to All on Mon Jun 20 18:05:23 2022
    Hi,

    I need an array of high-side switches, not more than 50mA per channel.
    The MUN5333DW1T1G would be handy. Unfortunately, the datasheet specifies
    100mA max. continuous I_C only and I can't see anything about its surge handling capabilities. What should I assume for an 8/20us ESD pulse?
    Does 1A looks OK?

    Best regards, Piotr

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  • From jlarkin@highlandsniptechnology.com@21:1/5 to bombald@protonmail.com on Mon Jun 20 09:24:13 2022
    On Mon, 20 Jun 2022 18:05:23 +0200, Piotr Wyderski
    <bombald@protonmail.com> wrote:

    Hi,

    I need an array of high-side switches, not more than 50mA per channel.
    The MUN5333DW1T1G would be handy. Unfortunately, the datasheet specifies >100mA max. continuous I_C only and I can't see anything about its surge >handling capabilities. What should I assume for an 8/20us ESD pulse?
    Does 1A looks OK?

    Best regards, Piotr

    Why use NPNs as high-side switches?

    Single transistors seldom include ESD protection.

    What's the application?


    --

    Anybody can count to one.

    - Robert Widlar

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  • From Piotr Wyderski@21:1/5 to jlarkin@highlandsniptechnology.com on Mon Jun 20 19:39:43 2022
    jlarkin@highlandsniptechnology.com wrote:

    Why use NPNs as high-side switches?

    The high-side switch is the PNP half. The NPN one is a level translator
    from the 2.5V FPGA enable.

    Single transistors seldom include ESD protection.

    There will be a 600W 14V TVS, with 29V max clamp voltage during the
    surge. The question is what should be the value of the resistor between
    the TVS and the high-side collector.

    What's the application?

    A digitizer for an array of mechanical switches. The 20-50mA is the
    wetting current, one switch will be tested at a time in a round-robin
    fashion to limit the supply current.

    Best regards, Piotr

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  • From John Larkin@21:1/5 to bombald@protonmail.com on Mon Jun 20 11:41:31 2022
    On Mon, 20 Jun 2022 19:39:43 +0200, Piotr Wyderski
    <bombald@protonmail.com> wrote:

    jlarkin@highlandsniptechnology.com wrote:

    Why use NPNs as high-side switches?

    The high-side switch is the PNP half. The NPN one is a level translator
    from the 2.5V FPGA enable.

    Single transistors seldom include ESD protection.

    There will be a 600W 14V TVS, with 29V max clamp voltage during the
    surge. The question is what should be the value of the resistor between
    the TVS and the high-side collector.


    Zero?



    What's the application?

    A digitizer for an array of mechanical switches. The 20-50mA is the
    wetting current, one switch will be tested at a time in a round-robin
    fashion to limit the supply current.

    Best regards, Piotr

    We like TPIC6595 whan we need a lot of current-sinking drivers from an
    FPGA. It's very rugged, controlled avalanche. You'd still need the
    PNPs.

    There was a cool octal pull-up driver, UCN5815A, but it's unobtanium
    now.

    --

    If a man will begin with certainties, he shall end with doubts,
    but if he will be content to begin with doubts he shall end in certainties. Francis Bacon

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  • From Martin Rid@21:1/5 to Piotr Wyderski on Mon Jun 20 15:32:56 2022
    Piotr Wyderski <bombald@protonmail.com> Wrote in message:r
    Hi,I need an array of high-side switches, not more than 50mA per channel. The MUN5333DW1T1G would be handy. Unfortunately, the datasheet specifies 100mA max. continuous I_C only and I can't see anything about its surge handling capabilities. What
    should I assume for an 8/20us ESD pulse? Does 1A looks OK? Best regards, Piotr

    Have a look at Micrel eg microchip. The have some dual tsop 's

    Cheers
    --


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  • From Piotr Wyderski@21:1/5 to John Larkin on Mon Jun 20 21:51:18 2022
    John Larkin wrote:

    There will be a 600W 14V TVS, with 29V max clamp voltage during the
    surge. The question is what should be the value of the resistor between
    the TVS and the high-side collector.


    Zero?

    When the surge is negative with respect to the collector, the situation
    is under control: it will be clamped to 29V and the transistor can
    withstand 50V. If the surge is positive, the PNP will be driven into the reverse active region with sort of 5V V_EBO. I can't find the TVS
    forward voltage at the I_MAX and so I assumed it would be prudent to
    limit the I_C a bit. Indeed, zero was my initial approach, but then some afterthoughts started coming.

    We like TPIC6595 whan we need a lot of current-sinking drivers from an
    FPGA. It's very rugged, controlled avalanche.

    I love the part. FYI, you can make 8 flybacks using the TPIC6595 by
    modulating the OE. Works OK up to a MHz: I gave up here, maybe it still
    can go faster. The snubber is built-in, you just connect the transformer
    and call it a day.

    But since a PNP per channel is one part to add to the board and the
    pre-biased dual is one part as well, just by connecting pins 5 and 6 you
    end up with a logic-level-driven high-side switch, eliminating the HV
    shift register from the BOM. And the board must be small, so it matters.

    Best regards, Piotr

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