https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
On Mon, 9 May 2022 17:06:08 -0400, Phil Hobbs ><pcdhSpamMeSenseless@electrooptical.net> wrote:
John Larkin wrote:
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
Ish. Alternating traces going in opposite directions is a big help, >>because the coupling doesn't build up that way.
It depends on how far they go together, how fast the signals are, and
how vulnerable the receiving trace is.
Cheers
Phil Hobbs
This board has a MicroZed that runs a lot of fast signals to 8 plugin
boards. The pinouts were selected (not by me) to minimize crossovers
and vias without much thought to signal speeds or directions. The easy
fix is to just spread them out.
The traces are, quite by accident, the correct 75 ohms, 8 mil wide >microstrips.
John Larkin wrote:
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
Ish. Alternating traces going in opposite directions is a big help,
because the coupling doesn't build up that way.
It depends on how far they go together, how fast the signals are, and
how vulnerable the receiving trace is.
Cheers
Phil Hobbs
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
On Mon, 9 May 2022 17:06:08 -0400, Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
Ish. Alternating traces going in opposite directions is a big help,
because the coupling doesn't build up that way.
This board has a MicroZed that runs a lot of fast signals to 8 plugin
boards. The pinouts were selected (not by me) to minimize crossovers
and vias without much thought to signal speeds or directions. The easy
fix is to just spread them out.
On Monday, May 9, 2022 at 5:18:14 PM UTC-7, John Larkin wrote:But not if there is a ground plane underneath as the loop is then the area
On Mon, 9 May 2022 17:06:08 -0400, Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
That's not a great fix for ground-loop (inductive) problems. Area insideIsh. Alternating traces going in opposite directions is a big help, >because the coupling doesn't build up that way.This board has a MicroZed that runs a lot of fast signals to 8 plugin boards. The pinouts were selected (not by me) to minimize crossovers
and vias without much thought to signal speeds or directions. The easy
fix is to just spread them out.
the loop is an interfering-signal coupler, so 'spread' is a square-law interference increaser.
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
On Monday, May 9, 2022 at 5:18:14 PM UTC-7, John Larkin wrote:
On Mon, 9 May 2022 17:06:08 -0400, Phil Hobbs
<pcdhSpamM...@electrooptical.net> wrote:
Ish. Alternating traces going in opposite directions is a big help,
because the coupling doesn't build up that way.
This board has a MicroZed that runs a lot of fast signals to 8 plugin
boards. The pinouts were selected (not by me) to minimize crossovers
and vias without much thought to signal speeds or directions. The easy
fix is to just spread them out.
That's not a great fix for ground-loop (inductive) problems. Area inside >the loop is an interfering-signal coupler, so 'spread' is a square-law >interference increaser.
On 5/9/2022 23:51, John Larkin wrote:
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
For digital (where density is really needed) within 100-200 MHz
we have been doing 4 mil trace 4 mil spacing for ages now.
That on the visible (top and bottom layers), referenced to GND
planes beneath each.
No issue whatsoever. Well, actually I had one, an I2C line was
passing too close (probably not 4 mil, may be a whole mm) to a
flyback switch (IRF540-ish) for the HV which was doing nice
100V excursions and at times managed to upset the i2c.
Pulling the latter up with 1k on each line fixed it (was 2k IIRC).
On Tue, 10 May 2022 17:49:20 +0300, Dimiter_Popoff <dp@tgi-sci.com>
wrote:
On 5/9/2022 23:51, John Larkin wrote:
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
For digital (where density is really needed) within 100-200 MHz
we have been doing 4 mil trace 4 mil spacing for ages now.
That on the visible (top and bottom layers), referenced to GND
planes beneath each.
No issue whatsoever. Well, actually I had one, an I2C line was
passing too close (probably not 4 mil, may be a whole mm) to a
flyback switch (IRF540-ish) for the HV which was doing nice
100V excursions and at times managed to upset the i2c.
Pulling the latter up with 1k on each line fixed it (was 2k IIRC).
Some of our traces will be fast 8b10b data streams. At powerup time we "train" the receivers to adapt to the actual data timing. Crosstalk
from other signals can wobble the bit edges and potentially make data
errors.
On Tuesday, May 10, 2022 at 9:52:52 AM UTC-7, John Larkin wrote:
On Tue, 10 May 2022 00:22:16 -0700 (PDT), whit3rd <whi...@gmail.com>
wrote:
On Monday, May 9, 2022 at 5:18:14 PM UTC-7, John Larkin wrote:
... to minimize crossovers
and vias without much thought to signal speeds or directions. The easy >>>> fix is to just spread them out.
That's not a great fix for ground-loop (inductive) problems. Area inside >>> the loop is an interfering-signal coupler, so 'spread' is a square-law
interference increaser.
But spreading the traces is a great fix for crosstalk. Try it.
How to apply that fix, though, to a cat5 cable's four pairs?
In one instance, I found a DC/DC converter that needed its input
power through a common-mode bead, because it crosstalked to components a
foot and three circuit boards away. Freeze mist on the converter
changed the frequency of the interference, after other inspections
didn't find the problem.
On Tue, 10 May 2022 00:22:16 -0700 (PDT), whit3rd <whi...@gmail.com>
wrote:
On Monday, May 9, 2022 at 5:18:14 PM UTC-7, John Larkin wrote:
... to minimize crossovers
and vias without much thought to signal speeds or directions. The easy
fix is to just spread them out.
That's not a great fix for ground-loop (inductive) problems. Area inside >the loop is an interfering-signal coupler, so 'spread' is a square-law >interference increaser.
But spreading the traces is a great fix for crosstalk. Try it.
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
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Subject: Re: crosstalk
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Xref: reader02.eternal-september.org sci.electronics.design:668762
On Tuesday, May 10, 2022 at 6:52:05 AM UTC+10, John Larkin wrote:
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
A ground strip between individual signal-carrying traces provides extra isolation between them. If John Larkin had read enough to become knowledgeable about PC traces. he would have seen that mentioned.
--
Bill Sloman, Sydney
The troll doesn't even know how to format a USENET post...
The reason Bozo cannot figure out how to get Google to keep from
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From: Edward Hernandez <dtgamer99@gmail.com>
Subject: Re: crosstalk
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The John Doe troll stated the following in message-id <sdhn7c$pkp$4@dont-email.me>:
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And the John Doe troll stated the following in message-id <sg3kr7$qt5$1@dont-email.me>:
The reason Bozo cannot figure out how to get Google to keep from
breaking its lines in inappropriate places is because Bozo is
CLUELESS...
And yet, the clueless John Doe troll has continued to post incorrectly formatted USENET articles that are devoid of content (latest example on
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Further, Troll Doe stated the following in message-id <svsh05$lbh$5@dont-email.me> posted Fri, 4 Mar 2022 08:01:09 -0000
(UTC):
Compared to other regulars, Bozo contributes practically nothing
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Yet, since Wed, 5 Jan 2022 04:10:38 -0000 (UTC) Troll Doe's post ratio
to USENET (**) has been 60.5% of its posts contributing "nothing except insults" to USENET.
** Since Wed, 5 Jan 2022 04:10:38 -0000 (UTC) Troll Doe has posted at
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This posting is a public service announcement for any google groups
readers who happen by to point out that the John Doe troll does not even follow the rules it uses to troll other posters.
Fr7RG8qvqnxH
The troll doesn't even know how to format a USENET post...
The reason Bozo cannot figure out how to get Google to keep from
breaking its lines in inappropriate places is because Bozo is
CLUELESS...
Compared to other regulars, Bozo contributes practically nothing
except insults to this group.
Anthony William Sloman <bill....@ieee.org> wrote:
On Tuesday, May 10, 2022 at 6:52:05 AM UTC+10, John Larkin wrote:
https://www.dropbox.com/s/zaf7w7t71jmc820/Xtalk.jpg?raw=1
PCB layout people like to pack traces in nice tight bundles, which
encourages crosstalk and impedance issues.
Some general advice might be to separate microstrip traces by 2x the
trace width or 2x the distance to the ground plane, whichever is
greater.
I just made that up. What are your rules?
A ground strip between individual signal-carrying traces provides extra isolation between them. If John Larkin had read enough to become knowledgeable about PC traces. he would have seen that mentioned.
An utterly loony Australian.
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