• does this make sense?

    From John Larkin@21:1/5 to All on Fri Mar 25 12:57:23 2022
    https://www.signalintegrityjournal.com/articles/2460-what-to-expect-in-a-multi-drop-bus


    --

    If a man will begin with certainties, he shall end with doubts,
    but if he will be content to begin with doubts he shall end in certainties. Francis Bacon

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  • From Jeroen Belleman@21:1/5 to John Larkin on Fri Mar 25 21:23:34 2022
    On 2022-03-25 20:57, John Larkin wrote:

    https://www.signalintegrityjournal.com/articles/2460-what-to-expect-in-a-multi-drop-bus



    Looks to me the authors are just bloviating. They didn't measure
    anything! Really, every chip along the bus is a 50 Ohm load? Nah.

    Jeroen Belleman

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  • From Jan Panteltje@21:1/5 to jlarkin@highland_atwork_technology. on Sat Mar 26 06:29:36 2022
    On a sunny day (Fri, 25 Mar 2022 12:57:23 -0700) it happened John Larkin <jlarkin@highland_atwork_technology.com> wrote in <3k7s3ht4jv42k9m2pat5pvuf8ibl77ek12@4ax.com>:


    https://www.signalintegrityjournal.com/articles/2460-what-to-expect-in-a-multi-drop-bus

    Dunno, had to think about that
    I can imagine the chips form a capacitor and the traces the inductor.
    That gives you a transmision line that *probably* would preserve the form of a fast pulse?

    Not sure that is what they are saying,
    Chip input capacitances have tolerances
    L L L
    -----------trace---- trace------------trace----
    [] fast pulse | | |
    Zin source === === termination
    | | Cin chip | |
    /// /// /// ///
    chip chip

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  • From Rickster@21:1/5 to Jan Panteltje on Sat Mar 26 09:19:45 2022
    On Saturday, March 26, 2022 at 2:31:05 AM UTC-4, Jan Panteltje wrote:
    On a sunny day (Fri, 25 Mar 2022 12:57:23 -0700) it happened John Larkin <jlarkin@highland_atwork_technology.com> wrote in <3k7s3ht4jv42k9m2p...@4ax.com>:


    https://www.signalintegrityjournal.com/articles/2460-what-to-expect-in-a-multi-drop-bus

    Dunno, had to think about that
    I can imagine the chips form a capacitor and the traces the inductor.
    That gives you a transmision line that *probably* would preserve the form of a fast pulse?

    Not sure that is what they are saying,
    Chip input capacitances have tolerances
    L L L
    -----------trace---- trace------------trace----
    [] fast pulse | | |
    Zin source === === termination
    | | Cin chip | |
    /// /// /// ///
    chip chip

    The chips are close together, but not close enough to be lumped capacitances. The guy is talking about memory chips with differential signals. The traces are almost certainly terminated as shown in the initial analysis, at each chip. The aggregate
    effect of the combined terminations is -15 dB of attenuation. At first I thought this had to be wrong, but then I realized the differential signalling can work properly with very small signals at the receivers. If the graphs are in volts, the
    differential signals seem to swing between 0.6V and 0.7V.

    The guy very clearly says he used an EM solver to start. That's because the signalling on a DRAM card is not impedance controlled because of the distributed input capacitances. The EM solver provides the S parameters and the "Keysight ADS" produces the
    eye diagrams. They mention the Keysight ADS multiple times, so obviously these are employees of Keysight and are promoting the product. That's why the step of analyzing the output of the EM field solver is not described in much details, not unlike, "
    and then magic happens".

    --

    Rick C.

    - Get 1,000 miles of free Supercharging
    - Tesla referral code - https://ts.la/richard11209

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  • From jlarkin@highlandsniptechnology.com@21:1/5 to pNaonStpealmtje@yahoo.com on Sat Mar 26 10:01:34 2022
    On Sat, 26 Mar 2022 06:29:36 GMT, Jan Panteltje
    <pNaonStpealmtje@yahoo.com> wrote:

    On a sunny day (Fri, 25 Mar 2022 12:57:23 -0700) it happened John Larkin ><jlarkin@highland_atwork_technology.com> wrote in ><3k7s3ht4jv42k9m2pat5pvuf8ibl77ek12@4ax.com>:

    https://www.signalintegrityjournal.com/articles/2460-what-to-expect-in-a-multi-drop-bus

    Dunno, had to think about that
    I can imagine the chips form a capacitor and the traces the inductor.
    That gives you a transmision line that *probably* would preserve the form of a fast pulse?

    Not sure that is what they are saying,
    Chip input capacitances have tolerances
    L L L
    -----------trace---- trace------------trace----
    [] fast pulse | | |
    Zin source === === termination
    | | Cin chip | |
    /// /// /// ///
    chip chip


    Sure, a txline can be analyzed as a string of LCs... lots of them [1].

    But 50 ohms DC at every dram chip?

    [1] the number increases as (Td/Tr) squared.



    --

    I yam what I yam - Popeye

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  • From Jan Panteltje@21:1/5 to jlarkin@highlandsniptechnology.com on Sat Mar 26 17:44:27 2022
    On a sunny day (Sat, 26 Mar 2022 10:01:34 -0700) it happened jlarkin@highlandsniptechnology.com wrote in <eihu3hdafbtt9simhhag0oico7ts0fqm1c@4ax.com>:

    On Sat, 26 Mar 2022 06:29:36 GMT, Jan Panteltje
    <pNaonStpealmtje@yahoo.com> wrote:

    On a sunny day (Fri, 25 Mar 2022 12:57:23 -0700) it happened John Larkin >><jlarkin@highland_atwork_technology.com> wrote in >><3k7s3ht4jv42k9m2pat5pvuf8ibl77ek12@4ax.com>:

    https://www.signalintegrityjournal.com/articles/2460-what-to-expect-in-a-multi-drop-bus

    Dunno, had to think about that
    I can imagine the chips form a capacitor and the traces the inductor.
    That gives you a transmission line that *probably* would preserve the form of a fast pulse?

    Not sure that is what they are saying,
    Chip input capacitances have tolerances
    L L L
    -----------trace---- trace------------trace----
    [] fast pulse | | |
    Zin source === === termination
    | | Cin chip | |
    /// /// /// ///
    chip chip


    Sure, a txline can be analyzed as a string of LCs... lots of them [1].

    But 50 ohms DC at every dram chip?

    The author writes he uses 50 Ohms just for ease of simulation or something.

    Reading it again I think they do not understand transmission lines :-)

    Way to complicated story.


    [1] the number increases as (Td/Tr) squared.

    Seems there are only 5 chips per driver...
    If pure capacitive what losses would there be?

    I could be wrong, but I only needed above few lines to explain that sort of setup.

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  • From John Larkin@21:1/5 to pNaonStpealmtje@yahoo.com on Sat Mar 26 11:25:15 2022
    On Sat, 26 Mar 2022 17:44:27 GMT, Jan Panteltje
    <pNaonStpealmtje@yahoo.com> wrote:

    On a sunny day (Sat, 26 Mar 2022 10:01:34 -0700) it happened >jlarkin@highlandsniptechnology.com wrote in ><eihu3hdafbtt9simhhag0oico7ts0fqm1c@4ax.com>:

    On Sat, 26 Mar 2022 06:29:36 GMT, Jan Panteltje
    <pNaonStpealmtje@yahoo.com> wrote:

    On a sunny day (Fri, 25 Mar 2022 12:57:23 -0700) it happened John Larkin >>><jlarkin@highland_atwork_technology.com> wrote in >>><3k7s3ht4jv42k9m2pat5pvuf8ibl77ek12@4ax.com>:

    https://www.signalintegrityjournal.com/articles/2460-what-to-expect-in-a-multi-drop-bus

    Dunno, had to think about that
    I can imagine the chips form a capacitor and the traces the inductor. >>>That gives you a transmission line that *probably* would preserve the form of a fast pulse?

    Not sure that is what they are saying,
    Chip input capacitances have tolerances
    L L L
    -----------trace---- trace------------trace----
    [] fast pulse | | |
    Zin source === === termination
    | | Cin chip | |
    /// /// /// ///
    chip chip


    Sure, a txline can be analyzed as a string of LCs... lots of them [1].

    But 50 ohms DC at every dram chip?

    The author writes he uses 50 Ohms just for ease of simulation or something.

    Reading it again I think they do not understand transmission lines :-)

    Way to complicated story.


    [1] the number increases as (Td/Tr) squared.

    Seems there are only 5 chips per driver...
    If pure capacitive what losses would there be?

    I could be wrong, but I only needed above few lines to explain that sort of setup.

    The fast DDR controllers run a calibration at startup to tweak out
    txline skews. They couldn't work otherwise. The DDR controller block
    in many FPGAs will do that for you.

    --

    If a man will begin with certainties, he shall end with doubts,
    but if he will be content to begin with doubts he shall end in certainties. Francis Bacon

    --- SoupGate-Win32 v1.05
    * Origin: fsxNet Usenet Gateway (21:1/5)