What's New in Synopsys Design Compiler 23?
Synopsys Design Compiler is a family of RTL synthesis products that enables designers to meet today's design challenges with concurrent optimization of timing, area, power and test. Synopsys Design Compiler 23 is the latest release that introduces new
features and enhancements to improve the quality of results (QoR) and productivity of the synthesis flow.

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Some of the key features of Synopsys Design Compiler 23 are:


2X faster runtime: Synopsys Design Compiler 23 leverages new optimization and intelligent multi-threading technologies to achieve better scalability up to eight CPUs, resulting in 2X faster runtime on quad-core platforms[^2^].
Improved QoR: Synopsys Design Compiler 23 delivers 12% lower total power and 10% smaller area through advanced optimizations and concurrent clock data (CCD) technology[^2^]. CCD technology enables gate-to-gate optimization for smaller area on new or
legacy designs while maintaining timing[^1^].
Cloud-ready: Synopsys Design Compiler 23 supports Synopsys Cloud Digital Instance, which provides pre-configured, simplified, automated synthesis flows on the cloud. This enables designers to access scalable compute resources on demand and accelerate
their design cycles[^2^].
RC estimation: Synopsys Design Compiler 23 introduces a new, highly accurate approach to RC estimation that provides timing and area prediction within 10% of the results seen post-layout[^1^]. This reduces costly iterations between synthesis and physical
implementation and enables a predictable flow.
5nm support: Synopsys Design Compiler 23 includes capabilities required for the process nodes 5nm and below, such as support for multi-voltage and multi-supply designs, advanced low-power techniques, and design-for-test features[^2^].

Synopsys Design Compiler 23 is the next-generation of RTL synthesis solution that offers fast, efficient, and cloud-ready optimization engines, as well as capabilities for next-generation process nodes. It is part of the comprehensive Synopsys RTL
synthesis solution, including Power Compiler™, DesignWare®, PrimeTime®, and DFTMAX™.

To learn more about Synopsys Design Compiler 23, visit https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/design-compiler-nxt.html.


What Customers Say About Synopsys Design Compiler 23?
Synopsys Design Compiler 23 has received positive feedback from customers who have used it on their design projects. Here are some of the testimonials from satisfied customers:


"We deployed and successfully used Design Compiler NXT on our latest 5nm tapeout project since it provided remarkable QoR improvement vs our previous synthesis solution." - JaeSin Shin, Principal Engineer, Samsung Foundry FDS Team[^2^]





"We are collaborating with Synopsys on the latest synthesis technologies in Design Compiler NXT and are looking forward to deploying them on our designs to help meet our ever-increasing pressure of time-to-market and higher QoR." - Tatsuji Kagatani, Vice
President, Renesas[^2^]



"Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler™ and PrimeTime® is a very good book for anyone who wants to learn more about the synthesis flow and tools. It covers both the theory and practice of synthesis with clear
explanations and examples. It also provides useful tips and tricks for optimizing the design performance and quality." - Amazon Customer[^3^]


These customer reviews show that Synopsys Design Compiler 23 is a trusted and reliable solution that delivers high-quality results and faster turnaround time for complex designs.

How to Get Started with Synopsys Design Compiler 23?
If you are interested in trying out Synopsys Design Compiler 23 for your next design project, you can request a free evaluation license from Synopsys. You can also access online resources such as datasheets, white papers, webinars, tutorials, and user
guides to learn more about the features and benefits of Synopsys Design Compiler 23.

To request a free evaluation license, visit https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra/evaluation.html.

To access online resources, visit https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra/resources.html.
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