• Libre-SOC OpenPOWER Project

    From lkcl@21:1/5 to All on Thu Apr 15 00:10:01 2021
    hi folks i thought it might be time to let everyone know of the plans for Libre-SOC.

    it is a new SoC based on OpenPOWER, with a roadmap to ramp up from single
    core 300mhz (as an entirely Libre ASIC, using opencores PHYs, coriolis2 for
    P&R and Chips4Makers Cell Libraries), to quad core within 2 years, then 8
    core and on to a 64 monster in 6 years time.

    we aim to extend and adapt the OpenPOWER ISA, given that there now exists a
    way to propose extensions. this will include full Cray-style
    Variable-length Vectorisation (VSX is 15 year old SIMD) and adding 3D and
    Video opcodes directly to OpenPOWER (*NOT* as a separate core), such that Vulkan Shader binaries may be JIT translated then directly executed
    natively.

    the kicker: after reading the v3.0B ISA manual and seeing that of its 1300 pages, fully 50% was dedicated to VSX, we simply flatly refused point blank
    to consider implementing it. this decision was reinforced after seeing
    that in binutils ppc port, a staggering 4500 assembly mnemonics are listed,
    90% of which are VSX.

    purely from a logistics perspective it would be insane to attempt to
    implement them (minimum 3 man-years). there are so many opcodes that the
    IBM POWER9 implementation actually has to have a 2 stage instruction
    decoder. just the integer opcodes (only 70 of them) requires 4,000 gates: imagine how many would be needed for VSX.

    what we intend to do instead is to add emulation in the linux kernel
    (extending lib/ppc/sstep.c) as a stopgap measure. however we will not be implementing the VSX instructions by hand: we will be auto-extracting the pseudocode from the v3.0B specification, and compiling it to c.

    this is already how our python-based OpenPOWER ISA emulator works: the pseudocode is converted to python. outputting c instead of python is a
    trivial next evolutionary step.

    that leaves a few years breathing space in which to define a new EABI which does not have VSX as mandatory. the mistake made a few years ago of adding VSX/VMX as mandatory, on the basis that it improved performance [for IBM POWER9] is a costly one. Microwatt, A2O, A2I and LibreSOC - none of these
    open cores have VSX or VMX, and consequently cannot run debian, fedora,
    arch, or in fact any modern mainline GNU/Linux distro at all.

    this is a massive project, for which we have grants from NLnet to help pay
    for it, if anyone would like to help.

    main site link: http://libre-soc.org

    l.

    hi folks i thought it might be time to let everyone know of the plans for Libre-SOC.<div><br></div><div>it is a new SoC based on OpenPOWER, with a roadmap to ramp up from single core 300mhz (as an entirely Libre ASIC, using opencores PHYs, coriolis2 for
    P&amp;R and Chips4Makers Cell Libraries), to quad core within 2 years, then 8 core and on to a 64 monster in 6 years time.</div><div><br></div><div>we aim to extend and adapt the OpenPOWER ISA, given that there now exists a way to propose extensions. 
    this will include full Cray-style Variable-length Vectorisation (VSX is 15 year old SIMD) and adding 3D and Video opcodes directly to OpenPOWER (*NOT* as a separate core), such that Vulkan Shader binaries may be JIT translated then directly executed
    natively.</div><div><br></div><div>the kicker: after reading the v3.0B ISA manual and seeing that of its 1300 pages, fully 50% was dedicated to VSX, we simply flatly refused point blank to consider implementing it.  this decision was reinforced after
    seeing that in binutils ppc port, a staggering 4500 assembly mnemonics are listed, 90% of which are VSX.</div><div><br></div><div>purely from a logistics perspective it would be insane to attempt to implement them (minimum 3 man-years).  there are so
    many opcodes that the IBM POWER9 implementation actually has to have a 2 stage instruction decoder.  just the integer opcodes (only 70 of them) requires 4,000 gates: imagine how many would be needed for VSX.</div><div><br></div><div>what we intend to do
    instead is to add emulation in the linux kernel (extending lib/ppc/sstep.c) as a stopgap measure.  however we will not be implementing the VSX instructions by hand: we will be auto-extracting the pseudocode from the v3.0B specification, and compiling it
    to c.</div><div><br></div><div>this is already how our python-based OpenPOWER ISA emulator works: the pseudocode is converted to python.  outputting c instead of python is a trivial next evolutionary step. </div><div><br></div><div>that leaves a few
    years breathing space in which to define a new EABI which does not have VSX as mandatory.  the mistake made a few years ago of adding VSX/VMX as mandatory, on the basis that it improved performance [for IBM POWER9] is a costly one.  Microwatt, A2O, A2I
    and LibreSOC - none of these open cores have VSX or VMX, and consequently cannot run debian, fedora, arch, or in fact any modern mainline GNU/Linux distro at all.</div><div><br></div><div>this is a massive project, for which we have grants from NLnet to
    help pay for it, if anyone would like to help.</div><div><br></div><div>main site link: <a href="http://libre-soc.org">http://libre-soc.org</a></div><div><br></div><div>l.</div><div><br></div>

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