On Monday, April 24, 2023 at 5:33:06 AM UTC+10, Antoine Vignau wrote:
Does pages 157+ of http://www.brutaldeluxe.fr/documentation/cortland/v3_01_CortlandHardwareReference.pdf help?
It doesn't. Thanks for the reference but it contains less information than the GS hardware reference although a couple of differences in the description. Also it indicates that the 14M signal is on memory the expansion connector when it is not (just phi2)
.
Anyway what I wanted to know is when in the phi2 cycle the 24 bit address is "known" to the exapnasion card. That would be when FRA9..0 in RAS and/or CAS have all of the low address bits. (the bank is on the data bus on the phi2 rising edge and A15..10
are valid at that time too). If I was doing it I would put A9..0 on FRA9..0 when they are valid (rising edge of phi2) and use them for the RAS address, and change to upper address/bank for CAS. That way the ROM address would not need to change giving
maximum timie for a slow ROM to get its data out. But its not my design, so...
So I had a look at the signals on a DSO. As I suspecdted the phi2 (2.8MHz) clock is asymmetrical. Its derived from the 14M clock, but 2.8 = 14 / 5, which doesn't divide nicely, so the phi2 clock is low for two 14M cycles (about 140ns) and high for three
14M cycles (about 210ns) unless it is extended (for MEGA2 access synchronised to its 1MHz clock) when it could be high for quite a few 14M clock cycles.
The FPI chip seems to watch both edges of the 14M clock. I noticed that there are repetitive refresh cycles going to the memory expansion connector. These occur about every 3.5us, one going to each bank successively then repeating (that is the CROW<x>
signals change for each refresh). The refresh is a CAS-before-RAS refresh cycle with the CAS being asserted for the entire high period of the phi2 clock (didn't see one happen while the phi2 cycle was being extended, though I didn't look for it) and the
RAS being asserted a little later.
unfortuantely the FPI doesn't assert the CCAS and CRAS signals when not accessing the memory expansion so I need to figure an easy way of reading thos signals without wrecking a RAM card that I want to keep. The iie technical reference has pseudo timing
diagrams and specifies the signals on hte multiplexed RAM address bus so I don't see why apple didn't make that available for the GS
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