I'm a bit late to the party but I did some interrupt free VBL detection for the //c some time ago for this demo:
https://github.com/cybernesto/F15-DGamma-Clone-A2/commit/488d53094e06c54e1308cb94b34e9d3d02022166#diff-102ef3ff63be5d1a6b40f88512a96100

Maybe it can be of some interest too.

Oliver Schmidt schrieb am Mittwoch, 17. Juni 2020 um 00:35:17 UTC+2:

Hi,

Putting all together I learned so far it seems that this all-in-one approach (no init code and no exit code) is preferable as it is least intrusive:

* It sets the CPU IRQ mask only during the actual wait.
* It restores the VBL interrupt mask to the previous state.

RDVBLBAR := $C019 ; >127 if not vertical blanking
RDVBLMSK := $C041 ; >127 if VBL interrupts enabled
DISVBL := $C05A ; Disable VBL interrupts
ENVBL := $C05B ; Enable VBL interrupts
IOUDISON := $C07E ; Disable IOU
IOUDISOFF := $C07F ; Enable IOU

sei
sta IOUDISOFF
lda RDVBLMSK
bit ENVBL
bit PTRIG ; Reset VBL interrupt flag
1: bit RDVBLBAR
bpl 1
asl
bcs 2 ; VBL interrupts were already enabled
bit DISVBL
2: sta IOUDISON ; IIc Tech Ref Man: The firmware normally leaves IOUDIS on. cli
rts

Regards,
Oliver

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That one has the same issue that I had originally - it can exit too soon if it's late to start checking.

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Oh, now I get it. You are right. I should have read the thread more carefully.

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