"Mike B." <
michael_bruestle@yahoo.com> writes:
You have to enable the interrupts twice. One time in the STATUS
registers (C012) and once in the INT_ENABLE.
Thanks, Mike! I just tried that -- still no luck.
Am I right in assuming that while the DMA interrupt enable bit will need
to be turned off and on again by the driver in order to enable it for
the next transaction, the input and output enables are automatically
cleared by reading or writing a byte, so they just need to be re-enabled
for the next round? This is what the manual seems to say, but I haven't
found any text that's really clear on these points.
Right now, following the "belt and suspenders" plan, this is what I do
in the interrupt handler (plus another, similar, block for the receiving
part, of course):
if (wlink_busy && (wbuf_read_offset != wbuf_write_offset)) {
sys_inb(B004_OSR, &b);
if (b & B004_READY) {
sys_outb(B004_OSR, B004_INT_DIS);
b008_intmask &= ~B008_OUTINT_ENA;
sys_outb(B008_INT, b008_intmask);
sys_outb(B004_ODR, wlinkbuf[wbuf_read_offset++]);
if (wbuf_read_offset == wbuf_write_offset) {
wlink_busy = 0;
} else {
b008_intmask |= B008_OUTINT_ENA;
sys_outb(B008_INT, b008_intmask);
sys_outb(B004_OSR, B004_INT_ENA);
}
}
}
I check whether I'm currently writing, then whether the output is ready.
If it is, I disable that interrupt (both ways), and write the next byte.
If that wasn't the last one, I re-enable the interrupt.
Actually, it just strikes me that doing things this way in MINIX may be
too slow for interrupt-per-byte communication with the transputers. The sys_outb() calls use message passing through the microkernel between the
driver and the kernel proper, and I may just be too slow re-enabling.
Maybe do this polled, for now, ditch this part of the interrupt
handling, and start experimenting with DMA, instead?
Incidentally, is there a way for the driver to detect whether it's
talking to a B004 or a B008? The interrupt control register is,
according to the documentation for the older version of the B008 that I
have, write only, which seems to leave nothing the driver can depend on.
Maybe I can, just after the reset, when I know the output ready bit in
the OSR is 1, compare what happens when I enable the interrupt in the
OSR with and without the enabling bit in the B008 specific interrupt
control register set? If the B008 specific bit turns out to make a
difference, that must be the board I have... I'll give that a go.
0 T805d-25 39k 0 [ HOST 1:1 3:1 ... ]
39k ... that's horrible slow. Check you ISA IO settings in the BIOS.
Yeah - I still have some usleep() delays in there that I probably don't
need, and some debug output to console. I should get better speeds once
I tidy up that stuff. Been too focused on figuring out interrupts... :)
-tih
--
Most people who graduate with CS degrees don't understand the significance
of Lisp. Lisp is the most important idea in computer science. --Alan Kay
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