On Mon, 04 Apr 2016 13:01:50 +0200, Morten Reistad wrote:
In article <pfp9tc-bvt.ln1@news.informatik.uni-stuttgart.de>, Christian
Corti <cc@corti-net.de> wrote:
Dylan McNamee <dylan.mcnamee@gmail.com> wrote:
That is a great thread - thanks for the pointer! It seems that this is >>>> mostly an artifact of papertape and 6-bit ASCII, bothof which (mostly) went away after the PDP-8.
No and no.
First, ASCII is seven bits (octal 0-177). Second, it has nothing to do >>>with papertape or Teletypes. DEC simply defined the parity bit to be
mark (i.e. always 1), since the serial interface is 8 bits fixed.
They were not alone in doing this. Prime computer also had the MSB set
in all of their ASCII. Saving a few cents worth of hardware in the
serial ports and/or some cycles processing them. But leading to decades
of incompatibility.
ISTR having the same thing on a Honeywell DDP-516.
In article <dmf3pdFs66uU6@mid.individual.net>,
Bob Eager <news0006@eager.cx> wrote:
On Mon, 04 Apr 2016 13:01:50 +0200, Morten Reistad wrote:
In article <pfp9tc-bvt.ln1@news.informatik.uni-stuttgart.de>,
Christian Corti <cc@corti-net.de> wrote:
Dylan McNamee <dylan.mcnamee@gmail.com> wrote:
That is a great thread - thanks for the pointer! It seems that thisof which (mostly) went away after the PDP-8.
is mostly an artifact of papertape and 6-bit ASCII, both
No and no.
First, ASCII is seven bits (octal 0-177). Second, it has nothing to do >>>>with papertape or Teletypes. DEC simply defined the parity bit to be >>>>mark (i.e. always 1), since the serial interface is 8 bits fixed.
They were not alone in doing this. Prime computer also had the MSB set
in all of their ASCII. Saving a few cents worth of hardware in the
serial ports and/or some cycles processing them. But leading to
decades of incompatibility.
ISTR having the same thing on a Honeywell DDP-516.
ISTR that the earliest Primes (up to the 400, ISTR) were
embrace-and-extend versions of the DDP-5xx architecture. Later versions
had compatibility-mode (R-mode?) that ran DDP-516 code.
Crossposted to comp.sys.prime, and followup-to set there.
ISTR that the earliest Primes (up to the 400, ISTR) were embrace-and-extend versions of the DDP-5xx architecture. Later versions had compatibility-mode (R-mode?) that ran DDP-516 code.
ISTR that the earliest Primes (up to the 400, ISTR) were embrace-and-extend versions of the DDP-5xx architecture. Later versions had compatibility-mode (R-mode?) that ran DDP-516 code.
Prime called the x16 mode S mode. As far as I know, it existed
until the end. Even the 100 and 200 had R-mode, though, the "embrace
and extend".
The P300 added virtual memory.
In article <3cSdnc2MWvG_jZ7KnZ2dnUU7-VfNnZ2d@giganews.com>,
Dennis Boone <drb@ihatespam.msu.edu> wrote:
ISTR that the earliest Primes (up to the 400, ISTR) were embrace-and-extend
versions of the DDP-5xx architecture. Later versions had compatibility-mode
(R-mode?) that ran DDP-516 code.
Prime called the x16 mode S mode. As far as I know, it existed
until the end. Even the 100 and 200 had R-mode, though, the "embrace
and extend".
The P300 added virtual memory.
They sure had a lot of processor modes, S, R, I, V and IX. This puts even
a '486 and an ARM8 (with 64, 32 and 24 bit modes plus thumb2) to shame.
-- mrr
On Monday, April 4, 2016 at 10:18:33 PM UTC-4, Morten Reistad wrote:
In article <3cSdnc2MWvG_jZ7KnZ2dnUU7-VfNnZ2d@giganews.com>,
Dennis Boone <drb@ihatespam.msu.edu> wrote:
ISTR that the earliest Primes (up to the 400, ISTR) were embrace-and-extend
versions of the DDP-5xx architecture. Later versions had compatibility-mode
(R-mode?) that ran DDP-516 code.
Prime called the x16 mode S mode. As far as I know, it existed
until the end. Even the 100 and 200 had R-mode, though, the "embrace
and extend".
The P300 added virtual memory.
They sure had a lot of processor modes, S, R, I, V and IX. This puts even
a '486 and an ARM8 (with 64, 32 and 24 bit modes plus thumb2) to shame.
-- mrr
And within each processor mode are multiple addressing schemes indicated in a different way in each mode:
- sector 0 relative
- program counter relative
- preindexed by index register
- postindexed by index register
- optional indirect
- base register relative (4 varieties)
- field address register relative
- general register relative
- gr indexed
In article <58a75f84-abea-4d96-a79d-9ec639f6fc26@googlegroups.com>,
Jim Wilcoxson <prirun@gmail.com> wrote:
On Monday, April 4, 2016 at 10:18:33 PM UTC-4, Morten Reistad wrote:
In article <3cSdnc2MWvG_jZ7KnZ2dnUU7-VfNnZ2d@giganews.com>,
Dennis Boone <drb@ihatespam.msu.edu> wrote:
ISTR that the earliest Primes (up to the 400, ISTR) were embrace-and-extend
versions of the DDP-5xx architecture. Later versions had compatibility-mode
(R-mode?) that ran DDP-516 code.
Prime called the x16 mode S mode. As far as I know, it existed
until the end. Even the 100 and 200 had R-mode, though, the "embrace
and extend".
The P300 added virtual memory.
They sure had a lot of processor modes, S, R, I, V and IX. This puts even >> a '486 and an ARM8 (with 64, 32 and 24 bit modes plus thumb2) to shame.
-- mrr
And within each processor mode are multiple addressing schemes indicated in a different way in each mode:
- sector 0 relative
- program counter relative
- preindexed by index register
- postindexed by index register
- optional indirect
- base register relative (4 varieties)
- field address register relative
- general register relative
- gr indexed
I discovered this in october 1984 when I read the processor and PMA
manuals for Primos 19.3; while upgrading to 19.4.
That was when I decided that I'll stick to procedural languages, after
doing assembly programming for nearly a decade. First the 6502, then the PDP10, then the Z80, a little PDP11s, and then the Prime. After a few
weeks with PMA I went for FTN, PLP, SPL and all the other Prime-specific stuff.
-- mrr
On Wednesday, 6 April 2016 00:04:45 UTC+10, Morten Reistad wrote:
In article <58a75f84-abea-4d96-a79d-9ec639f6fc26@googlegroups.com>,
Jim Wilcoxson <prirun@gmail.com> wrote:
On Monday, April 4, 2016 at 10:18:33 PM UTC-4, Morten Reistad wrote:
In article <3cSdnc2MWvG_jZ7KnZ2dnUU7-VfNnZ2d@giganews.com>,
Dennis Boone <drb@ihatespam.msu.edu> wrote:
ISTR that the earliest Primes (up to the 400, ISTR) were embrace-and-extend
versions of the DDP-5xx architecture. Later versions had compatibility-mode
(R-mode?) that ran DDP-516 code.
Prime called the x16 mode S mode. As far as I know, it existed
until the end. Even the 100 and 200 had R-mode, though, the "embrace >> >and extend".
The P300 added virtual memory.
They sure had a lot of processor modes, S, R, I, V and IX. This puts even
a '486 and an ARM8 (with 64, 32 and 24 bit modes plus thumb2) to shame. >>
-- mrr
And within each processor mode are multiple addressing schemes indicated in a different way in each mode:
- sector 0 relative
- program counter relative
- preindexed by index register
- postindexed by index register
- optional indirect
- base register relative (4 varieties)
- field address register relative
- general register relative
- gr indexed
I discovered this in october 1984 when I read the processor and PMA
manuals for Primos 19.3; while upgrading to 19.4.
That was when I decided that I'll stick to procedural languages, after doing assembly programming for nearly a decade. First the 6502, then the PDP10, then the Z80, a little PDP11s, and then the Prime. After a few
weeks with PMA I went for FTN, PLP, SPL and all the other Prime-specific stuff.
-- mrr
Same with me and a few others I think.
I had some IBM S/370 Assembler experience and loved it.
Got a copy of PMA manual and stopped.
Then found FTN was there (I was on a customer site and no PLP/SPL).
The rest is history.
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