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  • 68EC020 cache question

    From Roger Hanscom@21:1/5 to All on Mon Jun 19 10:15:47 2023
    I'm looking into the firmware for a 68EC020 based device, and find multiple examples of a cache access code that goes something like this:
    save D0 to the stack
    get CACR into D0
    save it to the stack
    load zero to D0
    write D0 to CACR
    stall for an amount of time that varies in places in the firmware
    restore CACR from value saved in stack
    restore D0 from the stack
    From what I'm reading about the 68EC020 cache, disabling cache (which I think is what this does?) does not change the cache contents. So I'm not understanding what these code routines in the firmware do. Flush the cache? What am I missing here?

    Roger

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  • From thomasalexanderevans@gmail.com@21:1/5 to Roger Hanscom on Mon Jun 19 19:04:27 2023
    On Tuesday, June 20, 2023 at 3:15:48 AM UTC+10, Roger Hanscom wrote:
    I'm looking into the firmware for a 68EC020 based device, and find multiple examples of a cache access code that goes something like this:
    save D0 to the stack
    get CACR into D0
    save it to the stack
    load zero to D0
    write D0 to CACR
    stall for an amount of time that varies in places in the firmware
    restore CACR from value saved in stack
    restore D0 from the stack
    From what I'm reading about the 68EC020 cache, disabling cache (which I think is what this does?) does not change the cache contents. So I'm not understanding what these code routines in the firmware do. Flush the cache? What am I missing here?

    Long time no posts!

    Can't tell. But what is it doing when it is "stalling"? Disabling the cache may let it write directly to memory (or an i/o mapped peripheral) or read a memory location that some DMA hardware is reading or writing.

    Why not post on the NXP Community Forums in the "ColdFire/68K Microcontrollers and Processors" part?

    T

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  • From Roger Hanscom@21:1/5 to All on Tue Jun 20 08:04:40 2023
    Thanks for your interest in this "problem"!

    Can't tell. But what is it doing when it is "stalling"?

    Nothing? It's a very tight loop. For example:

    move.l #$8b74,d0
    zzzz: subq.l #1,d0
    bne.s zzzz

    There are a number of Cirrus Logic CD-1400 "serial communication engines" on the PCB. I believe they have the capability to buffer quite a bit of data (compared to other (older) UART devices)? Could this be a way to let them flush their buffers?

    Why not post on the NXP Community Forums in the "ColdFire/68K Microcontrollers and Processors" part?

    Didn't know such a forum existed. I'll try that!

    Roger

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  • From David Schultz@21:1/5 to thomasalex...@gmail.com on Tue Jun 20 10:21:38 2023
    On 6/19/23 9:04 PM, thomasalex...@gmail.com wrote:
    On Tuesday, June 20, 2023 at 3:15:48 AM UTC+10, Roger Hanscom wrote:
    I'm looking into the firmware for a 68EC020 based device, and find multiple examples of a cache access code that goes something like this:
    save D0 to the stack
    get CACR into D0
    save it to the stack
    load zero to D0
    write D0 to CACR
    stall for an amount of time that varies in places in the firmware

    Perhaps a delay and it was deemed too difficult to generate accurate
    timings with the cache enabled.

    --
    http://davesrocketworks.com
    David Schultz

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  • From Roger Hanscom@21:1/5 to David Schultz on Wed Jun 21 08:56:22 2023
    On Tuesday, June 20, 2023 at 8:21:42 AM UTC-7, David Schultz wrote:

    Perhaps a delay and it was deemed too difficult to generate accurate timings with the cache enabled.

    Ahhh .... I see what you're saying. With cache enabled, timing loops wouldn't necessarily be deterministic? By golly .... you might be right!!!

    Roger

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