paltoran@gmail.com wrote:
On Monday, 17 September 2018 22:36:28 UTC+1, Theo wrote:
Sounds like fun.
Fingers crossed!
The protocol is rather interesting. I think doing it in a CPLD (basic FPGA) would probably be most flexible, but I can understand that's a
place you don't want to go. Also, you need to a device with 5V
capability, which is quite rare nowadays.
I hadn't heard of CPLDs before, although to be fair I didn't know much
about FPGAs until a couple of days ago. I'll do some research into CPLD
test boards. Even if I don't use it for this project, it'll be good to learn.
I've used the Altera MAX-II and some from Lattice (a long time ago). The Altera ones use their FPGA tools, which are a bit unwieldy but OK when you
get into them.
I'd start with a chip that does 5V, and a dev board that has some example projects you can modify. You don't need to know a whole lot of Verilog or
VHDL to write basic logic. It's better if you can run your code in a
simulator first, because then you can more easily see what's going on than trying to probe hardware.
Converting to parallel with shift registers is a really good idea. How
would that work with the data heading back to the Psion? Would I need to keep an eye on the first three bits from the Psion for a data request command, then get the output shift register to send data back?
Something like that. You could clock the input and output shift registers
at the same time and then select one based on the direction. Or you could
have 8 bit in/out shift registers and then implement the remaining 4 bits in discrete logic.
Do you have oscilloscope traces[1]? That's where I'd start. (I wonder if there's a way to work out which end is driving at any given time? For instance, gimp the power supply so the SSD voltage is slightly lower than the other, or something like that?)
I haven't got an oscilloscope, but I've just bought the logic analyser you linked to. Very pleased that Sigrok is open source and runs on Linux.
The only examples of the protocol I have are from the HDK.[1] I'm going to make an adapter so that I can use an SSD from outside the Psion. That
would make it easier for me to use a separate power source for the SSD,
too. Alternatively, could I put something in the middle that would
monitor the signals and separate them? Thinking about it, maybe a CPLD
would do the trick...
One useful thing about CPLDs is you can largely decouple the physical/board design from the logic. You can put down the CPLD on the PCB and then figure out what logic you need later - as long as it still fits within the CPLD.
They are also handy for voltage conversion - for example, if you wanted to attach to a Raspberry Pi or similar which has 3.3V I/O - you just wire up
I/Os of different voltages to different I/O banks on the CPLD, and set the IOVCC of each bank to the voltage you need.
So a little breakout board with a CPLD, a connector for an ESP8266 (or
whatever you want), and some header pins for probing or taking to a
computer, might be a very useful first step.
Hmm, now I look it seems 5V capable CPLDs are getting rare now.
It might be worth trying an Altera MAX II board with an EPM240 part:
https://www.openimpulse.com/blog/products-page/product-category/max-ii-epm240-cpld-minimal-development-board/
https://www.ebay.co.uk/itm/1PCS-Altera-MAX-II-EPM240-CPLD-development-board-learning-board-breadboard-NEW-C/191911917944
and then adding a clamp diode/resistor arrangement described in ch8:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max2/max2_mii5v1.pdf
While this board is cheap, there's not a whole lot of info available for it.
So you could also look at other MAX II boards with better documentation/tutorials. There are also tutorials for larger FPGAs (the tools/design flow is largely the same) but you'd need to do some translation for your board.
Thanks - looks like I'm going to need it!
:-)
Theo
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