PCINFO, PS2SYSTM.1

TITLE: 9556
Model Bus Proc./MHz Slots Planar Memory Hard Disk Size &
Type /Bays Std/Max / Comments

9556-0B6 MC 486SLC2 25/50 3/3 8/16 MB (70ns) 104MB SCSI
-0BA MC 486SLC2 25/50 3/3 8/16 MB (70ns) 212MB SCSI
-2BX MC 486SLC2 25/50 3/3 4/16 MB (70ns) 56LS /NONE /
TOKEN RING
-KB6 MC 486SLC2 25/50 3/3 8/16 MB (70ns) 104MB SCSI /
OS/2 2.1
-KB6F Canadian French model
-KBA MC 486SLC2 25/50 3/3 8/16 MB (70ns) 212MB SCSI /
OS/2 2.1
-KBAF Canadian French model
-DB6 Replaces 0B6, KB6 - provides choice of preloaded OS
As of 3/15/94, the 104MB drive was replaced by a 170MB drive
-DBA Replaces 0BA, KBA - provides choice of preloaded OS
As of 3/15/94, the 212MB drive was replaced by a 270MB drive
-DE9 MC 486SLC3 25/75 3/3 8/16 MB (70ns) 170MB SCSI
-DEB MC 486SLC3 25/75 3/3 8/16 MB (70ns) 245MB SCSI
As of 3/31/94, the 245MB drive was replaced by a 270MB drive
-DED MC 486SLC3 25/75 3/3 8/16 MB (70ns) 340MB SCSI
-DEG MC 486SLC3 25/75 3/3 8/16 MB (70ns) 540MB SCSI
-2EX MC 486SLC3 25/75 3/3 4/16 MB (70ns) 56LS /NONE /
TOKEN RING

NOTE: Premier replacement for the 8556. 9556 has these additional features:
1) Premier line has 3 year on-site warranty
2) ISO-compliant
3) 32-bit XGA-2 with 1MB VRAM rather than 16-bit VGA (see note 9)
4) More base memory (8MB) in comparison to some 8556 models
5) Different size SCSI drives standard
6) Faster clock speed. 9556 is a 486SLC2 25/50 MHz. The 8556 with
the SLC2 upgrade runs at 20/40 MHz
7) Better interior space utilization provides an extra bay
8) 32-bit Busmaster SCSI-2 (see note 9)
9) The external I/O bus is 16-bit, like the 8556. However, the
9556's SCSI-2 and XGA-2 are 32-bit by being built into the planar and
therefore utilizing the internal bus.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

The SLC2 chip is a pin-compatible replacement for i386SX (ignoring the
lower core voltage). They both have a 16-bit external data bus. So I
don't see how could they possibly get a real 32-bit planar I/O bus from
that (aside from what I mention in the 3rd paragraph).

Now, the SLC3 is a different story. It was designed to replace a 386*DX*
and it indeed has a 32-bit external data bus (possibly switchable
between 16- and 32-bit mode).

But if you compare the 9556/7 SLC2 and SLC3 planars, they are virtually identical (aside from the CPU itself). Which doesn't make much sense.
Unless both planars use a 32-bit path from the BIC to the XGA-2 and SCSI subsystems and it's only the CPU <-> BIC bus ("FSB") that differs
between the two (single-cycle 32-bit vs. double-cycle 16-bit). Of
course, the 16-bit FSB path would cripple the rest of the system, and
you wouldn't get real 32-bit performance from the onboard subsystems,
but it may still give you some performance lift (FSB runs @ 25 MHz, I/O
at 10 MHz). I'm not sure how is the memory subsystem implemented in
these systems, but this is probably where the real bottleneck would be
(even with the larger L1 cache).

On 08.12.2021 4:42, Louis Ohland wrote:

PCINFO, PS2SYSTM.1

TITLE: 9556
Model      Bus   Proc./MHz   Slots    Planar Memory     Hard Disk Size &
Type                          /Bays     Std/Max           / Comments

9556-0B6   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   104MB SCSI
    -0BA   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   212MB SCSI
    -2BX   MC  486SLC2 25/50  3/3     4/16 MB (70ns)   56LS /NONE /
TOKEN RING
    -KB6   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   104MB SCSI /
OS/2 2.1
    -KB6F  Canadian French model
    -KBA   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   212MB SCSI /
OS/2 2.1
    -KBAF  Canadian French model
    -DB6   Replaces 0B6, KB6 - provides choice of preloaded OS
           As of 3/15/94, the 104MB drive was replaced by a 170MB drive
    -DBA   Replaces 0BA, KBA - provides choice of preloaded OS
           As of 3/15/94, the 212MB drive was replaced by a 270MB drive
    -DE9   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   170MB SCSI
    -DEB   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   245MB SCSI
           As of 3/31/94, the 245MB drive was replaced by a 270MB drive
    -DED   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   340MB SCSI
    -DEG   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   540MB SCSI
    -2EX   MC  486SLC3 25/75  3/3     4/16 MB (70ns)   56LS /NONE /
TOKEN RING

NOTE: Premier replacement for the 8556.  9556 has these additional
features:
      1) Premier line has 3 year on-site warranty
      2) ISO-compliant
      3) 32-bit XGA-2 with 1MB VRAM rather than 16-bit VGA (see note 9)
      4) More base memory (8MB) in comparison to some 8556 models
      5) Different size SCSI drives standard
      6) Faster clock speed. 9556 is a 486SLC2 25/50 MHz. The 8556 with the SLC2 upgrade runs at 20/40 MHz
      7) Better interior space utilization provides an extra bay
      8) 32-bit Busmaster SCSI-2 (see note 9)
      9) The external I/O bus is 16-bit, like the 8556.  However, the 9556's SCSI-2 and XGA-2 are 32-bit by being built into the planar and
         therefore utilizing the internal bus.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Tom, I was bi-curious about "32-bit" in a 9556. It is either a typo/
mis-match / sloppy cut 'n paste... The 9556-DEB -DOES- use a 16-bit riser.

Not sure of the system board level path.

An evil thought - IBM slapped a SLC3 on the SLC2 system without much alteration...

A weg to test this would be to test / probe the XGA-2 for data-path
width, fall-back would be testing performance. As you refer to it "double-cycle".

On 12/9/2021 10:23, Tomas Slavotinek wrote:

The SLC2 chip is a pin-compatible replacement for i386SX (ignoring the
lower core voltage). They both have a 16-bit external data bus. So I
don't see how could they possibly get a real 32-bit planar I/O bus from
that (aside from what I mention in the 3rd paragraph).

Now, the SLC3 is a different story. It was designed to replace a 386*DX*
and it indeed has a 32-bit external data bus (possibly switchable
between 16- and 32-bit mode).

But if you compare the 9556/7 SLC2 and SLC3 planars, they are virtually identical (aside from the CPU itself). Which doesn't make much sense.
Unless both planars use a 32-bit path from the BIC to the XGA-2 and SCSI subsystems and it's only the CPU <-> BIC bus ("FSB") that differs
between the two (single-cycle 32-bit vs. double-cycle 16-bit). Of
course, the 16-bit FSB path would cripple the rest of the system, and
you wouldn't get real 32-bit performance from the onboard subsystems,
but it may still give you some performance lift (FSB runs @ 25 MHz, I/O
at 10 MHz). I'm not sure how is the memory subsystem implemented in
these systems, but this is probably where the real bottleneck would be
(even with the larger L1 cache).

On 08.12.2021 4:42, Louis Ohland wrote:

PCINFO, PS2SYSTM.1

TITLE: 9556
Model      Bus   Proc./MHz   Slots    Planar Memory     Hard Disk Size
& Type                          /Bays     Std/Max           / Comments

9556-0B6   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   104MB SCSI >>      -0BA   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   212MB SCSI
     -2BX   MC  486SLC2 25/50  3/3     4/16 MB (70ns)   56LS /NONE /
TOKEN RING
     -KB6   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   104MB SCSI /
OS/2 2.1
     -KB6F  Canadian French model
     -KBA   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   212MB SCSI /
OS/2 2.1
     -KBAF  Canadian French model
     -DB6   Replaces 0B6, KB6 - provides choice of preloaded OS
            As of 3/15/94, the 104MB drive was replaced by a 170MB drive
     -DBA   Replaces 0BA, KBA - provides choice of preloaded OS
            As of 3/15/94, the 212MB drive was replaced by a 270MB drive
     -DE9   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   170MB SCSI
     -DEB   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   245MB SCSI
            As of 3/31/94, the 245MB drive was replaced by a 270MB drive
     -DED   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   340MB SCSI
     -DEG   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   540MB SCSI
     -2EX   MC  486SLC3 25/75  3/3     4/16 MB (70ns)   56LS /NONE /
TOKEN RING

NOTE: Premier replacement for the 8556.  9556 has these additional
features:
       1) Premier line has 3 year on-site warranty
       2) ISO-compliant
       3) 32-bit XGA-2 with 1MB VRAM rather than 16-bit VGA (see note 9)
       4) More base memory (8MB) in comparison to some 8556 models
       5) Different size SCSI drives standard
       6) Faster clock speed. 9556 is a 486SLC2 25/50 MHz. The 8556
with the SLC2 upgrade runs at 20/40 MHz
       7) Better interior space utilization provides an extra bay
       8) 32-bit Busmaster SCSI-2 (see note 9)
       9) The external I/O bus is 16-bit, like the 8556.  However, the
9556's SCSI-2 and XGA-2 are 32-bit by being built into the planar and
          therefore utilizing the internal bus.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

The expansion bus is 16-bit, no doubt about that :)

Either the SLC3 can be switched to a 16-bit mode and they did just that,
or the planar logic was designed with SLC2 and 3 and two different FSB
widths in mind, requiring only minimal layout changes in the CPU area.

I was about to mention benchmarking, but you were faster...

It would be interesting to do the following performance tests on the
955x SLC2 and SLC3 planars:

-disable L1 to make the external bus bottleneck more significant
-set both chips to the x2 multiplier mode
-use some CPU detection software to check that everything is set correctly
-run calculation, memory, and I/O-focused benchmarks on both planars

If the SLC3 chip really runs with a 32-bit "FSB" enabled there should be
some measurable performance difference when compared to SLC2. If they
both run on a 16-bit data bus, the results should be exactly the same...

@David, wanna include this test in your 56/57 benchmark video?

On 09.12.2021 17:51, Louis Ohland wrote:

Tom, I was bi-curious about "32-bit" in a 9556. It is either a typo/ mis-match / sloppy cut 'n paste... The 9556-DEB -DOES- use a 16-bit riser.

Not sure of the system board level path.

An evil thought - IBM slapped a SLC3 on the SLC2 system without much alteration...

A weg to test this would be to test / probe the XGA-2 for data-path
width, fall-back would be testing performance. As you refer to it "double-cycle".

On 12/9/2021 10:23, Tomas Slavotinek wrote:

The SLC2 chip is a pin-compatible replacement for i386SX (ignoring the
lower core voltage). They both have a 16-bit external data bus. So I
don't see how could they possibly get a real 32-bit planar I/O bus
from that (aside from what I mention in the 3rd paragraph).

Now, the SLC3 is a different story. It was designed to replace a
386*DX* and it indeed has a 32-bit external data bus (possibly
switchable between 16- and 32-bit mode).

But if you compare the 9556/7 SLC2 and SLC3 planars, they are
virtually identical (aside from the CPU itself). Which doesn't make
much sense. Unless both planars use a 32-bit path from the BIC to the
XGA-2 and SCSI subsystems and it's only the CPU <-> BIC bus ("FSB")
that differs between the two (single-cycle 32-bit vs. double-cycle
16-bit). Of course, the 16-bit FSB path would cripple the rest of the
system, and you wouldn't get real 32-bit performance from the onboard
subsystems, but it may still give you some performance lift (FSB runs
@ 25 MHz, I/O at 10 MHz). I'm not sure how is the memory subsystem
implemented in these systems, but this is probably where the real
bottleneck would be (even with the larger L1 cache).

On 08.12.2021 4:42, Louis Ohland wrote:

PCINFO, PS2SYSTM.1

TITLE: 9556
Model      Bus   Proc./MHz   Slots    Planar Memory     Hard Disk
Size & Type                          /Bays     Std/Max           /
Comments

9556-0B6   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   104MB SCSI >>>      -0BA   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   212MB SCSI
     -2BX   MC  486SLC2 25/50  3/3     4/16 MB (70ns)   56LS /NONE /
TOKEN RING
     -KB6   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   104MB SCSI /
OS/2 2.1
     -KB6F  Canadian French model
     -KBA   MC  486SLC2 25/50  3/3     8/16 MB (70ns)   212MB SCSI /
OS/2 2.1
     -KBAF  Canadian French model
     -DB6   Replaces 0B6, KB6 - provides choice of preloaded OS
            As of 3/15/94, the 104MB drive was replaced by a 170MB drive
     -DBA   Replaces 0BA, KBA - provides choice of preloaded OS
            As of 3/15/94, the 212MB drive was replaced by a 270MB drive
     -DE9   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   170MB SCSI
     -DEB   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   245MB SCSI
            As of 3/31/94, the 245MB drive was replaced by a 270MB drive
     -DED   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   340MB SCSI
     -DEG   MC  486SLC3 25/75  3/3     8/16 MB (70ns)   540MB SCSI
     -2EX   MC  486SLC3 25/75  3/3     4/16 MB (70ns)   56LS /NONE /
TOKEN RING

NOTE: Premier replacement for the 8556.  9556 has these additional
features:
       1) Premier line has 3 year on-site warranty
       2) ISO-compliant
       3) 32-bit XGA-2 with 1MB VRAM rather than 16-bit VGA (see note 9)
       4) More base memory (8MB) in comparison to some 8556 models >>>        5) Different size SCSI drives standard
       6) Faster clock speed. 9556 is a 486SLC2 25/50 MHz. The 8556 >>> with the SLC2 upgrade runs at 20/40 MHz
       7) Better interior space utilization provides an extra bay
       8) 32-bit Busmaster SCSI-2 (see note 9)
       9) The external I/O bus is 16-bit, like the 8556.  However, >>> the 9556's SCSI-2 and XGA-2 are 32-bit by being built into the planar
and
          therefore utilizing the internal bus.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

The expansion bus is 16-bit, no doubt about that :)

Either the SLC3 can be switched to a 16-bit mode and they did just that,
or the planar logic was designed with SLC2 and 3 and two different FSB
widths in mind, requiring only minimal layout changes in the CPU area.

I was about to mention benchmarking, but you were faster...

It would be interesting to do the following performance tests on the
955x SLC2 and SLC3 planars:

-disable L1 to make the external bus bottleneck more significant
-set both chips to the x2 multiplier mode
-use some CPU detection software to check that everything is set correctly -run calculation, memory, and I/O-focused benchmarks on both planars

If the SLC3 chip really runs with a 32-bit "FSB" enabled there should be
some measurable performance difference when compared to SLC2. If they
both run on a 16-bit data bus, the results should be exactly the same...

@David, wanna include this test in your 56/57 benchmark video?

Sorry, I was napping - Yes, I can write up a plan. An open mind, but I wouldn't believe that the SLC3 has 32-bit connections on an 'xEx' planar. The pinout is supposed to be close to a PQFP 386DX, and I'm expecting a bunch of pins are 'N/C' on the planar.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Don't quote me on this, but isn't the 386SX 32bit internal/24bit address bus with a 16bit data path? And the SLC3 the clock-tripled SX? What you possibly mean sounds like the DLC - the DX replacement with 32bit external data path.

IBMMuseum schrieb am Mittwoch, 15. Dezember 2021 um 00:02:36 UTC+1:

The expansion bus is 16-bit, no doubt about that :)

Either the SLC3 can be switched to a 16-bit mode and they did just that, or the planar logic was designed with SLC2 and 3 and two different FSB widths in mind, requiring only minimal layout changes in the CPU area.

I was about to mention benchmarking, but you were faster...

It would be interesting to do the following performance tests on the
955x SLC2 and SLC3 planars:

-disable L1 to make the external bus bottleneck more significant
-set both chips to the x2 multiplier mode
-use some CPU detection software to check that everything is set correctly -run calculation, memory, and I/O-focused benchmarks on both planars

If the SLC3 chip really runs with a 32-bit "FSB" enabled there should be some measurable performance difference when compared to SLC2. If they
both run on a 16-bit data bus, the results should be exactly the same...

@David, wanna include this test in your 56/57 benchmark video?

Sorry, I was napping - Yes, I can write up a plan. An open mind, but I wouldn't believe that the SLC3 has 32-bit connections on an 'xEx' planar. The pinout is supposed to be close to a PQFP 386DX, and I'm expecting a bunch of pins are 'N/C' on the

planar.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

From my fervid imagination, the SLC3 has the lines for 32-bit external,
but they aren't connected. The 9556 has nowhere for those lines to go.

Wish we had the tech ref / datasheets for it...

On 12/16/2021 10:01, schimmi wrote:

Don't quote me on this, but isn't the 386SX 32bit internal/24bit address bus with a 16bit data path? And the SLC3 the clock-tripled SX? What you possibly mean sounds like the DLC - the DX replacement with 32bit external data path.

IBMMuseum schrieb am Mittwoch, 15. Dezember 2021 um 00:02:36 UTC+1:

The expansion bus is 16-bit, no doubt about that :)

Either the SLC3 can be switched to a 16-bit mode and they did just that, >>> or the planar logic was designed with SLC2 and 3 and two different FSB
widths in mind, requiring only minimal layout changes in the CPU area.

I was about to mention benchmarking, but you were faster...

It would be interesting to do the following performance tests on the
955x SLC2 and SLC3 planars:

-disable L1 to make the external bus bottleneck more significant
-set both chips to the x2 multiplier mode
-use some CPU detection software to check that everything is set correctly >>> -run calculation, memory, and I/O-focused benchmarks on both planars

If the SLC3 chip really runs with a 32-bit "FSB" enabled there should be >>> some measurable performance difference when compared to SLC2. If they
both run on a 16-bit data bus, the results should be exactly the same... >>>
@David, wanna include this test in your 56/57 benchmark video?

Sorry, I was napping - Yes, I can write up a plan. An open mind, but I wouldn't believe that the SLC3 has 32-bit connections on an 'xEx' planar. The pinout is supposed to be close to a PQFP 386DX, and I'm expecting a bunch of pins are 'N/C' on the

planar.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

I've done some probing on the SLC3 planar and the CPU indeed seems to be pin-compatible with the 386DX PQFP chip, at least as far as the power
and ground pins are concerned. The clock input is also where it should be.

Now, the interesting thing is that there are some traces going from the supposed D17-31 and A24-31 pins. However, as far as I can tell all of
them are terminated by a via and don't go anywhere else from there. The
lower bits are easy to trace down - they go to the "system controller"
96F7690 (bus interface, memory controller...), the SCSI controller
91F9906, and also some other components. The same can't be said about
the higher bits. I've probed pretty much the entire planar and got
nothing. But ut's strange that the traces exist at all. If it was just a
set of fan-out vias, I wouldn't think much of it, but some of them are
rather far away from the chip. Some are hidden under other components,
so they can't be test points either. Strange...

Either way, it seems that the CPU data and address buses are only 16-
and 24-bits wide.

Well, this exercise at least helped me identify some of the components.
I'll update the parts list in a bit...

Btw, the SCSI controller is connected directly to the CPU bus (both
address and data), so it's essentially a local bus SCSI controller...

The onboard XGA-2 controller is connected to the shared planar/micro
channel bus as expected. There are only three 8-bit address buffers
associated with it, so it's also limited to a 24-bit address bus (and
most likely 16-bit data, but I don't have a standalone XGA-2 adapter
here to verify that...)

On 16.12.2021 19:06, Louis Ohland wrote:

From my fervid imagination, the SLC3 has the lines for 32-bit external,
but they aren't connected. The 9556 has nowhere for those lines to go.

Wish we had the tech ref / datasheets for it...

On 12/16/2021 10:01, schimmi wrote:

Don't quote me on this, but isn't the 386SX 32bit internal/24bit
address bus with a 16bit data path? And the SLC3 the clock-tripled SX?
What you possibly mean sounds like the DLC - the DX replacement with
32bit external data path.

IBMMuseum schrieb am Mittwoch, 15. Dezember 2021 um 00:02:36 UTC+1:

The expansion bus is 16-bit, no doubt about that :)

Either the SLC3 can be switched to a 16-bit mode and they did just
that,
or the planar logic was designed with SLC2 and 3 and two different FSB >>>> widths in mind, requiring only minimal layout changes in the CPU area. >>>>
I was about to mention benchmarking, but you were faster...

It would be interesting to do the following performance tests on the
955x SLC2 and SLC3 planars:

-disable L1 to make the external bus bottleneck more significant
-set both chips to the x2 multiplier mode
-use some CPU detection software to check that everything is set
correctly
-run calculation, memory, and I/O-focused benchmarks on both planars

If the SLC3 chip really runs with a 32-bit "FSB" enabled there
should be
some measurable performance difference when compared to SLC2. If they
both run on a 16-bit data bus, the results should be exactly the
same...

@David, wanna include this test in your 56/57 benchmark video?

Sorry, I was napping - Yes, I can write up a plan. An open mind, but
I wouldn't believe that the SLC3 has 32-bit connections on an 'xEx'
planar. The pinout is supposed to be close to a PQFP 386DX, and I'm
expecting a bunch of pins are 'N/C' on the planar.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

So, does this mean the SCSI controller does not have to negotiate for
the MCA bus -IF- the request is from the CPU?

Obviously, if the request is from a MCA slot mounted adapter, -THEN- the
SCSI controller negotiates for the MCA bus...

On 12/18/2021 10:57, Tomas Slavotinek wrote:

Btw, the SCSI controller is connected directly to the CPU bus (both
address and data), so it's essentially a local bus SCSI controller...

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Yep, I assume so.

On 18.12.2021 19:48, Louis Ohland wrote:

So, does this mean the SCSI controller does not have to negotiate for
the MCA bus -IF- the request is from the CPU?

Obviously, if the request is from a MCA slot mounted adapter, -THEN- the
SCSI controller negotiates for the MCA bus...

On 12/18/2021 10:57, Tomas Slavotinek wrote:

Btw, the SCSI controller is connected directly to the CPU bus (both
address and data), so it's essentially a local bus SCSI controller...

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Now that makes me wonder if you are a real person, or a
machine-generated persona.

Who the heck DOESN'T have multiple XGA-2 cards?

On 12/18/2021 10:57, Tomas Slavotinek wrote:

I don't have a standalone XGA-2 adapter here

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Maybe we are all machine-generated. Maybe this entire universe is just a simulation. How would we know?

Anyway, I don't have any of my PS/2 stuff here at home anymore...

On 19.12.2021 3:48, Louis Ohland wrote:

Now that makes me wonder if you are a real person, or a
machine-generated persona.

Who the heck DOESN'T have multiple XGA-2 cards?

On 12/18/2021 10:57, Tomas Slavotinek wrote:

I don't have a standalone XGA-2 adapter here

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On 12/19/2021 04:40, Tomas Slavotinek wrote:

I don't have any of my PS/2 stuff here at home anymore...

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Louis Ohland schrieb am Sonntag, 19. Dezember 2021 um 13:27:51 UTC+1:

On 12/19/2021 04:40, Tomas Slavotinek wrote:

I don't have any of my PS/2 stuff here at home anymore...

"Either way, it seems that the CPU data and address buses are only 16-
and 24-bits wide. "

^^Yep, this is my understanding of a 386SX :)
Didn't know anything about the pin-compatibility SLC3 vs. DX. Interesting, thank you.
So, the planar itself was 'prepared' for an external 32bit bus?

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Yeah, externally, the 386SX is very close to the older 286 design with
its 16/24-bit bus.

The SLC3/BL chip supports 32-bit buses, the planar doesn't. As far as I
can tell, the additional traces go nowhere. Maybe they wanted to have a
32-bit path to the local SCSI controller but scraped the idea for
whatever reason. But that doesn't explain the leftover stuff, because
normally you rework the schematic first and only then move to the PCB
layout, running the autorouter, or whatever.

I wonder if the SCSI controller is 32-bit wide externally and the only
thing missing are the traces and maybe some glue to handle the bus mode switching.

I'll probably revisit this later...

On 21.12.2021 19:47, schimmi wrote:

Louis Ohland schrieb am Sonntag, 19. Dezember 2021 um 13:27:51 UTC+1:

On 12/19/2021 04:40, Tomas Slavotinek wrote:

I don't have any of my PS/2 stuff here at home anymore...

"Either way, it seems that the CPU data and address buses are only 16-
and 24-bits wide. "

^^Yep, this is my understanding of a 386SX :)
Didn't know anything about the pin-compatibility SLC3 vs. DX. Interesting, thank you.
So, the planar itself was 'prepared' for an external 32bit bus?

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