The subaddress-pointer registers located at input/output ports 106(hex)
and 107(hex) serve a dual function, storing channel check status
information in addition to pointing to subaddressing data. A specially defined bit, called the channel check status indicator field and located
at bit six in the register at I/O port 105(hex), shows which of the two functions these registers are performing at any given time. When the
Channel Check Status Indicator Field shows a value of a logical zero, it means that registers 106(hex) and 107(hex) provide Channel Check status
(or point to the location where this status information is stored). When
this bit indicates a logical one, registers 106(hex) and 107(hex) can be
used as pointers to subaddressing data.
Ryan, the references barely mention POS 5 bits 6,7 when those two bits determine the function of POS 6 and POS 7.
I sendt you a link to my latest brainchild page, http://ps-2.kev009.com/ohland/9-K/9-K_and_XPOS.html
I think they futzed up POS 5 bits 6,7 with POS 6 and POS 7. Then they
say to use POS 4 to access the XPOS. I am kontuzed.
Ryan Alswede wrote:
Bit 7 of POS register 5 is set to 1 unless -CHCK is active from the
adapter.
The remaining bits can be implemented as required....
hex 0105
bit 6 **may** be used to indicate that additional status is available
through bytes hex 0106 and 0107.
The indicator is set to 0 on a channel check condition, or when bit
7 of hex 0105 is o. The indicator is set to 1 on a channel reset, or
when bit 7 of hex 0105 is 1. This bit may be reset by any action
that occurs during the channel check service routine.
-------
Will look at this next:
This byte may be read at address hex 0091. Bit 0 of this
byte is set to 1 whenever the 'card selected feedback' signal was
active on a previous cycle or when the system board 1/0 functions
(diskette drive, serial, or parallel interfaces) are accessed by an 1/0
cycle. Bit 0 is reset by the read operation
Bit 7 of POS register 5 is set to 1 unless -CHCK is active from the adapter. The remaining bits can be implemented as required....
hex 0105
bit 6 **may** be used to indicate that additional status is available
through bytes hex 0106 and 0107.
The indicator is set to 0 on a channel check condition, or when bit
7 of hex 0105 is o. The indicator is set to 1 on a channel reset, or
when bit 7 of hex 0105 is 1. This bit may be reset by any action
that occurs during the channel check service routine.
-------
Will look at this next:
This byte may be read at address hex 0091. Bit 0 of this
byte is set to 1 whenever the 'card selected feedback' signal was
active on a previous cycle or when the system board 1/0 functions
(diskette drive, serial, or parallel interfaces) are accessed by an 1/0 cycle. Bit 0 is reset by the read operation
POS 5 bit 6 is not implemented on this card. All the mca docs say **may**. They are not using POS 6 or 7 for error status.
POS 6 is the address value mapping to sub register.
POS 7 turns on the piping from POS 4 to the registered addressed by POS 6.
This is just a patent doc so who knows what they revised when going to the real AIC-906R chip
Well, is B32 present? That is the -CHCK line.
The wimpy announcements make no mention of Channel Czech.
I started looking for a proper 100 MHz capable, multi-channel logic analyzer like the HP 16700 series to capture the initialization sequence directly on the bus, but those machines all look either dead or incomplete and still very expensive, ifavailable at all in my old world.
Any suggestions for an alternative?
Just for fun I fired up my -42T and stuffed 3 San Remo cards in it.
Check out the dump:
http://www.holzapfel.biz/8F62/IO_POS_3x_8F62.txt
I also added the current ressource configuration for comparison.
Looks like POS[3] upper nibble is clearly DMA arbitration level.
Still unsure about interrupt level and if the I/O dump is useful at all.
Are we sure the missing configuration is done through the XPOS rather than through the I/O window or DMA memory space?
POS[4] register = 0x03 Interrupt priority 3
Got to be a simpler tool out there to just watch bits 0-3 on an address line and bits 0-7 on the data lines on a break out board when CDSETUP goes high and stop recording when CDSETUP goes low on the slot. The POS registers are only 1 byte and the buson an RS/6000 runs at a max of 20Mhz but if your machine is older then it's only 10mhz.
There's no access to POS[6-7], no signs of XPOS subaddressing at all. No mysterious, unexpected reads or writes. All very simple and basic.
I'm afraid, we're on the wrong track here, and said patent does not have anything to do with our 9-K adapter.
It must be using a completely different way of configuration, maybe through the IO window.
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