https://patents.google.com/patent/US5301282?oq=%22memory+refresh%22+%22micro+channel%22+ibm

Refresh timer and control circuit 504 generates the timing and control information necessary to refresh any memory which is used in the
computer system. More specifically, refresh timer and control circuit
504 generates a refresh request control signal (REF REQ) which is a
refresh request pulse that is dependent upon the refresh requirements of
the memory which is used in the computer system (e.g., every 15.6
microseconds for conventional dynamic random access memory). Upon
generating the first refresh request control signal, refresh timer and
control circuit 504 generates a refresh preempt signal (REF PREEMPT).
The PREEMPT signals which are generated by various devices indicate that
the device which currently has ownership of the bus has a preselected
amount of time (e.g. 7.8 microseconds) to relinquish control of the bus
so that another arbitration cycle can commence. The refresh operation is performed during the ensuing arbitration cycle. In addition to the REF
PREEMPT signal, refresh timer and control circuit 504 generates and
receives a plurality of refresh controls signals.

More specifically, refresh timer and control circuit 504 provides a
refresh complete signal (REF DONE), which indicates that the refresh
cycle or cycles are complete, a refresh request pending signal (REF REQ
PEND), which indicates that refresh of memory has been requested or is
pending, a refresh pending signal (REF PEND), which indicates that a
refresh request is pending and a bus timeout strobe signal (TOUT STR),
which indicates when three refresh requests have gone unserviced due to
the current owner of I/O bus 18 ignoring the PREEMPT signal and not
releasing the bus. The refresh control signals also include a 30 bit
address signal (A(0-29)) and a four bit byte enable signals (BE(0-3)),
which indicate which memory locations to refresh, an address strobe
signal (ADS), which indicates when to sample the address signal and a
refresh indication signal (REFRESH), which indicates that a refresh
operation is being performed. Refresh timer and control circuit 504 also generates the I/O bus control signals MIO and R/W. Refresh timer and
control circuit 504 receives refresh configuration information which is
stored in a register during power on of computer system 10, a refresh acknowledge signal (REF ACK) signal, which is provided by CACP state
machine 534 to indicate that it has granted refresh access to the bus
and bus ready signals (RDY, BRDY) which indicate that a respective bus
has completed its refresh cycles. The RDY signal is provided by bus
interface unit 54 to indicate that I/O bus 18 has completed its refresh operation and the BRDY signal is provided by memory controller 50 to
indicate that the local bus has completed its refresh operation.

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