IBM Single Chip SCSI Subsystem

http://ps-2.kev009.com/ohland/Spock_Bermuda/8556_SCSI.html

Point taken.

Tom, US5293590A Personal computer with interface controller looks to be
THE patent for the single chip scsi subsystem.

The patent does NOT appear to be recognized. Digitize me!

Somehow, there is emulation of a SCSI controller....

Tomas Slavotinek wrote:

But yes, they unique since they are single chip solutions (ignoring the
MCU) and are attached to a local bus instead of MCA.

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https://worldwide.espacenet.com/patent/search/family/025342881/publication/US5293590A?q=pn%3DUS5293590A

Louis Ohland wrote:

IBM Single Chip SCSI Subsystem

http://ps-2.kev009.com/ohland/Spock_Bermuda/8556_SCSI.html

Point taken.

Tom, US5293590A Personal computer with interface controller looks to be
THE patent for the single chip scsi subsystem.

The patent does NOT appear to be recognized. Digitize me!

Somehow, there is emulation of a SCSI controller....

Tomas Slavotinek wrote:

But yes, they unique since they are single chip solutions (ignoring
the MCU) and are attached to a local bus instead of MCA.

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Google's version is OCR'd:
https://patents.google.com/patent/US5293590A

Or did you mean the illustrations?

On 18.04.2023 17:43, Louis Ohland wrote:

https://worldwide.espacenet.com/patent/search/family/025342881/publication/US5293590A?q=pn%3DUS5293590A

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Tom, OCR or not, did you READ it?

Tomas Slavotinek wrote:

Google's version is OCR'd:
https://patents.google.com/patent/US5293590A

Or did you mean the illustrations?

On 18.04.2023 17:43, Louis Ohland wrote:

https://worldwide.espacenet.com/patent/search/family/025342881/publication/US5293590A?q=pn%3DUS5293590A

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Sometimes Gooble gives me a blank page... This worked, for some odd
raisin...

Tomas Slavotinek wrote:

Google's version is OCR'd:
https://patents.google.com/patent/US5293590A

Or did you mean the illustrations?

On 18.04.2023 17:43, Louis Ohland wrote:

https://worldwide.espacenet.com/patent/search/family/025342881/publication/US5293590A?q=pn%3DUS5293590A

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Classic IBM

This invention relates to personal computers and, more particularly, to
a personal computer having an interface controller providing an
economical way to achieve access to a direct access storage device by a
small computer system interface. In accordance with this invention, the
system CPU is selectively allowed to access all or only a portion of the internal registers in an interface controller, enabling implementation
in conjunction with a conventional subsystem microprocessor interface to
the registers if desired. With this change, either interface has full
access to the interface controller's internal registers. By allowing
such access, the number of component parts required can be reduced where multitasking possibilities are not desired, and the cost of providing
SCSI capability significantly reduced.

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On 18.04.2023 19:12, Louis Ohland wrote:

Tom, OCR or not, did you READ it?

Not yet, Louis. I have too many irons in the fire...

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On 18.04.2023 19:09, Louis Ohland wrote:

Sometimes Gooble gives me a blank page... This worked, for some odd
raisin...

You mean the Patents website or the actual PDF?

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Tom, IMHO this is about the most specific patent from IBM. No, you can't
build one after reading it, but it answers the design philosophy of
selling only what is required.

It seems the design goal was to NOT support multi-tasking. What a
conundrum, a 9533 with single chip SCSI and XGA-2 vs a 9556.

At some point, the irons should be removed from the heat and tempered...

Tomas Slavotinek wrote:

On 18.04.2023 19:12, Louis Ohland wrote:

Tom, OCR or not, did you READ it?

Not yet, Louis. I have too many irons in the fire...

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Hm, I thought, the Local Bus on a PS/2 _is_ MCA, like VLB or PCI on other machines. Do I miss something here? :)

Louis Ohland schrieb am Mittwoch, 19. April 2023 um 01:41:20 UTC+2:

Tom, IMHO this is about the most specific patent from IBM. No, you can't build one after reading it, but it answers the design philosophy of
selling only what is required.

It seems the design goal was to NOT support multi-tasking. What a
conundrum, a 9533 with single chip SCSI and XGA-2 vs a 9556.

At some point, the irons should be removed from the heat and tempered... Tomas Slavotinek wrote:

On 18.04.2023 19:12, Louis Ohland wrote:

Tom, OCR or not, did you READ it?

Not yet, Louis. I have too many irons in the fire...

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The local bus is between the CPU and the single chip SCSI, the BIC is at
the other end of the local bus and the BIC then connects to the MCA bus.

I czeched, the 8556 and 9556 are the ONLY PS/2 that use the Single Chip
SCSI. All other system-board SCSI use MCA connected SCSI.

You can see why this SCS caught my attention.

schimmi wrote:

Hm, I thought, the Local Bus on a PS/2 _is_ MCA, like VLB or PCI on other machines. Do I miss something here? :)

Louis Ohland schrieb am Mittwoch, 19. April 2023 um 01:41:20 UTC+2:

Tom, IMHO this is about the most specific patent from IBM. No, you can't
build one after reading it, but it answers the design philosophy of
selling only what is required.

It seems the design goal was to NOT support multi-tasking. What a
conundrum, a 9533 with single chip SCSI and XGA-2 vs a 9556.

At some point, the irons should be removed from the heat and tempered...
Tomas Slavotinek wrote:

On 18.04.2023 19:12, Louis Ohland wrote:

Tom, OCR or not, did you READ it?

Not yet, Louis. I have too many irons in the fire...

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Thank you both, so, a real Local Bus would be VLB with its direct ties to the 32bit CPU? Or the SCSI Chips mentioned by Louis that are connected right before the MCA Bus?

Louis Ohland schrieb am Mittwoch, 19. April 2023 um 21:46:33 UTC+2:

The local bus is between the CPU and the single chip SCSI, the BIC is at
the other end of the local bus and the BIC then connects to the MCA bus.

I czeched, the 8556 and 9556 are the ONLY PS/2 that use the Single Chip
SCSI. All other system-board SCSI use MCA connected SCSI.

You can see why this SCS caught my attention.
schimmi wrote:

Hm, I thought, the Local Bus on a PS/2 _is_ MCA, like VLB or PCI on other machines. Do I miss something here? :)

Louis Ohland schrieb am Mittwoch, 19. April 2023 um 01:41:20 UTC+2:

Tom, IMHO this is about the most specific patent from IBM. No, you can't >> build one after reading it, but it answers the design philosophy of
selling only what is required.

It seems the design goal was to NOT support multi-tasking. What a
conundrum, a 9533 with single chip SCSI and XGA-2 vs a 9556.

At some point, the irons should be removed from the heat and tempered... >> Tomas Slavotinek wrote:

On 18.04.2023 19:12, Louis Ohland wrote:

Tom, OCR or not, did you READ it?

Not yet, Louis. I have too many irons in the fire...

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On 19.04.2023 20:47, schimmi wrote:

Hm, I thought, the Local Bus on a PS/2 _is_ MCA, like VLB or PCI on other machines. Do I miss something here? :)

Well, local bus is a rather ambiguous term. Generally it has two
(sometimes overlapping) meanings:

-a bus that is a direct or almost direct extension of the CPU bus (no
bridges, only buffers... if that)
-a high-performance bus that overcomes the bandwidth limitations of the
legacy bus (this meaning is somewhat relative as "legacy" may mean ISA
or even MCA or EISA)

Some period-correct publications called MCA "a local bus" but this was
mainly to highlight its higher performance (granted, the early MCA implementations where somewhat closer to the CPU bus...).

Even PCI is sometimes called a local bus (the term is used even in the
PCI standard itself), yet it clearly is not local to the CPU, it's
always bridged.

To remove this ambiguity we use the "local bus" term only for components
that are attached directly to the CPU bus (possibly through some
buffers) - like the S3 video on Lacuna, the SCSI subsystem on the 56/57
planars, the GXT150L GPU in the RS/6000 7006, etc.

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On 19.04.2023 22:06, schimmi wrote:

Thank you both, so, a real Local Bus would be VLB with its direct ties to the 32bit CPU? Or the SCSI Chips mentioned by Louis that are connected right before the MCA Bus?

Both.

VL-bus is essentially the 32-bit 486 CPU bus wired to a connector (this
is of course far from ideal from signal integrity point of view, hence
the limitation to 3 or less slots).

Similarly The 56/57 SCSI chips are also directly connected to the 16-bit
386SX (486SLC) bus.

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The number of slots also decreases with increased speed. IIRC, you could
only use one slot at 50MHz.

Tomas Slavotinek wrote:

hence the limitation to 3 or less slots).

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But for the cost of a pint of warm beer, we might have a better answer...

I can remember the flash in the pan of VLB. Some implementations skimped
on buffering, and weren't reliable.

At some point, IBM would have evaluated it's efforts to support the
various bus flavors. ISA. PCI. MCA. VLB. RS/6000. S390. And a whole
buncha legacy big iron... Hell, AS/400...

I did see an IBM boxed VL SCSI controller, dunno if it was IBM built or
made for IBM. Lor, any comments?

I have noticed the Model 56 "local bus" comes off the CPU, shares the
SCS, and reaches the BIC. The Micro Channel is on the other side of the
BIC [and buffered by the BIC].

At this point, I am unaware of any IBM MCA system where the MCA feeds
directly off the CPU bus. Think of the DMA logic, the arbitration, and
other stuff [like memory controller].

schimmi wrote:

Hm, I thought, the Local Bus on a PS/2 _is_ MCA, like VLB or PCI on other machines. Do I miss something here? :)

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On 20.04.2023 3:13, Louis Ohland wrote:

The number of slots also decreases with increased speed. IIRC, you could
only use one slot at 50MHz.

Tomas Slavotinek wrote:

hence the limitation to 3 or less slots).

That's correct. At 50 MHz you were lucky if it even worked in the
single-slot configuration. The CPU bus was never designed for something
like this...

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Guess there was only one CPU made for this - the DX50. On my old 486/VLB setup I always had problems even with 40MHz/VLB using more than just the graphics adapter. On a 3-slot VLB Board you had one busmastering and accordingly 2 secondary slots you had
to address using more than one card, especially with a SCSI/IO-Cards. With all three VLB slots filled, it was some kind of a gamble if the system was stable, even with 40MHz :-/ VLB was very card-dependant.

Tomas Slavotinek schrieb am Donnerstag, 20. April 2023 um 16:20:17 UTC+2:

On 20.04.2023 3:13, Louis Ohland wrote:

The number of slots also decreases with increased speed. IIRC, you could only use one slot at 50MHz.

Tomas Slavotinek wrote:

hence the limitation to 3 or less slots).

That's correct. At 50 MHz you were lucky if it even worked in the single-slot configuration. The CPU bus was never designed for something
like this...

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I'm a bit off here, sorry. The question I now have in mind is: is SCSI between CPU and MCA better than SCSI on MCA, nicely packed between all other MCA-devices, on one bus? I mean, local bus operations should impact MCA transactions and vice versa,
probably affecting the overall performance Oo

schimmi schrieb am Donnerstag, 20. April 2023 um 22:05:21 UTC+2:

Guess there was only one CPU made for this - the DX50. On my old 486/VLB setup I always had problems even with 40MHz/VLB using more than just the graphics adapter. On a 3-slot VLB Board you had one busmastering and accordingly 2 secondary slots you had

to address using more than one card, especially with a SCSI/IO-Cards. With all three VLB slots filled, it was some kind of a gamble if the system was stable, even with 40MHz :-/ VLB was very card-dependant.

Tomas Slavotinek schrieb am Donnerstag, 20. April 2023 um 16:20:17 UTC+2:

On 20.04.2023 3:13, Louis Ohland wrote:

The number of slots also decreases with increased speed. IIRC, you could only use one slot at 50MHz.

Tomas Slavotinek wrote:

hence the limitation to 3 or less slots).

That's correct. At 50 MHz you were lucky if it even worked in the single-slot configuration. The CPU bus was never designed for something like this...

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Sorry, we don't have a full busmaster local bus implementation to
compare to. The 56 SCS is a cost reduced implementation, at some point,
the CPU has to step in to emulate the missing functionality.

So trying to compare a true SCSI busmaster, that can perform all SCSI
control tasks without CPU involvement, to a cost reduced single SCSI
chip, is unwarranted.

So, IBM chose to have a reduced functionality SCSI Control Chip on the
CPU local bus, as long as the system isn't heavily multi-tasked, you
probably wouldn't notice the difference.

schimmi wrote:

I'm a bit off here, sorry. The question I now have in mind is: is SCSI between CPU and MCA better than SCSI on MCA, nicely packed between all other MCA-devices, on one bus? I mean, local bus operations should impact MCA transactions and vice versa,

probably affecting the overall performance Oo

schimmi schrieb am Donnerstag, 20. April 2023 um 22:05:21 UTC+2:

Guess there was only one CPU made for this - the DX50. On my old 486/VLB setup I always had problems even with 40MHz/VLB using more than just the graphics adapter. On a 3-slot VLB Board you had one busmastering and accordingly 2 secondary slots you

had to address using more than one card, especially with a SCSI/IO-Cards. With all three VLB slots filled, it was some kind of a gamble if the system was stable, even with 40MHz :-/ VLB was very card-dependant.

Tomas Slavotinek schrieb am Donnerstag, 20. April 2023 um 16:20:17 UTC+2: >>> On 20.04.2023 3:13, Louis Ohland wrote:

The number of slots also decreases with increased speed. IIRC, you could >>>> only use one slot at 50MHz.

Tomas Slavotinek wrote:

hence the limitation to 3 or less slots).

That's correct. At 50 MHz you were lucky if it even worked in the
single-slot configuration. The CPU bus was never designed for something
like this...

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Hm, makes sense. Guess i try disabling the onboard SCSI and use a MCA SCSI card instead. I really want to know if there is a significant delta in overall performance, reducing the local bus usage. :]

Louis Ohland schrieb am Freitag, 21. April 2023 um 00:36:50 UTC+2:

Sorry, we don't have a full busmaster local bus implementation to
compare to. The 56 SCS is a cost reduced implementation, at some point,
the CPU has to step in to emulate the missing functionality.

So trying to compare a true SCSI busmaster, that can perform all SCSI control tasks without CPU involvement, to a cost reduced single SCSI
chip, is unwarranted.

So, IBM chose to have a reduced functionality SCSI Control Chip on the
CPU local bus, as long as the system isn't heavily multi-tasked, you probably wouldn't notice the difference.
schimmi wrote:

I'm a bit off here, sorry. The question I now have in mind is: is SCSI between CPU and MCA better than SCSI on MCA, nicely packed between all other MCA-devices, on one bus? I mean, local bus operations should impact MCA transactions and vice versa,

probably affecting the overall performance Oo

schimmi schrieb am Donnerstag, 20. April 2023 um 22:05:21 UTC+2:

Guess there was only one CPU made for this - the DX50. On my old 486/VLB setup I always had problems even with 40MHz/VLB using more than just the graphics adapter. On a 3-slot VLB Board you had one busmastering and accordingly 2 secondary slots you

had to address using more than one card, especially with a SCSI/IO-Cards. With all three VLB slots filled, it was some kind of a gamble if the system was stable, even with 40MHz :-/ VLB was very card-dependant.

Tomas Slavotinek schrieb am Donnerstag, 20. April 2023 um 16:20:17 UTC+2: >>> On 20.04.2023 3:13, Louis Ohland wrote:

The number of slots also decreases with increased speed. IIRC, you could
only use one slot at 50MHz.

Tomas Slavotinek wrote:

hence the limitation to 3 or less slots).

That's correct. At 50 MHz you were lucky if it even worked in the
single-slot configuration. The CPU bus was never designed for something >>> like this...

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I have the popcorn ready. Show us how to git 'r dun!

schimmi wrote:

disabling the onboard SCSI

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