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More of my philosophy about SiFive P550 with RISC-V CPU and more..
From
Amine Moulay Ramdane
@21:1/5 to
All
on Fri Sep 10 10:44:18 2021
Hello,
More of my philosophy about SiFive P550 with RISC-V CPU and more..
I invite you to read the following interesting news that says
that Intel is Looking to Acquire SiFive for $2B:
https://www.eetasia.com/intel-looking-to-acquire-sifive-for-2b/
Since i think that Intel also wants to acquire SiFive since it wants
to dominate in the smartphone market since SiFive CEO predicts RISC-V smartphones, servers within five years, read it here:
https://bit-tech.net/news/tech/cpus/sifive-ceo-predicts-risc-v-smartphones-servers-within-five-years/1/
RISC-V also has a weak memory ordering by default, with TSO (like x86) as an optional feature.
You can notice it here on the wikipedia:
https://en.wikipedia.org/wiki/Memory_ordering
So i think all my software products that are compatible with x86 TSO hardware memory model will be compatible with RISC-V TSO hardware memory model.
And read the the following news so that to notice that SiFive P550 with RISC-V is superior in performance to ARM Cortex-A75:
https://arstechnica.com/gadgets/2021/06/sifives-brand-new-p550-is-one-of-the-worlds-fastest-risc-v-cpus/
And read the following:
Intel to Create RISC-V Development Platform with SiFive P550 Cores on 7nm in 2022
https://www.anandtech.com/show/16780/intel-to-create-riscv-development-platform-with-sifive-p550-cores-on-7nm-in-2022
Thank you,
Amine Moulay Ramdane.
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