On 10/22/21 6:41 AM, sven wrote:
So I think it is not unusual if I see CS# pulses without a RD#.
I changed the logic which creates the CS# signal to the WD2797 so there are no 'glitches' on the CS# signal anymore and now there are no missing
data bytes.
That seems odd as the data sheet gives a setup time for CS to RD or WR
which certainly implies that CS changing state without a read or write
strobe shouldn't cause any trouble. If CS is changing within the 50ns
setup time, then all bets are off.
I have never used it with DMA but that shouldn't make much difference
since the response to a DMA request is just an I/O cycle. I looked at my
old BIOS code and it didn't help much. The data transfer loop checks DRQ
and INTRQ (those pins are routed to tristate buffers).
It has been a while since I looked at this code...
rloop:
btst #6,(a2)
bne rdone
btst #7,(a2)
beq rloop
move.b ddata(a2),(a1)+
bra rloop
rdone:
bsr rstatus
move.w imsave,sr * re-enable interupts
tst.b d0
bne rerror
rstatus:
move.b dstat(a2),d0 * read status
and.w #$9d,d0 * set condition codes
rts
The transfer loop checks the DRQ and INTRQ pins.
The error check masks out the DRQ bit so I wouldn't have seen that
problem. Perhaps I had a DRQ problem but if so it has been far too many
years ago for me to remember it. :-) But no missed data errors as that
bit is checked. There is a retry on error but transfers were not slowed
down enough to make a problem apparent.
(This was a Peripheral Technologies FD-2 card grafted into my MEK68KECB system.)
http://davesrocketworks.com
David Schultz
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