• SRAM transistor sizing

    From tomar.bhawna@gmail.com@21:1/5 to All on Fri May 27 06:40:49 2016
    Thanks for giving so much insight everyone!

    I am bit confused for the read margin definition by Mark Johnson

    Define a quantity called ReadMargin. ReadMargin is
    (bitline voltage during a read) minus (cell trip
    point). Suppose you've read a cell containing a
    zero, and now you read a new cell (you assert a new
    wordline) that contains a one. You don't want the
    previous read data on the bitlines, to write the
    new cell. So you want the bitline-low voltage that
    results from a read, to be comfortably above the
    cell trip point.

    After the first read cycle on say WL1 - BL swing to Low value. We must be precharging the BL to read the second address WLn.
    If we are considering the precharge was inadequate or If there is failure to precharge in between successive read 0's on it will keep lowering the voltage of BL. This would not work.

    So what is the significance of such Read margin definition?
    Please clarify.

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  • From nainasinghal1234@gmail.com@21:1/5 to Aditya Agrawal on Sun Sep 10 23:42:43 2017
    On Monday, July 24, 1995 at 12:30:00 PM UTC+5:30, Aditya Agrawal wrote:
    What are the criteria that one should use when sizing transistors
    in a simple CMOS 6-transistor/cell SRAM ?

    SPecifically, I have seen SRAM cells designed by other people
    with the size of the P pullup in the ramcell as WP=2.0,LP=3.7
    in a 1.0um technology. I would have thought that LP should
    have been 1.0um to keep the size of the ramcell as small as

    Also, how can we figure out what size the row select and
    column select transistors need to be for a particular sized
    RAM for optimal area ?

    I would appreciate any information on this.


    I am designing a SRAM for my project
    For a single 6T cell, during reading how to store data bit in cell so that we can read it. Should i push data externally using a supply to read it?
    I am having trouble in understanding reading and writing cycle of SRAM using cadence virtuso.


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