Define a quantity called ReadMargin. ReadMargin is
(bitline voltage during a read) minus (cell trip
point). Suppose you've read a cell containing a
zero, and now you read a new cell (you assert a new
wordline) that contains a one. You don't want the
previous read data on the bitlines, to write the
new cell. So you want the bitline-low voltage that
results from a read, to be comfortably above the
cell trip point.
What are the criteria that one should use when sizing transistors
in a simple CMOS 6-transistor/cell SRAM ?
SPecifically, I have seen SRAM cells designed by other people
with the size of the P pullup in the ramcell as WP=2.0,LP=3.7
in a 1.0um technology. I would have thought that LP should
have been 1.0um to keep the size of the ramcell as small as
Also, how can we figure out what size the row select and
column select transistors need to be for a particular sized
RAM for optimal area ?
I would appreciate any information on this.
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