AFAIK, the only data which is 16 bits wide is audio quality CD, so my focus is now on an audio processor
for musicians, hearing aids, and echolocation.
Thanks to all of you, my understanding of the technology and the market continues to improve. 16 bit Forth machines are very space and memory efficient, but the problem is that real time control applications use more than 16 bits of accuracy’s andyou really do not want to be doing stack operations on doubles. Dup is two deep, Over is 4 deep, but rot is 6 deep. Sure at 60Mhz there is enough time, but it is just ugly. So I need an application which uses 16 bit data or less.
AFAIK, the only data which is 16 bits wide is audio quality CD, so my focus is now on an audio processor for musicians, hearing aids, and echolocation. There are a lot of older Forth developers who need hearing aids, and in the US, they are no longerregulated. Here is the $35 board I am targeting.
https://tinyvision.ai/products/pico-ice
This board, can happily fit 8 * 16 bit stack machines.
Each will have a hard core multiplier and 128Kbits of memory. That is 8K 16bit words. If needed, I can even go t0 16 processors, 8 with hard core multipliers.
This processor will be very different from the J1 and Mecrisp processors. They are optimized to be as small as possible, with only 16 instructions. Each one only takes 160 LUT’s, but I have 5260 LUTs on this board. With all of that logic fabric, Ican happily have 32 instructions instead of the J1’s 16. That makes this closer to Ting’s eForth EP16/24/32. Of course Ting had 3 different code bases, but with modern tools like Python’s Amaranth, or Java’s SpinalHDL, I should be able to
The J1 depends on dual port memory. It can read or write to memory at the same time that it is fetching the next instruction. And one needs that to be able to edit code. Sadly the inexpensive Lattice boards are mostly single port memory. So I have touse a Harvard architecture, where code and memory are separate. MicroCore does this. I suspect Ting also did this.
I will also need some logic dedicated to audio processing. I am not yet sure what it will be. There may need to be a shift register to store some history from two or three microphones for cross-correlation and edge detection. There may need to be someflags for when the next bit of audio becomes available.
So I see a family of many core eForth CPU’s, all in Amaranth, taking the best ideas from many of the existing Forth cpus. Initially my focus will be on 16 bits for audio, later on 24 bits for video. If someone actually needs a 32 bit processor, Iwill release that as well.
Particular thanks to @Lorum Ipsum for pointing out that the low end Lattice boards are also low power. Thanks to Juergen Pintaske for connecting me to the Facebook Forth group, and to a real time control expert who pointed out that they need 32 bitdata. Thanks to the the Mecrisp-Ice author for pointing out that the Lattice Ice40 boards are single port. Thanks to the Core-1 lead for all of his great advice. Thanks to the 22 people on Facebook who like this idea, and to the one person who already
Any musician is going to drop a 16 bit device in the trash, because the artifacts will be audible.
The dual port memory is internal to an FPGA and is available in nearly every device that is still in production.
Why am I focused on small, low cost, efficient and many core?
This video from the recent open source conference will explain the issues with climate change, limits to growth and planetary boundaries.
Not quite correct. I am mindful of the climate and planetary boundaries, and that tells me which direction the world is going.Why am I focused on small, low cost, efficient and many core?Ah, so you're fighting the climate and planetary boundaries — and that requires multicore. :) Finally got it.
This video from the recent open source conference will explain the issues with climate change, limits to growth and planetary boundaries.
On Thursday, August 10, 2023 at 12:59:40 PM UTC+2, Zbig wrote:
Not quite correct. I am mindful of the climate and planetary boundaries, and that tells me which direction the world is going.Why am I focused on small, low cost, efficient and many core?Ah, so you're fighting the climate and planetary boundaries — and that requires multicore. :) Finally got it.
This video from the recent open source conference will explain the issues with climate change, limits to growth and planetary boundaries.
My efforts to fight climate change are at the followinglink. You can watch 84 excellent videos about climate change, curated by numerous individuals.
https://uncensorednews.us/climate-change?query=&type=video&recommended=recommended&category=climate-change
The good news is that at least now people know that something is wrong with the climate. Generally, because of censorship, they still do not know how bad it already is, nor how much worse it is about to get.
Lorum Ipsum wrote:
Any musician is going to drop a 16 bit device in the trash, because the artifacts will be audible.Thank you. I will drop music from the target market. Simplifies life.
But digital telephony is at 8 bits, so I should be able to do a hearing aid at 16 bits.
As for echo location, the number of bits is not nearly as important as the timing.
Why am I focused on small, low cost, efficient and many core?
This video from the recent open source conference will explain the issues with climate change, limits to growth and planetary boundaries.
https://peertube.f-si.org/videos/watch/73680ce5-dd9e-483c-b6dd-88abcda548c4 If you understand climate change,, you can skip to 26:30.
And of course FPGA's are just the first step.
I generally think of soft core processors on FPGA's as 10 times slower and 10 times larger than competing hard core cpus. If I have a 16bit soft core, it is half as wide, and half as tall, and so maybe 1/4 the size of a 32 bit soft core cpu, so it isonly 2.5 times larger and slower than a 32 bit hard core cpu. Certainly levels the playing field a lot. A lot easier to be competitive in the market.
Why am I doing stack machines instead of register machines?
Register machines and C compilers are too complex for innovation. The Gnu C compiler is some 16 million lines of code. Impossible to innovate there. Stack machines allow me to do all kinds of interesting and needed things quite quickly and easily.
Why do I want more instructions? My instinct is that the additional 16 instructions that the Ting CPU provides would each take so many clock cycles to implement in the 16 instructions that the J1 provides, that although the ting cpu may half as fast,the application will run twice as fast. Supporting evidence is that the MicroCore with about 86 instructions, the author said he never needed a faster cpu.
Why do I use the term Forth processor? To distinguish it in my mind from a C processor.
The dual port memory is internal to an FPGA and is available in nearly every device that is still in production.Thank you. So I checked again. Turns out we both got it wrong. From the "iCE40 SPRAM Usage Guide"
The iCE40 devices offer four embedded memory blocks of SPRAM(Single Port RAM)....
The iCE40 family has four 256 kb memory blocks available, that is a total of 1024 kb of Single Port memory. Each of these blocks can be configured only in 16K x 16 mode.
So the ICE40 family will not meet my needs for an audio processor. I will need to upgrade to the ECP5 boards. Tons of dual port memory, and more LUTs than I know what to do with. Great! Sadly not low power.
Signal Processing: The architecture’s parallel processing capabilities can be harnessed for real-time signal processing tasks, such as audio and image processing, enabling faster and more accurate results.
Have you looked at Gowin, Efinix, Xilinx(AMD), Altera(Intel)? Gowin and Efinix have good supply and prices.
Yeah, „all people contribute to climate change”Some contribute more than others.
@SpainHackForth, thank you for the list of potential applications. Can you say more about this area which is of particular interest to me.
Signal Processing: The architecture’s parallel processing capabilities can be harnessed for real-time signal processing tasks, such as audio and image processing, enabling faster and more accurate results.
Christopher Lozinski
Well, since it was asked, here are three areas of possible innovation
with a hardware dual-stack CPU (similar to Forth’s design) and their >potential use cases:
- Real-time Systems and Embedded Applications:
**Innovation Area:
* Utilizing the dual-stack architecture for real-time systems and
embedded applications can lead to precise and predictable execution of
tasks, making it suitable for robotics, industrial automation, and
control systems.
** Use Cases;
* Robotics Control- The architecture’s deterministic execution
can ensure accurate control of robotic movements, enhancing safety and >efficiency in tasks like manufacturing, assembly, and exploration.
* Industrial Automation- Dual-stack CPUs can power real-time automation
systems, controlling processes with precise timing and responsiveness in >industries such as manufacturing and logistics.
* IoT Devices- In IoT applications, the architecture can enable
real-time monitoring and control of smart devices, ensuring rapid
response to events and minimizing latency.
- Secure and Reliable Systems.
** Innovation Area:
* Leveraging the dual-stack architecture for secure and reliable
systems can enhance software resilience, isolate critical components,
and provide a strong foundation for secure computing environments.
** Use Cases:
* Cybersecurity: Dual-stack CPUs can facilitate secure booting, code
integrity checks, and cryptographic operations. These features enhance
system security, protect sensitive data, and defend against cyber
threats.
* Safety-Critical Systems: The architecture’s isolation of control
flow and data can be critical in safety-critical applications such as >aerospace, automotive, and medical devices, minimizing the risk of
software failures.
* Secure Transactions: For finncial and transactional systems, the
dual-stack architecture can support secure execution of encryption
algorithms and authentication protocols, safeguarding sensitive
transactions.
- Advanced Algorithm Development.
** Innovation Area:
* The dual-stack architecture can inspire the development of
novel algorithms and data structures that leverage the separation of
data and control stacks, leading to improved computational efficiency
and performance.
** Use Cases:
* Data Analytics: Developing algorithmsn for data processing, analysis,
and transformation can benefit from the architecture’s ability to
manage data separately from control flow, leading to optimized
data-driven insights.
* Signal Processing: The architecture’s parallel processing
capabilities can be harnessed for real-time signal processing tasks,
such as audio and image processing, enabling faster and more accurate >results.
*Scientific Computing: Dual-stack CPUs can accelerate complex
scientific simulations by optimizing data manipulation and parallel >computations, advancing research in various domains.
Personally, I believe that a hardware dual-stack CPU architecture,
resembling Forth’s design, can drive many areas of innovation. The >architecture’s predictable execution, separation of stacks, and
parallel processing capabilities offer opportunities to create efficient
and reliable solutions for various industries and applications.
Cheers and I look forward to positive contribution from all in the community.
JoseM--
In article <d617ced0-7d37-4967...@googlegroups.com>,
SpainHackForth <jem...@gmail.com> wrote:
Well, since it was asked, here are three areas of possible innovation
with a hardware dual-stack CPU (similar to Forth’s design) and their >potential use cases:
- Real-time Systems and Embedded Applications:
**Innovation Area:
* Utilizing the dual-stack architecture for real-time systems and
embedded applications can lead to precise and predictable execution of >tasks, making it suitable for robotics, industrial automation, and
control systems.
** Use Cases;
* Robotics Control- The architecture’s deterministic execution
can ensure accurate control of robotic movements, enhancing safety and >efficiency in tasks like manufacturing, assembly, and exploration.
* Industrial Automation- Dual-stack CPUs can power real-time automation
systems, controlling processes with precise timing and responsiveness in >industries such as manufacturing and logistics.
* IoT Devices- In IoT applications, the architecture can enable
real-time monitoring and control of smart devices, ensuring rapid
response to events and minimizing latency.
- Secure and Reliable Systems.
** Innovation Area:
* Leveraging the dual-stack architecture for secure and reliable
systems can enhance software resilience, isolate critical components,
and provide a strong foundation for secure computing environments.
** Use Cases:
* Cybersecurity: Dual-stack CPUs can facilitate secure booting, code
integrity checks, and cryptographic operations. These features enhance >system security, protect sensitive data, and defend against cyber
threats.
* Safety-Critical Systems: The architecture’s isolation of control
flow and data can be critical in safety-critical applications such as >aerospace, automotive, and medical devices, minimizing the risk of >software failures.
* Secure Transactions: For finncial and transactional systems, the
dual-stack architecture can support secure execution of encryption >algorithms and authentication protocols, safeguarding sensitive >transactions.
- Advanced Algorithm Development.
** Innovation Area:
* The dual-stack architecture can inspire the development of
novel algorithms and data structures that leverage the separation of
data and control stacks, leading to improved computational efficiency
and performance.
** Use Cases:
* Data Analytics: Developing algorithmsn for data processing, analysis,
and transformation can benefit from the architecture’s ability to
manage data separately from control flow, leading to optimized
data-driven insights.
* Signal Processing: The architecture’s parallel processing
capabilities can be harnessed for real-time signal processing tasks,
such as audio and image processing, enabling faster and more accurate >results.
*Scientific Computing: Dual-stack CPUs can accelerate complex
scientific simulations by optimizing data manipulation and parallel >computations, advancing research in various domains.
Personally, I believe that a hardware dual-stack CPU architecture, >resembling Forth’s design, can drive many areas of innovation. The >architecture’s predictable execution, separation of stacks, and
parallel processing capabilities offer opportunities to create efficient >and reliable solutions for various industries and applications.
Cheers and I look forward to positive contribution from all in the community.I have the suspicion that post was generated by AI.
The content is reminiscient of China's "People Review" in the 60's. Basically devoid of content.
JoseM--
Don't praise the day before the evening. One swallow doesn't make spring. You must not say "hey" before you have crossed the bridge. Don't sell the hide of the bear until you shot it. Better one bird in the hand than ten in the air. First gain is a cat spinning. - the Wise from Antrim -
Thanks to all of you, my understanding of the technology and the market continues to improve. 16 bit Forth machines are very space and memory efficient, but the problem is that real time control applications use more than 16 bits of accuracy’s andyou really do not want to be doing stack operations on doubles. Dup is two deep, Over is 4 deep, but rot is 6 deep. Sure at 60Mhz there is enough time, but it is just ugly. So I need an application which uses 16 bit data or less. AFAIK, the only data
https://tinyvision.ai/products/pico-icecan happily have 32 instructions instead of the J1’s 16. That makes this closer to Ting’s eForth EP16/24/32. Of course Ting had 3 different code bases, but with modern tools like Python’s Amaranth, or Java’s SpinalHDL, I should be able to
This board, can happily fit 8 * 16 bit stack machines.
Each will have a hard core multiplier and 128Kbits of memory. That is 8K 16bit words. If needed, I can even go t0 16 processors, 8 with hard core multipliers.
This processor will be very different from the J1 and Mecrisp processors. They are optimized to be as small as possible, with only 16 instructions. Each one only takes 160 LUT’s, but I have 5260 LUTs on this board. With all of that logic fabric, I
The J1 depends on dual port memory. It can read or write to memory at the same time that it is fetching the next instruction. And one needs that to be able to edit code. Sadly the inexpensive Lattice boards are mostly single port memory. So I have touse a Harvard architecture, where code and memory are separate. MicroCore does this. I suspect Ting also did this.
I will also need some logic dedicated to audio processing. I am not yet sure what it will be. There may need to be a shift register to store some history from two or three microphones for cross-correlation and edge detection. There may need to be someflags for when the next bit of audio becomes available.
So I see a family of many core eForth CPU’s, all in Amaranth, taking the best ideas from many of the existing Forth cpus. Initially my focus will be on 16 bits for audio, later on 24 bits for video. If someone actually needs a 32 bit processor, Iwill release that as well.
Particular thanks to @Lorum Ipsum for pointing out that the low end Lattice boards are also low power. Thanks to Juergen Pintaske for connecting me to the Facebook Forth group, and to a real time control expert who pointed out that they need 32 bitdata. Thanks to the the Mecrisp-Ice author for pointing out that the Lattice Ice40 boards are single port. Thanks to the Core-1 lead for all of his great advice. Thanks to the 22 people on Facebook who like this idea, and to the one person who already
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