Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.
Christopher Lozinski
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.
Christopher Lozinski
On Wednesday, 2 August 2023 at 07:31:00 UTC+1, Christopher Lozinski wrote:
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.Thank you very much for sharing your presentation.
Christopher Lozinski
The first reactions I had:
Can you please add Bernd Paysans b16
https://bernd-paysan.de/b16.html
And can you please add a page or 2 with links, so people can find the places more easily.
You have done so much work putting it all together - please share the links.
And it might be worth mentioning, that there are (or were)to my knowledge 2 Forth Processors in production/products
the b16
the J1
On Wednesday, 2 August 2023 at 08:19:13 UTC+1, Jurgen Pitaske wrote:
On Wednesday, 2 August 2023 at 07:31:00 UTC+1, Christopher Lozinski wrote:
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.Thank you very much for sharing your presentation.
Christopher Lozinski
The first reactions I had:
Can you please add Bernd Paysans b16
https://bernd-paysan.de/b16.html
And can you please add a page or 2 with links, so people can find the places more easily.
You have done so much work putting it all together - please share the links.
And it might be worth mentioning, that there are (or were)to my knowledge 2 Forth Processors in production/productsAnd please remember the book about Ting's EP32 https://www.amazon.co.uk/EP32-RISC-Processor-Description-Implementation-ebook/dp/B071D3XMPS/ref=sr_1_12?qid=1690962051&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-12
the b16
the J1
And it might be worth mentioning, that there are (or were)to my knowledge
2 Forth Processors in production/products
the b16
the J1
[Hugh] was difficult to work with. ...
I let him go myself...
He had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version [of the MiniForth] was based upon our original Forth Engine done long before we ever ran across Hugh.
Sounds like the Forth community has some problems with non team players.
On Wednesday, August 2, 2023 at 12:19:13 AM UTC-7, Jurgen Pitaske wrote:
And it might be worth mentioning, that there are (or were)to my knowledge 2 Forth Processors in production/productsThe MiniForth processor was used in the motion-control board of the laser-etcher in 1995. In a laser-etcher, the mirrors have to move at a steady
the b16
the J1
speed. They can't have a pause when they change direction because this
will result in a burned blotch at the point where the direction changes.
The speed has to be consistent whether the lines are ziggy or straight.
This requires a very high-speed processor!
The B16, J1, Mecrisp-Ice, BUGS18, RTX-2000, etc. are toy processors
that are not capable of supporting motion-control in the year 2023,
although the MiniForth did this in 1995.
I'm proud of having written MFX the assembler/simulator and Forth cross-compiler for the MiniForth, although Tom Hart and Juergen Pintaske will never admit that I wrote MFX. The liar Tom Hart says: https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0/m/mvVy-GN7AwAJ
[Hugh] was difficult to work with. ...
I let him go myself...
He had nothing to do with the processor itself,
that was all designed by John Hart and Steve Brault.
The PLD version [of the MiniForth] was based upon our original Forth Engine
done long before we ever ran across Hugh.
Tom Hart is not giving me credit for writing MFX that is an integral aspect of the MiniForth (a processor is not worth anything without an assembler). He is not giving me credit for being an assembly-language programmer.
John Hart didn't know how to write the assembler. The advice that he gave
me was useless and really absurd. I doubt that Steve Brault knew how to write
the assembler either --- he was already employed at Testra, so if he knew how
to write the assembler, then why did they need to hire me to do it? --- Steve had
to wait for me to write the assembler before he could begin porting his motion-control program (I remember that he was quite impatient waiting).
I figured out how to do the out-of-ordering of the instructions myself.
Sounds like the Forth community has some problems with non team players.
The problem with the Forth community is not a lack of team players.
Juergen Pintaske is the most loyal team player than any big boss could possibly hope for --- Stephen Pelc will certainly vouch for this statement! The problem with the Forth community is too many liars --- and too many brown-nosers who support the leadership unquestioningly.
Which team does Tom Hart think lacks team players?
Obviously, he is referring to the Forth-200x committee!
I think that, with his nasty email attacking me, Tom Hart was brown-nosing Stephen Pelc in the hopes of getting appointed to the Forth-200x committee so he could be a big leader too (the whole point of joining a team
is to quickly get promoted into leadership).
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.
Christopher Lozinski
One of the issues with such presentations using viewgraphs (sorry for the ancient terminology) is when they are so terse, they >themselves contain virtually no information. Some of yours are like that. Brevity is good, but at some point you need tohave them >convey some information, without the presentation. I like to use them as review material after I've heard such a presentation..
Without a >bit more info, they aren't much good for that.
On Thursday, August 3, 2023 at 5:59:42 AM UTC-4, Lorem Ipsum wrote:have them >convey some information, without the presentation. I like to use them as review material after I've heard such a presentation..
One of the issues with such presentations using viewgraphs (sorry for the ancient terminology) is when they are so terse, they >themselves contain virtually no information. Some of yours are like that. Brevity is good, but at some point you need to
Without a >bit more info, they aren't much good for that.On the other hand using a "power point" style slide show is not the message. The presenter conveys the message. Slides are for support.
I have too often had junior people try to take me threw "wall of text" slide shows.
My opinion is a separate handout document with the detail is better than putting it on the screen.
I took a course from an company called Black Isle where they want a cover slide on the screen
while you are speaking. Then the presenter says "Here is an example of what I am talking about" or
some such line and then says nothing while the slide is being read by the audience.
After a proper time, the slide comes down and the speaker resumes.
Theory being that we cannot read a slide and hear a speech at the same time.
It's very effective when done well, but it drove our CMO nuts when I did it because he
wanted to read ahead. :-)
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.
Christopher Lozinski
On Wednesday, 2 August 2023 at 07:31:00 UTC+1, Christopher Lozinski wrote:
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.I have reposted it in the Forth facebook group,
Christopher Lozinski
and people can send you an email
as well as you have your email address in your presentation lozi...@PythonLinks.info <lozi...@PythonLinks.info>;
Thank you for the feedback.
I was just doing this for my own education.
I had not realized that this document would be more widely useful.
I will go ahead and incorporate your suggestions, and repost it.
I think that you are quite right, that the slides do not stand alone.
But then the video takes too long to watch.
I should draft a script on Google Docs, and allow people to edit it.
I am sure that some of my beliefs are incorrect, or incomplete.
And many links are included,
most of the titles are actually hyperlinked,
but since there is no underlining you cannot tell. I will also fix that.
Warm Regards
Christopher Lozinski
On Wednesday, 2 August 2023 at 07:31:00 UTC+1, Christopher Lozinski wrote:
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.
Christopher Lozinski
I have reposted it in the Forth facebook group,
and people can send you an email
as well as you have your email address in your presentation lozi...@PythonLinks.info <lozi...@PythonLinks.info>;
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September.
Your expert comments would be most appreciated.
The general plan is to build large numbers of MeCrips cores on an FPGA.
On Friday, 4 August 2023 at 07:39:35 UTC+1, Jurgen Pitaske wrote:be of great interest, Ilya Tarasov (sorry for the spelling if I goofed that) who had a well advanced Forth FPGA CPU, might we well worth the trouble to add it to the presentation.
On Wednesday, 2 August 2023 at 07:31:00 UTC+1, Christopher Lozinski wrote:
Here are the slides for my upcoming talk "A Review of Soft Core Forth Processors".
https://pythonlinks.info/presentations/ForthPresentation.pdf
I will be giving the talk at the August SVFIG meetup, and at the Stocklolm FPGA World conference in September. Your expert comments would be most appreciated.
For those who do not like the term "Forth Processor", I define it as a stack machine running programs written in Forth.
The general plan is to build large numbers of MeCrips cores on an FPGA. A future posting will discuss the details.
Thank you for all the advice I have received here so far.
Christopher Lozinski
I have reposted it in the Forth facebook group,A first feedback on facebook:
and people can send you an email
as well as you have your email address in your presentation lozi...@PythonLinks.info <lozi...@PythonLinks.info>;
Jose Morales
Here is a 'NEW WIP Forth CPU" https://github.com/jemo07/MyFPGA_FORTH, I would not add it to the list, just saying there is great deal of interest ( IMO ) of this subject, so looking forward to more details of the talk. There is a one missing that might
Here are some areas where I believe the presentation could provide more details on the Forth CPU's with some of the questions that would otherwise be answer in such a subject.
Architecture and Design
What is the architecture of the Soft Forth CPU? How does it differ from traditional CPU architectures?
Why choose a stack-based architecture? What are the advantages and disadvantages?
How is the instruction set designed? What considerations were made in selecting specific instructions?
Implementation Details
How is the Soft Forth CPU implemented on an FPGA? What are the specific Verilog or VHDL constructs used?
What are the optimization strategies employed? How are resources like gates, memory, and clock cycles optimized?
How is the stack implemented and managed? What are the mechanisms for stack overflow and underflow handling?
Performance and Benchmarking
How does the Soft Forth CPU perform compared to other soft CPUs or traditional hardware CPUs?
What are the benchmarks used to evaluate performance? How does it perform in terms of speed, resource utilization, power consumption, etc.?
Applications and Use Cases
What are the specific applications or domains where a Soft Forth CPU would be particularly beneficial?
How can the Soft Forth CPU be integrated into existing systems or workflows? Challenges and Limitations
What are the challenges faced in designing and implementing a Soft Forth CPU?
What are the current limitations, and how might they be overcome in future iterations or versions?
Future Directions and Research
What are the future directions for Soft Forth CPUs? Are there new features, optimizations, or applications on the horizon?
How does the Soft Forth CPU fit into the broader landscape of research and development in soft CPUs and FPGA technology?
https://github.com/jemo07/MyFPGA_FORTH?fbclid=IwAR25E36dumZPqnrIrypOstcKqS8kdRoQJBVnrjWkSf_GOSjuWQgUGfa_aRg
you look like a sales clown.I agree with you that there is no money to be made with Forth cores, but there is tremendous knowledge to be acquired by presenting things. And better yet, connection with some very interesting people. Humans are a social species. We share knowledge.
The feedback I have received from posting the slides has been fantastic. They include links to the source code on how the GA144 nodes communicate, detailed documentation on how the transputer worked, and lots of other great advice. It is only byyou look like a sales clown.I agree with you that there is no money to be made with Forth cores, but there is tremendous knowledge to be acquired by presenting things. And better yet, connection with some very interesting people. Humans are a social species. We share knowledge.
In the private discussions following posting, I realized that Video processing is a bad target market. the Low cost FPGA's are just not large enough.bothered you with the presentation. Did you want it to be more technical??? Was it something else?
640 x 480 pixels x 24 bits/pixel = 7372800 bits.
The Lattice ECP5 family has at most 3.7 Mbits of RAM.
I also learned that human sound localization is way more complicated than I had realized.
https://en.wikipedia.org/wiki/Sound_localization#:~:text=Localization%20accuracy%20is%201%20degree,of%2010%20microseconds%20or%20less
Multiple Forth cores for hearing aids will just have to wait a while.
And I did learn of a great market for a six core Forth CPU, but that will be the topic of another thread.
There is an old saying: "Be hard on issues, soft on people." When. you criticized me as a sales clown, I completely missed what is your concern with the presentation. So I did not learn anything from your email. What was the specific issue that
you look like a sales clown.I agree with you that there is no money to be made with Forth cores
there is tremendous knowledge to be acquired by presenting things.
The feedback I have received from posting the slides has been fantastic.
On Tuesday, August 8, 2023 at 2:18:10 AM UTC-7, Christopher Lozinski wrote:
I didn't say that no money can be made with Forth cores.you look like a sales clown.I agree with you that there is no money to be made with Forth cores
I said that no selling internet freebies doesn't provide a commission.
Forth cores can be worth money if they are competitive in the real world.
Testra has been in business since 1995 thanks to the MiniForth
(later the RACE) Forth cores. Testra was on the verge of going
out of business in 1994 because their Dallas 80c320 motion-control
board wasn't competitive with the competition that was using an
MC68000 programmed in C --- the MiniForth board (based on the
Lattice isp1048 PLD) was less expensive than the MC68000 board
and out-performed it. This is the only case that I'm aware of in which
Forth did beat C in both price and performance. I made my MFX assembly-language as easy to use as possible (the out-of-ordering
was done by the assembler, so the programmer could write his
assembly source-code as if the instructions executed sequentially).
Despite making MFX assembly-language as easy as possible, I would
still estimate the difficulty of MFX assembly-language to be about
an order of magnitude above MC68000 assembly-language.
For one thing, the MiniForth didn't have an ALU so there was
no instruction to do integer addition. For another thing, there was
no way to change the PC (no branch or jump instructions)
other than the NXT instruction at the end of the primitives (it was
possible to conditionally load the IP register inside of the primitive).
With processors, you get high-performance, low cost and easy programming. Pick any two!
there is tremendous knowledge to be acquired by presenting things.There isn't any knowledge to be acquired by presenting things.
Educating the world on a subject that you have superficial knowledge of
is the path of the fool.
The feedback I have received from posting the slides has been fantastic.When you try to present information using light-weight media such as
a slide show, technical people will run away.
You end up getting fantastic feedback from non-technical people such as Juergen Pintaske. He's a pig! Tom Hart totally disgraced himself by accepting Juergen Pintaske as his peer --- I recommend against doing this.
Thank you for all of the feedback. Much of it was included. Here is the new version.
https://pythonlinks.info/presentations/ForthPresentation.pdf
On page 4, I talk about the main application for Forth Processors. "System within a chip"
On page 13, I am now able to classify the different processors based on what their design goals and constraints were. It makes it much easier to choose the right processor for an application.
On pages 29-33 I talk about my plans. 1 core, 8 core and 10 core processors. Hearing aids , and FFT's.
Hyperlinks are underlined.
The GA144 was not included because it is not a soft core processor. Multiple requests for them to make it available as a soft core processor have been rejected.
Processors I had never heard about were not included.
People who were rude, got their comments ignored.
Additional comments are welcome. I will present at SVFIG later this month.
Thank you for all of the help.
Christopher Lozinski
On Sunday, 20 August 2023 at 11:29:28 UTC+1, Christopher Lozinski wrote:
Thank you for all of the feedback. Much of it was included. Here is the new version.
https://pythonlinks.info/presentations/ForthPresentation.pdf
On page 4, I talk about the main application for Forth Processors. "System within a chip"
On page 13, I am now able to classify the different processors based on what their design goals and constraints were. It makes it much easier to choose the right processor for an application.
On pages 29-33 I talk about my plans. 1 core, 8 core and 10 core processors. Hearing aids , and FFT's.
Hyperlinks are underlined.
The GA144 was not included because it is not a soft core processor. Multiple requests for them to make it available as a soft core processor have been rejected.
Processors I had never heard about were not included.
People who were rude, got their comments ignored.
Additional comments are welcome. I will present at SVFIG later this month.
Thank you for all of the help.Quite a few nice changes.
Christopher Lozinski
Just a quick point: it is b16 not B1
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