Microcore.GoLang uses CSP. So here is what the Microcore has to say about pauses.
https://github.com/microCore-VHDL/microCore
Hardware pauses are how the Transputer managed Communicaing Sequential Processes (CSP). Ask to receive a message, if it was not there, the process would pause, an interrupt would call some microcode, which would allow another process to run. And now
Interupt: An event which happened which was not expected by the application.Googling for "forth multitasking" returns this at the top: https://www.bradrodriguez.com/papers/mtasking.html
Pause: An event which did not happen, which was expected by the application.
You can read more here: Scroll down to section six, or search for "pause". https://github.com/microCore-VHDL/microCore/blob/master/documents/uCore_overview.pdf
His CPU was recommended to me by Jim Brake. https://github.com/jimbrake/cpu_soft_cores
Who was recommended to me by Lorum Ipsum.
So what do you think of pausing?
Are there any other Forth CPU's with pause functionality?
Thank you everyone. None of the faculty at my University seem to know anything about Forth.
Chris
Microcore.GoLang uses CSP. So here is what the Microcore has to say about pauses.
https://github.com/microCore-VHDL/microCore
Hardware pauses are how the Transputer managed Communicaing Sequential Processes (CSP). Ask to receive a message, if it was not there, the process would pause, an interrupt would call some microcode, which would allow another process to run. And now
Interupt: An event which happened which was not expected by the application.
Pause: An event which did not happen, which was expected by the application.
You can read more here: Scroll down to section six, or search for "pause". https://github.com/microCore-VHDL/microCore/blob/master/documents/uCore_overview.pdf
His CPU was recommended to me by Jim Brake. https://github.com/jimbrake/cpu_soft_cores
Who was recommended to me by Lorum Ipsum.
So what do you think of pausing?
Are there any other Forth CPU's with pause functionality?
Thank you everyone. None of the faculty at my University seem to know anything about Forth.
Chris
On Saturday, April 8, 2023 at 7:42:29 AM UTC-7, Christopher Lozinski wrote:GoLang uses CSP. So here is what the Microcore has to say about pauses.
Microcore.
https://github.com/microCore-VHDL/microCore
Hardware pauses are how the Transputer managed Communicaing Sequential Processes (CSP). Ask to receive a message, if it was not there, the process would pause, an interrupt would call some microcode, which would allow another process to run. And now
REPEAT.Interupt: An event which happened which was not expected by the application.
Pause: An event which did not happen, which was expected by the application.
You can read more here: Scroll down to section six, or search for "pause". https://github.com/microCore-VHDL/microCore/blob/master/documents/uCore_overview.pdf
His CPU was recommended to me by Jim Brake. https://github.com/jimbrake/cpu_soft_cores
Who was recommended to me by Lorum Ipsum.
So what do you think of pausing?Googling for "forth multitasking" returns this at the top: https://www.bradrodriguez.com/papers/mtasking.html
Are there any other Forth CPU's with pause functionality?
Thank you everyone. None of the faculty at my University seem to know anything about Forth.
Chris
PAUSE is Forth's multitasking word. If hardware is busy, pass control to the next task in a round-robin queue. uCore's Pause uses hardware to execute a trap, which could execute PAUSE instead of explicitly coding something like BEGIN TEST WHILE PAUSE
Since you are investing your time in multi-processor designs, it seems to me a more valuable topic would be on-chip networking. NOCs have not had the scrutiny that ISAs have so the field has much room for growth. The low performance of on-chip networkscauses applications to favor single-core or few-core platforms, so NOCs are a scalability bottleneck. If apps had more flexible networks, they could exploit more cores.
Also, RISC V is "the thing" now. If you are implementing anything else, you should have a very good reason. Even if you do, you would want your multi-core chip to support the inclusion of RISC V. Oddball cores like Forth processors would be add-ons.That makes the NOC infrastructure the first thing to look at, not the particular CPU design.
Sorry if I got Jim Brakefield's name wrong. I just took it from the name of the repository.is not ready, the peripheral issues a pause, the pauses are ORed together, the instruction is aborted and a pause instruction is put on the stack. In contrast, Forth and most of the software world will read a semaphore, and then proceed or pause
So I think that there is a HUGE difference between how the Microcore does Pause, and how most Forths do pause. The Microcore does not have semaphores. Instead each peripheral can raise a pause exception. If the cpu tries to access a peripheral which
if you only occasionally access shared resources, no one cares. But if you frequently access shared resources, then this would be a lot faster. As for on chip networking. I totally agree that is a critical area. I have no idea how it should bedone. What do you recommend? KISS They actually have a course here about on-chip networking.
Why not Risc v? It is not easily accessible. Have you seen how complex the c++ language and compiler are? Forth is so much simpler. I can much more easily do whatever I want. A lot more fun.
The power of a CPU comes from the huge multiplexer in the program memory, allowing very complex logic to be implemented sequentially, rather than in parallel.
I'm not at all clear on what your goals are, what the purpose of this effort is.
PAUSE is Forth's multitasking word. If hardware is busy, pass control to the next task in a round-robin queue. uCore's Pause uses hardware to execute a trap,
which could execute PAUSE instead of explicitly coding something like BEGIN TEST WHILE PAUSE REPEAT.
Also, RISC V is "the thing" now. If you are implementing anything else, you should have a very good reason. Even if you do, you would want your multi-core
chip to support the inclusion of RISC V. Oddball cores like Forth processors would be add-ons. That makes the NOC infrastructure the first thing to look at,
not the particular CPU design.
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