Riscv is in the long run to obliterate Intel AMD and ARM, because
it is royalty free, such that Chinese companies can no longer be
strong armed. The smaller ARM royalties has had already an impact.
Riscv is in the long run to obliterate Intel AMD and ARM, because
it is royalty free, such that Chinese companies can no longer be
strong armed. The smaller ARM royalties has had already an impact.
Competition is good. At the moment RISC V boards still are expensive
compared to ARM-based ones.
Riscv is in the long run to obliterate Intel AMD and ARM, becauseCompetition is good. At the moment RISC V boards still are expensive
it is royalty free, such that Chinese companies can no longer be
strong armed. The smaller ARM royalties has had already an impact.
compared to ARM-based ones.
The board I have costs 17 dollars plus shipping. 64 bit 1 Ghz.
Not an expensive hobby.
Brian Fox <bria...@brianfox.ca> writes:
I read an article by Sam Falvo on trying to make machine Forth forRISC-V and ARM A64 (aka Aarch64) are both RISCs in my book (they are load/store architectures), but follow quite different design
RISC V and the instruction set seemed to require a lot of
instructions per Forth primitive. Is that the "state of the art" for >"risc".
philosophies.
ARM A64 has 32-bit wide instructions and puts as much functionality in
as fits and fits the basic RISC principles, sometimes crossing the
border. It does not try for minimal implementation, ARM has another instruction set (T32/A32, the 32-bit ARM instruction set with Thumb2 compression) for that.
By contrast, RISC-V tends to keep instructions minimal, supports a
compressed extension (that supports common instructions in 16 bits in addition to the 32-bit encoding for all instructions), allowing for
smaller minimal implementations; for more sophisticated
implementations, the idea is that the instruction decoder combines instructions into more capable microinstructions (sometimes called macroinstructions because they are actually larger than the
architectural instructions). But of course you don't see that on the architectural level. E.g., here's gforth-fast's +:
RISC-V ARM A64 AMD64 RTL
ld a5,$8(s8) ldr x0, [x25,#0x8]! tmp = load(SP+8)
addi s10,s10,8 add x26, x26, #0x8 add r13,$08 IP = IP+8
addi s8,s8,8 add r15,$08 SP = SP+8
add s7,s7,a5 add x27, x0, x27 add r8,[r15] TOS = TOS+tmp
ld a4,$-8(s10) ldur x1, [x26,#-0x8] mov rcx,-$08[r13] tmp = load(IP-8)
jr a4 br x1 jmp ecx jmp tmp
RTL is "register-transfer language", a pseudocode for describing instructions. I use Forth virtual machine register names here.
I rearranged the AMD64 instructions to match the order of the others; originally the first and second AMD64 instructions were swapped.
Here A64 combines the first and third instruction of the RISC-V code
in its first instruction. We wrote it such that the last two
instructions can be separated from the others, otherwise the compiler
would probably have combined the second A64 instruction with the ldur
into one instruction.
As a non-RISC, AMD64 has load-and-op instructions, as demonstrated by combining the first and fourth RISC-V instruction into the third AMD64 instruction. AMD64 also could combine the last two instructions into
one, but gcc has not done that after gcc-2.95 (there for IA-32).
- anton
--
M. Anton Ertl http://www.complang.tuwien.ac.at/anton/home.html comp.lang.forth FAQs: http://www.complang.tuwien.ac.at/forth/faq/toc.html
New standard: https://forth-standard.org/
EuroForth 2022: https://euro.theforth.net
I read an article by Sam Falvo on trying to make machine Forth for
RISC V and the instruction set seemed to require a lot of
instructions per Forth primitive. Is that the "state of the art" for
"risc".
On Wednesday, January 11, 2023 at 11:12:03 AM UTC+1, none albert wrote:[..]
[..]I have now a DshangNezha STU board on my desk with a tinalinuxPlease, be more specific. "DshangNezha STU board" is something even Google can't find.
running right of the box. 64 bits 1 Ghz .5 Gbyte.
"Join the risc-V bandwagon" is a thread that is unknown.
Please, be more specific. "DshangNezha STU board" is something even Google can't find.
In 2020 the noforth team (Albert Nijhof and Willem Ouwerkerk)
has made a 32 bit noforth for the risc-V .
Latest official version : mid 2021
Subject: Join the risc-V bandwagon!
X-Newsreader: trn 4.0-test77 (Sep 1, 2010)
I have now a DshangNezha STU board on my desk with a tinalinux
running right of the box. 64 bits 1 Ghz .5 Gbyte.
On Wednesday, January 11, 2023 at 6:05:15 AM UTC-5, Zbig wrote:
Riscv is in the long run to obliterate Intel AMD and ARM, becauseCompetition is good. At the moment RISC V boards still are expensive
it is royalty free, such that Chinese companies can no longer be
strong armed. The smaller ARM royalties has had already an impact.
compared to ARM-based ones.
I read an article by Sam Falvo on trying to make machine Forth for
RISC V and the instruction set seemed to require a lot of
instructions per Forth primitive. Is that the "state of the art" for
"risc".
I am wondering how the Netherlands team found RISC V handled Forth?
Is the source available to be reviewed?
On Wednesday, January 11, 2023 at 8:29:15 PM UTC+1, Marcel Hendrix wrote:
On Wednesday, January 11, 2023 at 11:12:03 AM UTC+1, none albert wrote: >[..][..]
I have now a DshangNezha STU board on my desk with a tinalinuxPlease, be more specific. "DshangNezha STU board" is something even Google >> can't find.
running right of the box. 64 bits 1 Ghz .5 Gbyte.
"Join the risc-V bandwagon" is a thread that is unknown.
Wait, you meant "Sipeed Nezha 64bit RISC-V Linux Sbc Board,
Allwinner D1@1.0GHz, 1Gbyte DDR3, support for Tina/Debian System?"
But that board is $133, with $13.72 transportation cost, no power supply.
-marcel
The cheapest board is 13 dollar with 7 dollar shipping.
RISC-V
ld a5,$8(s8)
addi s10,s10,8
addi s8,s8,8
add s7,s7,a5
ld a4,$-8(s10)
jr a4
Wait, you meant "Sipeed Nezha 64bit RISC-V Linux Sbc Board,
Allwinner D1@1.0GHz, 1Gbyte DDR3, support for Tina/Debian System?"
But that board is $133, with $13.72 transportation cost, no power supply.
anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
RISC-V
ld a5,$8(s8)
addi s10,s10,8
addi s8,s8,8
add s7,s7,a5
ld a4,$-8(s10)
jr a4
It looks like you could get smaller code by choosing lower register
numbers, so that more of the instructions could use the compressed
encoding supported by almost all RISC-V chips.
For Gforth the Visionfive 1 is quite a bit slower than the Odroid C2
(and I expect that it is also slower than the Raspi 3, but by a
smaller margin). The numbers below are times in seconds:
sieve bubble matrix fib fft release; CPU; gcc
0.519 0.555 0.483 0.797 0.729 20220226 (3 regs); 1GHz U74 Visionfive V1 0.350 0.390 0.240 0.470 0.280 20190124; Odroid C2 (1536MHz Cortex-A53)
- anton--
Please, be more specific. "DshangNezha STU board" is something even Google can't find.
"Join the risc-V bandwagon" is a thread that is unknown.
Marcel Hendrix <m...@iae.nl> writes:
Please, be more specific. "DshangNezha STU board" is something even Google can't find.It's "Dshang" "Nezha", not the two run together. For instance:
"Join the risc-V bandwagon" is a thread that is unknown.
https://liliputing.com/nezha-is-a-99-single-board-pc-with-a-risc-v-processor/
Marcel Hendrix <m...@iae.nl> writes:
Please, be more specific. "DshangNezha STU board" is something even Google can't find.It's "Dshang" "Nezha", not the two run together. For instance:
"Join the risc-V bandwagon" is a thread that is unknown.
https://liliputing.com/nezha-is-a-99-single-board-pc-with-a-risc-v-processor/
I'm seeing prices more around USD $100 than $17, but we'll see.
It may have been discounted as it _is_ pretty modest in specs.
Andy Valencia
Home page: https://www.vsta.org/andy/
To contact me: https://www.vsta.org/contact/andy.html
I'm seeing prices more around USD $100 than $17, but we'll see.
It may have been discounted as it _is_ pretty modest in specs.
On Friday, January 13, 2023 at 12:30:08 AM UTC, Andy Valencia wrote:
Marcel Hendrix <m...@iae.nl> writes:
Please, be more specific. "DshangNezha STU board" is something even GoogleIt's "Dshang" "Nezha", not the two run together. For instance:
can't find.
"Join the risc-V bandwagon" is a thread that is unknown.
https://liliputing.com/nezha-is-a-99-single-board-pc-with-a-risc-v-processor/
I'm seeing prices more around USD $100 than $17, but we'll see.
It may have been discounted as it _is_ pretty modest in specs.
Andy Valencia
Home page: https://www.vsta.org/andy/
To contact me: https://www.vsta.org/contact/andy.html
Thanks for the link. From the photos, it is a clone of the
Sipeed Nezha 64bit RISC-V Linux SBC ?
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