There are sure to be some caveats, which is what I am asking about. Any thoughts?
I'm contemplating a Forth machine with 24-bit cells that pack three 8-bit chars per cell. Data memory would consist of three byte-lanes. Rather than use modulo 3 addressing, I would use modulo 4 which behaves like a typical 32-bit Forth (4 bytes/cell)but with the fourth byte-lane missing. Accessing any byte address whose two LSBs are "11" would be an ambiguous condition.
I think this is workable if the starting addresses of strings are cell-aligned. Then CELLS would have a reference point for its math. CELL+ would be easy: If it results in an invalid address, do 1+ again.
The most important thing is testability, which any 32-bit Forth can be adapted to. Char operators can test for invalid char addresses.
So, this breaks the assumption that char addressing is monotonic but it is not a show stopper nor does it break backward compatibility. The 24-bit code will still run in a 32-bit environment.
There are sure to be some caveats, which is what I am asking about. Any thoughts?
One interesting idea would be to design a word-addressed machine, and provide primitives to fetch/store a variable amount of bits or bytes starting from a native word address unit. With this in place, one could in theory resynthesise and recompile bothprocessor HDL and Forth core for an arbitrary Forth cell width.
On Sunday, October 30, 2022 at 4:56:01 PM UTC+1, Brad Eckert wrote:Nope, no sound technical reasons. But that's okay, I am tilting toward word addressing anyway. I like Sh-BOOM's handling of octets.
[..]
There are sure to be some caveats, which is what I am asking about. Any thoughts?I assume you have sound technical reasons for this.
The first iForth's were specific for a segmented architecture (32 address bits, upper
16 indicated the segment). It worked well, but eventually I got tired of the non-standardness of the scheme and scrapped the idea.
Do you think your idea will survive (i.e. be worthwile) 10 years from now (or even 2)?
-marcel
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