I am happy to announce that Mecrisp-Quintus,
an optimising native code Forth for 32 bit RISC-V and MIPS,
reached the first stable release!

The package also contains complete RISC-V example designs for FPGAs.

You can get it as usual on mecrisp.sourceforge.net

Best wishes,
Matthias Koch

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Matthias Koch <m.cook@gmx.net> writes:

I am happy to announce that Mecrisp-Quintus,
an optimising native code Forth for 32 bit RISC-V and MIPS,
reached the first stable release!

Nice, congrats!

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On Wednesday, 19 October 2022 at 19:42:22 UTC+1, Paul Rubin wrote:

Matthias Koch <m.c...@gmx.net> writes:

I am happy to announce that Mecrisp-Quintus,
an optimising native code Forth for 32 bit RISC-V and MIPS,
reached the first stable release!

Nice, congrats!

Congratulation from here as well.

And checking the link you posted
shows, how many processors you have ported mecrisp to.
And demonstrates the work and time you have invested to get there.
Very impressive.

Is there a "step by step" description, how to get mecrisp onto the different processors?
Could not see it but might have missed it.

While I did the book about Ting's "eForth as Arduino Sketch"
I documented the "39 steps" it took me to get there and some little examples. https://wiki.forth-ev.de/doku.php/projects:430eforth:start https://www.amazon.co.uk/eForth-Arduino-Sketch-extra-Programmer/dp/B088P1CW83

And many years ago you helped to get the mecrisp onto the microbit https://wiki.forth-ev.de/doku.php/en:projects:microbit:start

OK, microbit is not your target audience I assume,
but this brings up the question,
if there will be soon a mecrisp for RPI PICO?

It might be helpful as well, to have a table of boards
( in addition to the processors)
with links to point to the related hardware,
so people can recognize the board they have unused in the drawer,
download the related mecrisp and try it out.

Just ideas.
And thanks again for the great work.

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On Wednesday, 19 October 2022 at 10:34:52 pm UTC+10, Matthias Koch wrote:

I am happy to announce that Mecrisp-Quintus,
an optimising native code Forth for 32 bit RISC-V and MIPS,
reached the first stable release!

The package also contains complete RISC-V example designs for FPGAs.

You can get it as usual on mecrisp.sourceforge.net

Best wishes,
Matthias Koch

Matthias. Congratulations.

Any thoughts on things you found in optimising performance of forth on Risc compared to x86, and Arm.

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Thank you!

Any thoughts on things you found in optimising performance of forth on Risc compared to x86, and Arm.

I can comment on ARM vs RISC-V/MIPS only. ARM Cortex M0 offers eight registers only for most opcodes, r0 to r7, and requires special attention to load large constants or perform far calls, especially between RAM and flash memory that have large gap in
address space by convention. Conditional jump range is very short in M0.

RISC-V offers 31 registers (and one hardwired zero-register) and loads/stores/calls any 32 bit constant or destination with two instructions at most. For a Forth compiler performing register allocation, the RISC-V one benefits a lot taking advantage of
the additional registers available. Also the opcode format is simpler and more regular, which helps in compiler design complexity.

Besides that, one important conceptual difference is that ARM works with flags that are set by certain instructions and conditional jumps acting on these later, whereas RISC-V does not have flags, but uses "comparing jumps" like "beq x8, x9, label". Both
ways are fine for Forth.

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if there will be soon a mecrisp for RPI PICO?

Sure!

* Get current Mecrisp-Stellaris package,
* go to rp2040-ra folder,
* and see README in that folder for instructions.

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On Tuesday, October 25, 2022 at 9:36:11 AM UTC-4, Matthias Koch wrote:

Thank you!

Any thoughts on things you found in optimising performance of forth on Risc compared to x86, and Arm.

I can comment on ARM vs RISC-V/MIPS only. ARM Cortex M0 offers eight registers only for most opcodes, r0 to r7, and requires special attention to load large constants or perform far calls, especially between RAM and flash memory that have large gap in

address space by convention. Conditional jump range is very short in M0.

RISC-V offers 31 registers (and one hardwired zero-register) and loads/stores/calls any 32 bit constant or destination with two instructions at most. For a Forth compiler performing register allocation, the RISC-V one benefits a lot taking advantage of

the additional registers available. Also the opcode format is simpler and more regular, which helps in compiler design complexity.

Besides that, one important conceptual difference is that ARM works with flags that are set by certain instructions and conditional jumps acting on these later, whereas RISC-V does not have flags, but uses "comparing jumps" like "beq x8, x9, label".

Both ways are fine for Forth.

It's been a long time since I looked at ARM code, but I seem to recall there being means of conditional execution of instructions, rather than jumps. Is this something that is used in Forth easily? I don't recall details, but this might only be
available on certain instruction set variants. I believe there are a lot of those.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

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It's been a long time since I looked at ARM code, but I seem to recall there being means of conditional execution of instructions, rather than jumps. Is this something that is used in Forth easily? I don't recall details, but this might only be

available on certain instruction set variants. I believe there are a lot of those.

For short: Difficult to use in Forth, not available on ARM Cortex M0, very limited in M3, M4. Go read instruction set manuals!

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On Wednesday, October 26, 2022 at 4:42:57 AM UTC-4, Matthias Koch wrote:

It's been a long time since I looked at ARM code, but I seem to recall there being means of conditional execution of instructions, rather than jumps. Is this something that is used in Forth easily? I don't recall details, but this might only be

available on certain instruction set variants. I believe there are a lot of those.

For short: Difficult to use in Forth, not available on ARM Cortex M0, very limited in M3, M4. Go read instruction set manuals!

Thanks.

I'm not writing assembly code. That's why I'm not current on it all. I prefer writing code in Forth.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

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On Wednesday, October 19, 2022 at 1:34:52 PM UTC+1, Matthias Koch wrote:

I am happy to announce that Mecrisp-Quintus,
an optimising native code Forth for 32 bit RISC-V and MIPS,
reached the first stable release!

The package also contains complete RISC-V example designs for FPGAs.

You can get it as usual on mecrisp.sourceforge.net

Best wishes,
Matthias Koch

Thanks - I have a Vega board, will be nice to try this...

J^n

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