So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor
plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.


I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with
age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.


Thanks again.



Wayne.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 7, 2022 at 9:58:39 AM UTC-4, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor

plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

This sounds a bit like async logic design. I don't know about the "crossing paths", that sounds like something that is extremely hard to implement, coming under the heading of extreme optimization. As you may know, optimization is the enemy of
flexibility. Optimize in this manner and find you have a simple change to make to fix an error, and you have to do the optimization all over again.

However, if you have nothing but time on your hands, there's no reason to not give it a go. I suggest working with some very simple design first, to solidify your concepts. They certainly can use some degree of solidification.

One power optimization that many people don't understand, is to put enabled registers at the input of each section of logic, rather than at the output of each section. Power is dissipated by the logic elements changing. If a logic section's output is
not going to be used, it is the inputs that need to remain stable to prevent power waste in pointless calculations. So enabled registers at the input of each logic section saves that wasted power.

These days, it's not so important to make tiny processors into even smaller processors. Even if you want to put 1000s of them on a single chip, it is better to design for short term goals, than to try to bite off the whole cow at once.

Just some friendly advice. If you follow it, you might just start to get somewhere rather than always talking about a new direction you wish to go.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On 7/7/22 8:58 AM, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor

plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

You will need more transistors than that. An ALU, some registers, and
control logic. It adds up fast. A RAM/register cell is 4 transistors in
CMOS plus the access and decode logic.

My course work is now more than 20 years old but way back when the
standard text was: https://www.amazon.com/CMOS-VLSI-Design-Circuits-Perspective/dp/0321547748

Then of course there was the now wildly outdated course in computer architecture.

--
http://davesrocketworks.com
David Schultz

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 12:38:05 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Thursday, July 7, 2022 at 9:58:39 AM UTC-4, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000

transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

This sounds a bit like async logic design. I don't know about the "crossing paths", that sounds like something that is extremely hard to implement, coming under the heading of extreme optimization. As you may know, optimization is the enemy of

flexibility. Optimize in this manner and find you have a simple change to make to fix an error, and you have to do the optimization all over again.

However, if you have nothing but time on your hands, there's no reason to not give it a go. I suggest working with some very simple design first, to solidify your concepts. They certainly can use some degree of solidification.

One power optimization that many people don't understand, is to put enabled registers at the input of each section of logic, rather than at the output of each section. Power is dissipated by the logic elements changing. If a logic section's output is

not going to be used, it is the inputs that need to remain stable to prevent power waste in pointless calculations. So enabled registers at the input of each logic section saves that wasted power.

These days, it's not so important to make tiny processors into even smaller processors. Even if you want to put 1000s of them on a single chip, it is better to design for short term goals, than to try to bite off the whole cow at once.

Just some friendly advice. If you follow it, you might just start to get somewhere rather than always talking about a new direction you wish to go.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Thanks Rick. The stable outputs makes sense. A register doesn't. But maybe there is some circuit to hold the output or inputs stable, but do I want them to turn off completely with the section idea. However, there was that three state logic Chuck was
using which was stable, but that would be part of a special node process, not implementable in a normal process?

I look at doing optimisation, because I'm aiming at a low cost 1000+ trasistor design instead of a large complex design. So, the optimisation can be done a lot quicker to a higher perfection. Competition is cost, performance, low energy and reliability.
I'm worried about reliability here of a optimised design. It's something I can't prove. Products will last in field certain times.

I didn't go and work at ITV, because they wanted me to self fund going there, and I didn't trust my family, and that turned out to be so true. Otherwise I could have been over there designing processors too by now.

In this small design, there are ways to design to maximise performance or minimise energy, or design more costly for each. It's a matter of picking one of the first two for me. The smaller processor allows for faster processing timed and lower costs.
I am interested in using space for memory. Where GA144 uses a segmented space and lots of processors. I'm interested in a low segmented space with flatter addressing, with each segment tied to one of more processors tied to input or code work (thanks
fur the pep talk in the other thread, I actually came up with the design to answer many of your objections). So, all cores and inputs/outputs and memory are tightly bonded to the flow of work, with some flexibility to reassign some cores etc, to where
there is more work. Using simple signaling coordinating buffer access, a workflow could be pipelined like in a GA row, or mini array. Because the structure is dynamic, the amount of memory available to a core, is not restricted by inter core spacing,
like on the 144. Of course I'm looking at banked dual access (and associative) memory techniques. It's more dynamic and general purpose. It's not aimed at what the 144 is aimed at, but in performing custom feature sets simply fast. A perfect processor
for an simpler 1970's/1980's computer, to perform most functions. I've already came up with a simple interface to replace D controllers, rs232, parralel, USB, sound, video, wifi on such a computer leaving memory cards as the last thing. Using rom back
then could implement the standard part of the functions for the features (in 1976 ram would be thousands for hardly anything). I've worked out I can add lots of patterns on the card proposal at cheap prices. So, some tiling and some object techniques,
give you some pretty good imagery with little real memory. Allowing for more state bits stored for the game and graphics in the limited memory. It's not adding things, it's about including enough to make it a good product. holistic design rather thsnr
There is a lot I don't intend to add here, unless it is done as a close product. This is just enough to make it marketable.

A 1000+ transistor core on its own is pretty useless, as the 16 bit+ lines are going make it cost. So, adding relatively sized internal memory and IO bus configuration and processing, makes it a marketable product. I'm looking at single core design,
but also repeating the then existing core, IO pin configuration blocks and memories, to make a multiple core design simply. It's all tedious work to make things right. If you start out wrong, you can be compromised for the life of the product. So, I
don't aim for perfection, but an educational example base designs, hopefully complete and perfect, which can be improved upon. Analyse, use and rely on, at one's own risk. As such, I probably will be looking for an engineer's funded verification.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 11:28:47 AM UTC+10, David Schultz wrote:

On 7/7/22 8:22 PM, Wayne morellini wrote:

Are you from around here?

That depends on where "here" is.
--
http://davesrocketworks.com
David Schultz

Comp.lang.forth?

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 1:23:03 AM UTC+10, David Schultz wrote:

On 7/7/22 8:58 AM, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000

transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

You will need more transistors than that. An ALU, some registers, and control logic. It adds up fast. A RAM/register cell is 4 transistors in
CMOS plus the access and decode logic.

My course work is now more than 20 years old but way back when the
standard text was: https://www.amazon.com/CMOS-VLSI-Design-Circuits-Perspective/dp/0321547748

Then of course there was the now wildly outdated course in computer architecture.

--
http://davesrocketworks.com
David Schultz

That's the lower end target, but will be as big as it will be. It's meant to compete with low cost integrated controllers out there, so size matters. It's straight forwards 16 opcode or less 16 bit misc processor, very light weight processors. Are you
from around here? So, hopefully 4 instructions per memory access. In the extreme end of simple value generating and comparing decision tree and data shifting applications. But, not that it can't be used for more advanced applications. I admit, it
would be challenge and just have 4 slots per return and data stacks equals 512 transistors, a 4 bit version 128 transistors. A challenge to aim towards. As with the other thread, a coffee maker application requires very little, so a 4 bit version would
be fine. Even just storing the stacks in memory leaves two stack pointers. The whole thing slows down, and energy might go up, but a coffeemaker it makes very little difference in practical terms. On chip memory, yes. 4 or 8 bit versions, yes. But,
1000 is only a base line potential target for the core, which die size for cache segment could be increased, and bids width (but then again, optimisation might make extension difficult.

Thanks for the book link David.

Are you from around here?

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On 7/7/22 8:22 PM, Wayne morellini wrote:

Are you from around here?

That depends on where "here" is.

--
http://davesrocketworks.com
David Schultz

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On 7/7/22 9:02 PM, Wayne morellini wrote:

On Friday, July 8, 2022 at 11:28:47 AM UTC+10, David Schultz wrote:

On 7/7/22 8:22 PM, Wayne morellini wrote:

Are you from around here?

That depends on where "here" is.
--
http://davesrocketworks.com
David Schultz

Comp.lang.forth?

Nobody can be from there because it is nowhere. Or perhaps wherever the distributed servers are.

In any case, my first news reader was rn.

--
http://davesrocketworks.com
David Schultz

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 12:02:55 PM UTC+10, Wayne morellini wrote:

On Friday, July 8, 2022 at 11:28:47 AM UTC+10, David Schultz wrote:

On 7/7/22 8:22 PM, Wayne morellini wrote:

Are you from around here?

That depends on where "here" is.
--
http://davesrocketworks.com
David Schultz

Comp.lang.forth?

Yes. I see you here David. Thanks for the past advice on the magic design tool. I'm still trying to decide if magic or Okad is easier to do this. The glow version is supposed to be used by high school children.

I don't know why they don't go towards magnetic computing you could also print. But it would be potentially a few millions times less energy and much faster.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Does anybody know if their are restrictions on short haul video transmission to a in room tv via a tv digital channel, like they allowed with analogue tv channels?

Is there a way to produce a carrier clock that fast enough on chip? So send to tv from devices.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thu, 7 Jul 2022 18:00:34 -0700 (PDT)
Wayne morellini <waynemorellini@gmail.com> wrote:

But maybe there is some circuit to hold the output or inputs stable,
but do I want them to turn off completely with the section idea.

Transparent latch? (Not available in most FPGAs)

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Wayne morellini <waynemorellini@gmail.com> writes:

Does anybody know if their are restrictions on short haul video
transmission to a in room tv via a tv digital channel, like they
allowed with analogue tv channels?

Nobody cares about that any more. Everyone has cable and TV sets have
HDMI inputs.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 6:44:35 PM UTC+10, Paul Rubin wrote:

Wayne morellini <waynemo...@gmail.com> writes:

Does anybody know if their are restrictions on short haul video transmission to a in room tv via a tv digital channel, like they
allowed with analogue tv channels?

Nobody cares about that any more. Everyone has cable and TV sets have
HDMI inputs.

But HDMI is very impractical for very small portable devices. That's why I'm trying to come up with a HDMI attached relay alternative, but in the meantime digital TV signal is an existing standard that can be adopted in. It's all very messy, but a
digital tv signal is a compromise.. do, the question was, what restrictions are there.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 5:56:20 PM UTC+10, Jan Coombs wrote:

On Thu, 7 Jul 2022 18:00:34 -0700 (PDT)
Wayne morellini <waynemo...@gmail.com> wrote:

But maybe there is some circuit to hold the output or inputs stable,
but do I want them to turn off completely with the section idea.

Transparent latch? (Not available in most FPGAs)

Thanks Jan.

My.jtmoru 8s vkmy.bsck
Doesn't GA use some three state technology, or something like thyresistor or memristor?

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 7, 2022 at 9:00:35 PM UTC-4, Wayne morellini wrote:

On Friday, July 8, 2022 at 12:38:05 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Thursday, July 7, 2022 at 9:58:39 AM UTC-4, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000

transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

This sounds a bit like async logic design. I don't know about the "crossing paths", that sounds like something that is extremely hard to implement, coming under the heading of extreme optimization. As you may know, optimization is the enemy of

flexibility. Optimize in this manner and find you have a simple change to make to fix an error, and you have to do the optimization all over again.

However, if you have nothing but time on your hands, there's no reason to not give it a go. I suggest working with some very simple design first, to solidify your concepts. They certainly can use some degree of solidification.

One power optimization that many people don't understand, is to put enabled registers at the input of each section of logic, rather than at the output of each section. Power is dissipated by the logic elements changing. If a logic section's output is

not going to be used, it is the inputs that need to remain stable to prevent power waste in pointless calculations. So enabled registers at the input of each logic section saves that wasted power.

These days, it's not so important to make tiny processors into even smaller processors. Even if you want to put 1000s of them on a single chip, it is better to design for short term goals, than to try to bite off the whole cow at once.

Just some friendly advice. If you follow it, you might just start to get somewhere rather than always talking about a new direction you wish to go.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

Thanks Rick. The stable outputs makes sense. A register doesn't. But maybe there is some circuit to hold the output or inputs stable, but do I want them to turn off completely with the section idea. However, there was that three state logic Chuck was

using which was stable, but that would be part of a special node process, not implementable in a normal process?

Tristate??? If you want to turn off logic, that is done at the power connection and has nothing to do with tristate outputs. There is literally no use for tristate outputs in internal logic on a remotely modern chip. They used to provide tristate
buffers for long line drivers in FPGAs, in the very earliest devices (circa 1990s), because they allow multiple drivers to implement "wire OR" or "wire AND" buses, eliminating what can be large multiplexer logic. But driving long lines on a chip is slow,
so they were quickly eliminated from FPGA designs, being replaced with standard logic.

Powering down logic is typically done on large sections of logic, such as individual peripheral devices. Better is to stop the clock, which eliminates the dynamic power draw. If you are going to use more recent process nodes (anything below
approximately 90 nm), they also have significant static current. So stopping the clock is not as effective. Even more recent process nodes (not sure of exact numbers) use special gate geometry to have more control over the channel carriers, and so
reduce subthreshold leakage, only high-k dielectrics can mitigate gate oxide leakage which become a problem with the most recent process nodes. So powering down logic can reduce some of the impact of the high static current.

I look at doing optimisation, because I'm aiming at a low cost 1000+ trasistor design instead of a large complex design. So, the optimisation can be done a lot quicker to a higher perfection. Competition is cost, performance, low energy and reliability.

I'm worried about reliability here of a optimised design. It's something I can't prove. Products will last in field certain times.

Instead of a large, complex design (but no more complex than other designs, so not really complex at all), you wish to create a small, complex design, that is complex in ways most people can even imagine.

I didn't go and work at ITV, because they wanted me to self fund going there, and I didn't trust my family, and that turned out to be so true. Otherwise I could have been over there designing processors too by now.

In this small design, there are ways to design to maximise performance or minimise energy, or design more costly for each. It's a matter of picking one of the first two for me. The smaller processor allows for faster processing timed and lower costs. I

am interested in using space for memory. Where GA144 uses a segmented space and lots of processors. I'm interested in a low segmented space with flatter addressing, with each segment tied to one of more processors tied to input or code work (thanks fur
the pep talk in the other thread, I actually came up with the design to answer many of your objections). So, all cores and inputs/outputs and memory are tightly bonded to the flow of work, with some flexibility to reassign some cores etc, to where there
is more work. Using simple signaling coordinating buffer access, a workflow could be pipelined like in a GA row, or mini array. Because the structure is dynamic, the amount of memory available to a core, is not restricted by inter core spacing, like on
the 144. Of course I'm looking at banked dual access (and associative) memory techniques. It's more dynamic and general purpose. It's not aimed at what the 144 is aimed at, but in performing custom feature sets simply fast. A perfect processor for an
simpler 1970's/1980's computer, to perform most functions. I've already came up with a simple interface to replace D controllers, rs232, parralel, USB, sound, video, wifi on such a computer leaving memory cards as the last thing. Using rom back then
could implement the standard part of the functions for the features (in 1976 ram would be thousands for hardly anything). I've worked out I can add lots of patterns on the card proposal at cheap prices. So, some tiling and some object techniques, give
you some pretty good imagery with little real memory. Allowing for more state bits stored for the game and graphics in the limited memory. It's not adding things, it's about including enough to make it a good product. holistic design rather thsnr There
is a lot I don't intend to add here, unless it is done as a close product. This is just enough to make it marketable.

A 1000+ transistor core on its own is pretty useless, as the 16 bit+ lines are going make it cost. So, adding relatively sized internal memory and IO bus configuration and processing, makes it a marketable product. I'm looking at single core design,

but also repeating the then existing core, IO pin configuration blocks and memories, to make a multiple core design simply. It's all tedious work to make things right. If you start out wrong, you can be compromised for the life of the product. So, I don'
t aim for perfection, but an educational example base designs, hopefully complete and perfect, which can be improved upon. Analyse, use and rely on, at one's own risk. As such, I probably will be looking for an engineer's funded verification.

Lots of MCUs have very, very little memory, a fraction of 1kB RAM and only a handful kB of Flash. So you don't need to use much memory to design a useful processor. In fact, the real question comes back to application. What is the target application?
That will strongly impact the memory size since the memory has the biggest area impact on other small MCUs, and at 1000 transistors, the memory will totally dominate this design, and so, the cost.

In fact, you will see the memory size will be the only important cost controlling feature. If your CPU is 1,000 or 2,000 or even 4,000 transistors will barely matter at all if you have 8 kB of Flash and 1 kB of RAM.

It's only a multi CPU design where the processor size would be optimized usefully, but then you are back to a GA144 sort of design with a scrap of memory on each node. If you add more significant memory to each node, you are back to the memory
dominating chip size. If you try to share a single memory between all the nodes, you end up with a chip dominated by routing.

Why do you think no one has been able to improve on this to date? Do you think no one is smart enough?

As I've said, many, many times. Until you select a target application, you won't be able to pick the optimal trade off between the many, many factors involved.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 11:58:30 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Thursday, July 7, 2022 at 9:00:35 PM UTC-4, Wayne morellini wrote:

On Friday, July 8, 2022 at 12:38:05 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Thursday, July 7, 2022 at 9:58:39 AM UTC-4, Wayne morellini wrote:

..

I look at doing optimisation, because I'm aiming at a low cost 1000+ trasistor design instead of a large complex design. So, the optimisation can be done a lot quicker to a higher perfection. Competition is cost, performance, low energy and

reliability. I'm worried about reliability here of a optimised design. It's something I can't prove. Products will last in field certain times.

Instead of a large, complex design (but no more complex than other designs, so not really complex at all), you wish to create a small, complex design, that is complex in ways most people can even imagine.

Doing it with 1 million transistors by hand on an incredibly intertwined complex circuit would not normally be possible in normal lifetime. 2000 transistors would be exponentially more complex than 1000 transistors. It's likely that only certain parts
are optimal to be complexed to get a lot of gains. So, even if the core is 4000 transistors only 1000 or less might be in that category (a lot is memory in a full version). Maybe I should just say the core is without stacks (to the side of the core),
but placement of stacks will affect performance.

Lots of MCUs have very, very little memory, a fraction of 1kB RAM and only a handful kB of Flash. So you don't need to use much memory to design a useful processor. In fact, the real question comes back to application. What is the target application?

That will strongly


Most applications. It's general purpose, and can be made with differing amounts of pins, memory or processors. If an open community processor, manufacturers can pick the size of everything while maintaining binary compatibility (obviously, if 4 or 8 bit
stacks and memory, 16 bit usage is not included).

impact the memory size since the memory has the biggest area impact on other small MCUs, and at 1000 transistors, the memory will totally dominate this design, and so, the cost.

Core. Only stack memory and pointers etc to be included, however, I am amending that to potentially not have stacks in the design. Secretly. I'm looking at 2 or less transistor memory design, but sram is likely faster for stacks. If the available node
process isn't able to do this, my reaction will likely just be to use what it does support. If I can use rom to implement the features, it is still external to the core figure, which I have been saying is at least 1000 transistors (1000+). For a more
fuller design, there would be memory on die, if a memory die can't be packed in cheaply, as a multichip, (sorry loosing track here) instead of the extra cost of connecting it to an external memory. This would hopefully optimise performance and energy.
So, there is a certain level of on-chip memory you can have before a multiple chip package or external memory, would be cheaper. The fuller version would include multiple processors tied to the pin workflow. But, that includes the separate core, io and
memory section stages, and maybe just a simple one core version with external memory, might be done as proof of concept.

In fact, you will see the memory size will be the only important cost controlling feature. If your CPU is 1,000 or 2,000 or even 4,000 transistors will barely matter at all if you have 8 kB of Flash and 1 kB of RAM.

I want to explore packaged storage chip concepts, if flash can't be done, like flash. I think that the rom concept might be all that's needed at the cheapest prices. I mean, your coffee maker function can be made right once and not need an update.
Plus, external memory is commodity pricing, low processor die runs are more expensive. The reduced core size has distinctive advantages and allows for more in die memory, raising the effective wafer area usage, reducing manufacturing cost per unit of
area for the same amount of chips, until you get to the cross over point where using external memory to the die is cheaper. But, it depends on what is available in the manufacturing for the process. It maybe a process set up to support on due memory
cheap. But, I really would like to avoid the use of complex external serial dram schemes. That can be done later if things are go well. These motors, and flash have a lot of issues.

It's only a multi CPU design where the processor size would be optimized usefully,

I described that it can be dynamically setup to maximise usage, for that reason. What ever is surplus to optimal performance can be turned off or clocked down.

If you add more significant memory to each node, you are back to the memory dominating chip size. If you try to share a single memory between all the nodes, you end up with a chip dominated by routing.

No. The manufacturer adds as much memory and cores as needed. It's just that I want it to support a range from 16 words to megabytes. There would be a simple bus and transactional structure. In my simple scheme for other array processors, there is
space for each chip, and shared spaces fur each neighbours but there were some other low complexity buses, including one at a time shared buses. So using signaling as a token passing method you avoid access conflicts. Now, if you have the memory such
that the other neighbour can dump work into part of your processor's memory, and signal to you to process it (single user system, programmer can control interactions). You work on other parts of the memory, while the nearest neighbour works on that
section, then you work on that section. So, I would like dual access for performance etc, a lot can be done by dividing address sieve up into banks with a common bus, with access lines tied off until the processor is signaled, then the neighbour lines
are tied off and the processor accesses. Tieing off can be as simple as not accessing it. But, I do want to restrict rogue executing, incase of a execution fault, so only certain things give down until the user can get out and recover the system by
rebooting.

Anyway, having multiple neighbours handling the same data is maybe a bit more complex, but a common bus and signaling, different processors can read and perform processing, and as they process another can access. Unless you pass to nearest neighbour,
like a simple pipelined approach, you are likely dealing with chunks, so that processing a chunk will take more time than loading it in, leaving the next processors free to load in. There is a bit more to the scheme than I'm saying, but remember the non
neighbour general access is really meant for very heavy unnusual loads, or signaling and exceptional messaging. It could be fine with a single data line serially. However, In have another scheme in mind. But nearest neighbour is at least a group of
three processors, which is a lot, and you could say 9 processors etc, but then that might get tricky.

Why do you think no one has been able to improve on this to date? Do you think no one is smart enough?

Improve on what? Which part are you referring too? I assume others might have done something. Chuck certainly improved on it on various areas. There is a variety of ways to do things, and people often just dint see it. Smart is not the issue, it's
only part of it. I've been at this for decades. You can't just design a ISA, you have to think about the hardware design to make the ISA work better. I might have difficulty now, but I have a wealth of previous experience on this to draw upon, what I
can remember. I'm literally making a lot of this up as I type. I used to do that with complex stuff and no experience with a subject, a long time back, faster than I could type or write. You won't find many people like that. I used to think in
structure and dynamic structural concepts. People always say stuff, while it's obvious that it can be done differently. I wish things were a lot better, I got really sick in the death trap I lived in, and literally trapped there against my wishes. I
pulled something like 21 or 27 hormone based cockroach baits out over three years or so, and picked up, relatively, before the Lymes like disease there, then something else twisted to that etc, and other things which should have never been done. I had
to virtually stop all work on my OS design due to sickness there early on. The last major section so was working on was an API spec for a full body VR control interface, as the last part of my physical controller device interface spec. Every joint and
part movements, but that gets down to muscle movements. So fortunately I stopped then, lots of muscle movements to get into, which I wasn't up to speed on. You could literally use such a spec to monitor a patents health non contact remotely.

As I've said, many, many times. Until you select a target application you won't be able to pick the optimal trade off between the many, many factors involved.

Look Rick, when I was 10 or 12 I was mapping human intelligence worked and how to design it for a machine to do the same. Research since had proved my theory right band improvements since then.

When I was 14, our science teacher (the daughter of the South African mine manager that Roger More played in the movie Gold about a famous mine accident where they hit a pocket of water) told us that perpetual motion machines weren't possible, giving the
spinning axis motion stuff. Within 30 seconds I came up with a way it could be fine, and with 15 minutes or so, how to do it with conventional technology, and within 45 minutes, after class, I concluded it would disrupt the economy and energy sectors,
and decided it wasn't a good idea. It seems related to other ones out there. I used to annotate what was wrong with summary science articles all the time, and you would be surprised at how much is wrong on each page. So what do you think Rick? You
come along with stuff and I keep answering it. But, what have you done that's original thought? The past stuff I'm not putting here, is more new than anything out there. Like contextual serial computing, strange and weird 2 bit, conventional
processing like, architectures, fpga dsp and gpu and distributed parralel processing architectures where hundreds of thousands of cores could be useful (obviously I'm dropping the serial contextual stuff, too awkward). .the freakin tic tac patent is like
my surface affect design but extended down into the surface to be more robust safe and reliable, which I might have pursued if I hadn't been so sick). I see people with a chunk of what, but they can't see any features, and I tell them to get the best
equipment and look for nanolayers of complexity, and that's what they have found now, and also with that patent. And I have to listen to everybody groan about how difficult it is, and what a genius Steve Jobs or other celebrities, were. But, they had
the money to do so much more. Some of them really care about people, which is something.

Now, I just described a system that is highly optimised generally, and has many features to this. Unless you are going to add a custom asic for each application, you are likely not optimised. Your processor is likely not optimised, except at being that
exact processor. But the processor here is more optimised in some form to what is being used (except in dsp and various other specialities). But on a cost benefit scale, it is a legitimate choice. That is in sales territory.

Life isn't fair, but it doesn't mean I have to love it.

So, let's be part of solutions, I have got enough people around at the moment, preventing me from getting on with life. Which doesn't really help anybody. Maybe you could use such a chip, as it's more optimal than a FPGA in certain applications.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

In article <874jzsc7tb.fsf@nightsong.com>,
Paul Rubin <no.email@nospam.invalid> wrote:

Wayne morellini <waynemorellini@gmail.com> writes:

Does anybody know if their are restrictions on short haul video
transmission to a in room tv via a tv digital channel, like they
allowed with analogue tv channels?

Nobody cares about that any more. Everyone has cable and TV sets have
HDMI inputs.

If one needs to generate an analogue tv signal, it could be done
on one of the io coprocessors in the raspberry pico.

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

In article <9c5abe4c-d255-43bd-b92b-7f0d9b2343bfn@googlegroups.com>,
Rick C <gnuarm.deletethisbit@gmail.com> wrote:
<SNIP>

As I've said, many, many times. Until you select a target application,
you won't be able to pick the optimal trade off between the many, many >factors involved.

I'm interested to read your comments, but could you please
snip the text you respond to.
Especially because Waynotelli doesnot restrict line length,
so that proper quoting doesn't work, and I'm tricked in reading
his text, again.

Rick C.

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 3:17:24 PM UTC-4, none albert wrote:

In article <9c5abe4c-d255-43bd...@googlegroups.com>,
Rick C <gnuarm.del...@gmail.com> wrote:
<SNIP>

As I've said, many, many times. Until you select a target application,
you won't be able to pick the optimal trade off between the many, many >factors involved.

I'm interested to read your comments, but could you please
snip the text you respond to.
Especially because Waynotelli doesnot restrict line length,
so that proper quoting doesn't work, and I'm tricked in reading
his text, again.

I'm more inclined to not reply at all. I have no idea what the guy is thinking. As soon as he starts to make a bit of sense, he goes back into wide open, doing everything while doing nothing mode. I can't find much to respond to.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Saturday, July 9, 2022 at 6:27:38 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Friday, July 8, 2022 at 3:17:24 PM UTC-4, none albert wrote:

In article <9c5abe4c-d255-43bd...@googlegroups.com>,
Rick C <gnuarm.del...@gmail.com> wrote:
<SNIP>

As I've said, many, many times. Until you select a target application, >you won't be able to pick the optimal trade off between the many, many >factors involved.

I'm interested to read your comments, but could you please
snip the text you respond to.
Especially because Waynotelli doesnot restrict line length,
so that proper quoting doesn't work, and I'm tricked in reading
his text, again.

I'm more inclined to not reply at all. I have no idea what the guy is thinking. As soon as he starts to make a bit of sense, he goes back into wide open, doing everything while doing nothing mode. I can't find much to respond to.

It's much to do with the talent of the reader. I certainly never have had 10-100x times more talented people react in such ways, usually the opposite. I have however had more talented, say they don't come here because of this behaviour. Viva le death
of Forth, guys.

One doesn't just obstinately dig a little tiny microscopic trench in obscure territory, and declare "There is no gold here!". You have to dig for it, everywhere you can, and declare what you actually can find with reason. Google groups is certainly an
issue. You can't seem to get through to them, and so the mobile view continues to have no reply icon for many years, and using the desktop version just flashes and jumps around as you try to edit things. So, you have to write it outside to speed up
writing many many times, and paste it back in, which is a real problem if the products don't handle compatibility issues between products in the pasting. So, I suggest you talk to them about how their system works. Go to the the menu system, and select
feedback. I'm certainly sick of doing it after a handful of times over the years, without much success but maybe if more took responsibility for talking to them, they would take responsibility for fixing things. Some groups do and change problems,
others don't. I mainly talk to the former.

You could also take responsibility for reading design factors. But where is your original thought to justify commenting and where is your responsibility for reading to understand. As I said, actual superior people don't act like I read here, they are
humble and read to understand, rather than not to dismiss. As I said, most better types will not turn up because of this. I get to communicate behind the scenes. But, this is virtually the only place to have discussion left so know of, and it's
dominated by deliberate disruption. As a certainly subgroup level of people always, seemingly, do on every technical forum on the internet. Only really naive people can't see past them. Raise your game. If you are going comment, comment rightly. I
certainly don't have time to address all the stuff wrongly raised to promote understanding. I woke sick today, and this has caused me to forget an urgent medical appointment. Better to be part of solutions, rather than problems.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 10:38:24 PM UTC-4, Wayne morellini wrote:

On Saturday, July 9, 2022 at 6:27:38 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Friday, July 8, 2022 at 3:17:24 PM UTC-4, none albert wrote:

In article <9c5abe4c-d255-43bd...@googlegroups.com>,
Rick C <gnuarm.del...@gmail.com> wrote:
<SNIP>

As I've said, many, many times. Until you select a target application, >you won't be able to pick the optimal trade off between the many, many >factors involved.

I'm interested to read your comments, but could you please
snip the text you respond to.
Especially because Waynotelli doesnot restrict line length,
so that proper quoting doesn't work, and I'm tricked in reading
his text, again.

I'm more inclined to not reply at all. I have no idea what the guy is thinking. As soon as he starts to make a bit of sense, he goes back into wide open, doing everything while doing nothing mode. I can't find much to respond to.

It's much to do with the talent of the reader. I certainly never have had 10-100x times more talented people react in such ways, usually the opposite. I have however had more talented, say they don't come here because of this behaviour. Viva le death

of Forth, guys.

One doesn't just obstinately dig a little tiny microscopic trench in obscure territory, and declare "There is no gold here!". You have to dig for it, everywhere you can, and declare what you actually can find with reason. Google groups is certainly an

issue. You can't seem to get through to them, and so the mobile view continues to have no reply icon for many years, and using the desktop version just flashes and jumps around as you try to edit things. So, you have to write it outside to speed up
writing many many times, and paste it back in, which is a real problem if the products don't handle compatibility issues between products in the pasting. So, I suggest you talk to them about how their system works. Go to the the menu system, and select
feedback. I'm certainly sick of doing it after a handful of times over the years, without much success but maybe if more took responsibility for talking to them, they would take responsibility for fixing things. Some groups do and change problems, others
don't. I mainly talk to the former.

You could also take responsibility for reading design factors. But where is your original thought to justify commenting and where is your responsibility for reading to understand. As I said, actual superior people don't act like I read here, they are

humble and read to understand, rather than not to dismiss. As I said, most better types will not turn up because of this. I get to communicate behind the scenes. But, this is virtually the only place to have discussion left so know of, and it's dominated
by deliberate disruption. As a certainly subgroup level of people always, seemingly, do on every technical forum on the internet. Only really naive people can't see past them. Raise your game. If you are going comment, comment rightly. I certainly don't
have time to address all the stuff wrongly raised to promote understanding. I woke sick today, and this has caused me to forget an urgent medical appointment. Better to be part of solutions, rather than problems.

As usual, you fail to understand. That's ok. I don't really care much about what you talk about. It's really just talk as far as I can tell. The fact that you waste your time responding with such long, involved posts when it's just to defend yourself,
in spite of your not caring what I say, says you do care a lot. The point being you are very easily distracted from whatever your goals are.

Stop being weird about what I post that you don't like. Ignore it. Then you will do much better here. Or waste your breath discussing what is not worth discussing and fail to get on with what ever it is you are trying to do.

What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well. I don't use Forth a lot. I have designed stack processors over the years and have some ideas I'd
like to work on, but have many other priorities at this time. My lack of experience with Forth actually holds me back in not being able to design a good software development tool for one of the processors I want to extend.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On 07/07/2022 14:58, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign.

Does that mean you've no experience of digital hardware design at all?
You're full of ideas on advanced features to incorporate into a
processor, if you've no experience how can you evaluate what is
practical or not?

Have you any significant experience of writing Forth software. If not
how can you devise a suitable instruction set and on-chip architecture
to support the language.

So, any resources out there useful simplified guide for doing a simple
1000 transistor plus core, and designs for memory, rom and storage
memory, on the same process? I only am looking at this because I learnt
the basics of digital electronic circuit design, and it shouldn't be any
more difficult, with the right software

I've heard that sort of statement said before until reality hits.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

No doubt you'll interpret this as negativity, but some negativity is
part of the design process, e.g. you design something and should ask
yourself "why won't this work" - both for hardware and software.

--
Gerry

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Fri, 8 Jul 2022 10:00:52 -0700 (PDT)
Wayne morellini <waynemorellini@gmail.com> wrote:
[]
[Teacher] told us that perpetual motion machines weren't possible, giving the spinning axis motion stuff. Within 30 seconds I came up with a way it could be fine, and with 15 minutes or so, how to do it with conventional technology, and within 45
minutes, after class, I concluded it would disrupt the economy and energy sectors, and decided it wasn't a good idea. It seems related to other ones out there. I used to annotate what was wrong with
[]

Wait: you've invent a PMM and won't tell us?

--
Bah, and indeed Humbug.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Saturday, July 9, 2022 at 8:16:56 PM UTC+10, Kerr-Mudd, John wrote:

On Fri, 8 Jul 2022 10:00:52 -0700 (PDT)
Wayne morellini <waynemo...@gmail.com> wrote:
[]
[Teacher] told us that perpetual motion machines weren't possible, giving the spinning axis motion stuff. Within 30 seconds I came up with a way it could be fine, and with 15 minutes or so, how to do it with conventional technology, and within 45

minutes, after class, I concluded it would disrupt the economy and energy sectors, and decided it wasn't a good idea. It seems related to other ones out there. I used to annotate what was wrong with

[]

Wait: you've invent a PMM and won't tell us?

--
Bah, and indeed Humbug.

Yes. It's a misunderstanding of science. But when you say it like that.. We even had a local guy here decades latter, that lived on the same street as a freind, who was famous for inventing something, but it guess nowhere, and people died. Just saw a
video last night of somebody making a device from an old oil company patent, trying to prove to everybody it has no this that or the other. I'm sitting there also going, what about this that or other other" way of faking it. They covered most areas in
the video, but not remote projection of electrical energy, and can't convince me they couldn't have hidden a power storage device. But, not everybody is dishonest. I took a careful look at the asymmetrical factors in the design, which is part of the
trick. It's all a bit, most guys die unusually, who design these things (which seems to actually
be the case) so we don't want to reveal the complete secret until we hit 100 million subscribers. But, the we don't want to get sued for copying a 50 years old patent, is what gets me. Unless there is a special classification of military classified
patent I don't know of, these people should know that dyes t make sense, which might be a strong indicator of a fake. I used to examine sceptic claims for validity (often very fanciful people, looking for what they want to find to discredit instead of
objectivity). The only way these sorts of things can work is a trick that violates normal symmetry of reactions. There are many failings in science, such as the notion of quantum randomness and symmetry leading to completely reversible reactions sets.
If you have a complete set of reversible symmetrical reactions then you can't have true reversibility, unless you have time reversibility. Which brings up another whole can of worms to do with the generation of matter and interaction with gravitational,
and other, forces in a time stream, depending on how things actually work. Anyway, scientifically, further discoveries will sort things out. Some of these theories are stranger than fiction, and even in science fiction, there are a number of key
technologies ideas actually covered from historical stories (I do some mild archeological/anthropological information into earliest layers of history where these things happen to be copied from. That's how I'm aware of them. You will find high
intelligence capable workers, have an interest in interesting things in general). You get to a level, where people are interested in understanding and exploring sets of information, which less intelligent people are not good at, but merely opinionated
about part information as the limit of things. Really bad. An intellectual explorer will at least try to understand the limits of information, even if they can't come up with the information themselves. Believe me, I know people who believe all sorts
of things, and apart from put up with their antics, have to tell them why it can't be true (the actual limits of what can be true, but what do I know, you find things are different than what you think at times. We have these holographic universe experts
running around, and I point to local independent interaction of forces unless there is a method of remote local interactions, which sub implied a way to instantly interact over distance, or speed limits (maybe implying that light is speed limited by
remote interaction speed. But, it is all "if"'s is these hypothesis. Lost my train of thought, a new message notification turned up. I point to diffuse information at distance not interacting. So, you get to need a different version of such a theory,
to work, and or local interactions. I'm theorising a local local model.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 8, 2022 at 9:15:14 AM UTC-4, Wayne morellini wrote:

impractical for very small portable devices. That's why I'm trying to come up with a HDMI attached relay alternative, but in the >meantime digital TV signal is an existing standard that can be adopted in. It's all very messy, but a digital tv signal is

a >compromise.. do, the question was, what restrictions are there.

You might be late for that product concept...

https://www.amazon.ca/Dummy-Headless-Display-Emulator-Generation/dp/B07FB4VJL9/ref=asc_df_B07FB4VJL9/?tag=googleshopc0c-20&linkCode=df0&hvadid=335118530598&hvpos=&hvnetw=g&hvrand=12878053212799315034&hvpone=&hvptwo=&hvqmt=&hvdev=c&hvdvcmdl=&hvlocint=&
hvlocphy=9001065&hvtargid=pla-901877952212&th=1

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Saturday, July 9, 2022 at 10:00:09 PM UTC+10, Kerr-Mudd, John wrote:

On Sat, 9 Jul 2022 04:34:27 -0700 (PDT)
Wayne morellini <waynemo...@gmail.com> wrote:

On Saturday, July 9, 2022 at 8:16:56 PM UTC+10, Kerr-Mudd, John wrote:

On Fri, 8 Jul 2022 10:00:52 -0700 (PDT)
Wayne morellini <waynemo...@gmail.com> wrote:
[]
[Teacher] told us that perpetual motion machines weren't possible, giving the spinning axis motion stuff. Within 30 seconds I came up with a way it could be fine, and with 15 minutes or so, how to do it with conventional technology, and within 45

minutes, after class, I concluded it would disrupt the economy and energy sectors, and decided it wasn't a good idea. It seems related to other ones out there. I used to annotate what was wrong with

[]

Wait: you've invent a PMM and won't tell us?

--
Bah, and indeed Humbug.

Yes. It's a misunderstanding of science. But when you say it like that.. We even had a local guy here decades latter, that lived on the same street as a freind, who was famous for inventing something, but it guess nowhere, and people died. Just saw a

video last night of somebody making a device from an old oil company patent, trying to prove to everybody it has no this that or the other. I'm sitting there also going, what about this that or other other" way of faking it. They covered most areas in
the video, but not remote projection of electrical energy, and can't convince me they couldn't have hidden a power storage device. But, not everybody is dishonest. I took a careful look at the asymmetrical factors in the design, which is part of the
trick. It's all a bit, most guys die unusually, who design these things (which seems to actually

be the case) so we don't want to reveal the complete secret until we hit 100 million subscribers. But, the we don't want to get sued for copying a 50 years old patent, is what gets me. Unless there is a special classification of military classified

patent I don't know of, these people should know that dyes t make sense, which might be a strong indicator of a fake. I used to examine sceptic claims for validity (often very fanciful people, looking for what they want to find to discredit instead of
objectivity). The only way these sorts of things can work is a trick that violates normal symmetry of reactions. There are many failings in science, such as the notion of quantum randomness and symmetry leading to completely reversible reactions sets. If
you have a complete set of reversible symmetrical reactions then you can't have true reversibility, unless you have time reversibility. Which brings up another whole can of worms to do with the generation of matter and interaction with gravitational, and
other, forces in a time stream, depending on how things actually work. Anyway, scientifically, further discoveries will sort things out. Some of these theories are stranger than fiction, and even in science fiction, there are a number of key technologies
ideas actually covered from historical stories (I do some mild archeological/anthropological information into earliest layers of history where these things happen to be copied from. That's how I'm aware of them. You will find high intelligence capable
workers, have an interest in interesting things in general). You get to a level, where people are interested in understanding and exploring sets of information, which less intelligent people are not good at, but merely opinionated about part information
as the limit of things. Really bad. An intellectual explorer will at least try to understand the limits of information, even if they can't come up with the information themselves. Believe me, I know people who believe all sorts of things, and apart from
put up with their antics, have to tell them why it can't be true (the actual limits of what can be true, but what do I know, you find things are different than what you think at times. We

Wow.
have these holographic universe experts running around, and I point to local independent interaction of forces unless there is a method of remote local interactions, which sub implied a way to instantly interact over distance, or speed limits (maybe

implying that light is speed limited by remote interaction speed. But, it is all "if"'s is these hypothesis. Lost my train of thought, a new message notification turned up. I point to diffuse information at distance not interacting. So, you get to need a
different version of such a theory, to work, and or local interactions. I'm theorising a local local model.

But sometimes, and maybe especially here in this NG, you have to get down and apply things.

Sorry. You lost me. How does that apply to the paragraph it was applied to?

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Sat, 9 Jul 2022 04:34:27 -0700 (PDT)
Wayne morellini <waynemorellini@gmail.com> wrote:

On Saturday, July 9, 2022 at 8:16:56 PM UTC+10, Kerr-Mudd, John wrote:

On Fri, 8 Jul 2022 10:00:52 -0700 (PDT)
Wayne morellini <waynemo...@gmail.com> wrote:
[]
[Teacher] told us that perpetual motion machines weren't possible, giving the spinning axis motion stuff. Within 30 seconds I came up with a way it could be fine, and with 15 minutes or so, how to do it with conventional technology, and within 45

minutes, after class, I concluded it would disrupt the economy and energy sectors, and decided it wasn't a good idea. It seems related to other ones out there. I used to annotate what was wrong with

[]

Wait: you've invent a PMM and won't tell us?

--
Bah, and indeed Humbug.

Yes. It's a misunderstanding of science. But when you say it like that.. We even had a local guy here decades latter, that lived on the same street as a freind, who was famous for inventing something, but it guess nowhere, and people died. Just saw

a video last night of somebody making a device from an old oil company patent, trying to prove to everybody it has no this that or the other. I'm sitting there also going, what about this that or other other" way of faking it. They covered most areas
in the video, but not remote projection of electrical energy, and can't convince me they couldn't have hidden a power storage device. But, not everybody is dishonest. I took a careful look at the asymmetrical factors in the design, which is part of the
trick. It's all a bit, most guys die unusually, who design these things (which seems to actually

be the case) so we don't want to reveal the complete secret until we hit 100 million subscribers. But, the we don't want to get sued for copying a 50 years old patent, is what gets me. Unless there is a special classification of military classified

patent I don't know of, these people should know that dyes t make sense, which might be a strong indicator of a fake. I used to examine sceptic claims for validity (often very fanciful people, looking for what they want to find to discredit instead of
objectivity). The only way these sorts of things can work is a trick that violates normal symmetry of reactions. There are many failings in science, such as the notion of quantum randomness and symmetry leading to completely reversible reactions sets.
If you have a complete set of reversible symmetrical reactions then you can't have true reversibility, unless you have time reversibility. Which brings up another whole can of worms to do with the generation of matter and interaction with gravitational,
and other, forces in a time stream, depending on how things actually work. Anyway, scientifically, further discoveries will sort things out. Some of these theories are stranger than fiction, and even in science fiction, there are a number of key
technologies ideas actually covered from historical stories (I do some mild archeological/anthropological information into earliest layers of history where these things happen to be copied from. That's how I'm aware of them. You will find high
intelligence capable workers, have an interest in interesting things in general). You get to a level, where people are interested in understanding and exploring sets of information, which less intelligent people are not good at, but merely opinionated
about part information as the limit of things. Really bad. An intellectual explorer will at least try to understand the limits of information, even if they can't come up with the information themselves. Believe me, I know people who believe all sorts
of things, and apart from put up with their antics, have to tell them why it can't be true (the actual limits of what can be true, but what do I know, you find things are different than what you think at times. We

Wow.

have these holographic universe experts running around, and I point to local independent interaction of forces unless there is a method of remote local interactions, which sub implied a way to instantly interact over distance, or speed limits (maybe
implying that light is speed limited by remote interaction speed. But, it is all "if"'s is these hypothesis. Lost my train of thought, a new message notification turned up. I point to diffuse information at distance not interacting. So, you get to
need a different version of such a theory, to work, and or local interactions. I'm theorising a local local model.

But sometimes, and maybe especially here in this NG, you have to get down and apply things.

(He says, still unable to get a proper understanding of Forth; yes I've looked at 'Starting Forth', and I'm ok with simple stack stuff, but it seems one has to know a lot of 'words' before you^I can understand a program.

--
Bah, and indeed Humbug.

--- SoupGate-Win32 v1.05
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On Saturday, July 9, 2022 at 9:25:03 PM UTC+10, Brian Fox wrote:

On Friday, July 8, 2022 at 9:15:14 AM UTC-4, Wayne morellini wrote:

impractical for very small portable devices. That's why I'm trying to come up with a HDMI attached relay alternative, but in the >meantime digital TV signal is an existing standard that can be adopted in. It's all very messy, but a digital tv signal

is a >compromise.. do, the question was, what restrictions are there.

You might be late for that product concept...

https://www.amazon.ca/Dummy-Headless-Display-Emulator-Generation/dp/B07FB4VJL9/ref=asc_df_B07FB4VJL9/?tag=googleshopc0c-20&linkCode=df0&hvadid=335118530598&hvpos=&hvnetw=g&hvrand=12878053212799315034&hvpone=&hvptwo=&hvqmt=&hvdev=c&hvdvcmdl=&hvlocint=&

hvlocphy=9001065&hvtargid=pla-901877952212&th=1

That's a dummy plug, but want a wireless link from device to a plug like this, eventually, down the track. At the moment, a digital tv signal requires no device sales or manufacture and certification, just the original chip set up a manufacturer would
certify with their device device side, and auto compatability, and maybe a antenna splitter and small aerial. The broadcast people should have made something like this in the standard.

--- SoupGate-Win32 v1.05
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On 7/9/22 6:34 AM, Wayne morellini wrote:

Yes. It's a misunderstanding of science.

On your part.

If it were possible to create a PMM, someone would have done it long
ago. It isn't like people aren't trying in spite of the science. In
order for it to work, big chunks of science as known and applied every
day has to be wrong.


https://web.archive.org/web/20171112054010/http://www.lhup.edu:80/~dsimanek/museum/unwork.htm

--
http://davesrocketworks.com
David Schultz

--- SoupGate-Win32 v1.05
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On Saturday, July 9, 2022 at 4:06:58 PM UTC+10, Gerry Jackson wrote:

On 07/07/2022 14:58, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign.

Does that mean you've no experience of digital hardware design at all? You're full of ideas on advanced features to incorporate into a
processor, if you've no experience how can you evaluate what is
practical or not?

I didn't say either. You study this stuff, and forget a lot of it, but it's fairly simple concepts. Which is how people design CPU's on bread boards with active high res video graphics even. Analogue is a lot harder but still deceptively oversimplified,
actually working according to Maxwell Equations etc, and here require other quantum effects and material sciences at chemistry. So, I'm just looking at high level digital design (why you think I want to use GA's Glow, or Okad, if a high school kid can
use it. I should be good. The analogue sections are going require a bit of study, and others some trial and error tests based on basic knowledge of the shape and action of of effects. Basically, all else fails then existing DAC and ADC circuits would
stand in for less performance. So, yes, it might not turn out ideal, but some future version could take that over in an open design. Mostly, you are using simple existing circuit examples. I was originally actually thinking if all else failed, to
just have selectable circuits for different levels on each pin. Just some common levels.

Any descent princess is going have models for all these circuit events.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

No doubt you'll interpret this as negativity, but some negativity is
part of the design process, e.g. you design something and should ask yourself "why won't this work" - both for hardware and software.

That is just reality. The next question, is how do you make it work, otherwise you won't be very good at it. You have weigh up everything. Why do you think I'm working from simplest down. Nobody else here is bothering to do anything. The basic set
of forth language and misc words were worked out a long time ago (though multiplication is one thing I would like). To get extra code density or performance, you have to figure out how to design the ISA to perform this set of functions. But here, I'm
looking at using a subset of those as straight forwards opcodes, with a few opcodes replaced by by the counter DMA system, and one of my ISA techniques. The thing about the negative people around here, when their objectives aren't sincere, they can act
like answering their negativity realistically, is negative, producing a lot of "noise", from outside interference. I don't think I've ever seen such negative comments from anybody I respect that actually designs silicon. :( Virtually none come here
anymore. Just ignore their fantasy. It's slow methodical process, and I will ask about things beyond my knowledge.

--- SoupGate-Win32 v1.05
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On Saturday, July 9, 2022 at 10:46:17 PM UTC+10, David Schultz wrote:

On 7/9/22 6:34 AM, Wayne morellini wrote:

Yes. It's a misunderstanding of science.

On your part.

If it were possible to create a PMM, someone would have done it long
ago. It isn't like people aren't trying in spite of the science. In
order for it to work, big chunks of science as known and applied every
day has to be wrong.

https://web.archive.org/web/20171112054010/http://www.lhup.edu:80/~dsimanek/museum/unwork.htm
--
http://davesrocketworks.com
David Schultz

There is a lot wrong with the rational logic of these things. We don't have absolute complete proofs of the basics of science. It's portrayed as complete by people following charlatans. We have a version of symmetry that seems to work, but the formula
is not the answer, it's only a possible answer. So, within limitations, there is the possibility for the universe to operate in a non leaky fashion, but also to leak. There is a fundamental illogical problem with all this. Most all these pmm are not
going work, as it used nothing that can get around the loss of energy out of the system, let alone generate an excess. I point this out to people. But there is a certain category that could work, and it seems some people have independently come up with
mechanisms that add up to the same effect to achieve it That's the ones I'm interested in. But, things are run by people who have certain types of noisy people following them. 8f you can't talk about doing a new forth processor, then what hope do you
have to do this sort of thing. We actually get intel (not the company) people turn up and threaten people working on less problemed things then this. I've known people on the other side of things, and a lot happens people don't know about. They are
interested in team players, so be team players. You don't have to be on their team necessarily, but out of the way. :). A forth processor is ok.

--- SoupGate-Win32 v1.05
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On Saturday, July 9, 2022 at 8:00:09 AM UTC-4, Kerr-Mudd, John wrote:

But sometimes, and maybe especially here in this NG, you have to get down and apply things.

New here, huh? This has been going on for a while in many posts, across many threads.

(He says, still unable to get a proper understanding of Forth; yes I've looked at 'Starting Forth', and I'm ok with simple stack stuff, but it seems one has to know a lot of 'words' before you^I can understand a program.

Welcome to the club. You don't need to know the words inside out (although that helps), but simply know the word exists and have an idea of it's name. I spend a lot of time reading the standard to find words when I start a new project because it's
always been so long since the last one. However, because of the eccentric names in Forth, it can be hard to use the search feature in a Forth document. Try searching on any one-character word name. You will get a hit on every second page.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Saturday, July 9, 2022 at 9:20:43 AM UTC-4, Wayne morellini wrote:

On Saturday, July 9, 2022 at 4:06:58 PM UTC+10, Gerry Jackson wrote:

On 07/07/2022 14:58, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign.

Does that mean you've no experience of digital hardware design at all? You're full of ideas on advanced features to incorporate into a
processor, if you've no experience how can you evaluate what is
practical or not?

I didn't say either. You study this stuff, and forget a lot of it, but it's fairly simple concepts. Which is how people design CPU's on bread boards with active high res video graphics even. Analogue is a lot harder but still deceptively oversimplified,

actually working according to Maxwell Equations etc, and here require other quantum effects and material sciences at chemistry. So, I'm just looking at high level digital design (why you think I want to use GA's Glow, or Okad, if a high school kid can
use it. I should be good. The analogue sections are going require a bit of study, and others some trial and error tests based on basic knowledge of the shape and action of of effects. Basically, all else fails then existing DAC and ADC circuits would
stand in for less performance. So, yes, it might not turn out ideal, but some future version could take that over in an open design. Mostly, you are using simple existing circuit examples. I was originally actually thinking if all else failed, to just
have selectable circuits for different levels on each pin. Just some common levels.

Any descent princess is going have models for all these circuit events.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

No doubt you'll interpret this as negativity, but some negativity is
part of the design process, e.g. you design something and should ask yourself "why won't this work" - both for hardware and software.

That is just reality. The next question, is how do you make it work, otherwise you won't be very good at it. You have weigh up everything. Why do you think I'm working from simplest down. Nobody else here is bothering to do anything.

That is mostly because no one understands what you are talking about.

The basic set of forth language and misc words were worked out a long time ago (though multiplication is one thing I would like). To get extra code density or performance, you have to figure out how to design the ISA to perform this set of functions.

But here, I'm looking at using a subset of those as straight forwards opcodes, with a few opcodes replaced by by the counter DMA system, and one of my ISA techniques. The thing about the negative people around here, when their objectives aren't sincere,
they can act like answering their negativity realistically, is negative, producing a lot of "noise", from outside interference. I don't think I've ever seen such negative comments from anybody I respect that actually designs silicon. :( Virtually none
come here anymore. Just ignore their fantasy. It's slow methodical process, and I will ask about things beyond my knowledge.

This is a Forth group. How many chip designers have ever posted here? Not many.

What I don't understand is why you spend so much time responding to posts here, rather than gittin' 'er done?

Have you done any work at all on whatever it is that you want to design?

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On 9/07/2022 22:46, David Schultz wrote:

If it were possible to create a PMM, someone would have done it long
ago. It isn't like people aren't trying in spite of the science. In
order for it to work, big chunks of science as known and applied every
day has to be wrong.

Surely it's possible for someone to make a $billion where nobody loses.
It's the principle upon which our economic system runs.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Saturday, July 9, 2022 at 2:45:48 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Friday, July 8, 2022 at 10:38:24 PM UTC-4, Wayne morellini wrote:

On Saturday, July 9, 2022 at 6:27:38 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Friday, July 8, 2022 at 3:17:24 PM UTC-4, none albert wrote:

In article <9c5abe4c-d255-43bd...@googlegroups.com>,
Rick C <gnuarm.del...@gmail.com> wrote:

..

As usual, you fail to understand. That's ok. I don't really care much about what you talk about. It's really just talk as far as I can tell. The fact that you waste your time responding with such long, involved posts when it's just to defend yourself,

in spite of your not caring what I say, says you do care a lot. The point being you are very easily distracted from whatever your goals are.

No, it's you. Don't twist this up again. I'm still on objective, as per usual, as can be shown everytime you come along. You are still on about a countering objective. I care about the truth and good pursuit, and when somebody comes along and tries
to counter truth, of course I'm going say something. It's my place to counter trolling attempts and untwist things for other readers, which trolls know and why they try to say things that require longer answers to untwist. A troll is ultimately an
inferior intelligence, that instead of fit in, stalks for other reasons. And reverts to this behaviour a lot. Despite what some people do, I don't go around doing that, I tend to keep away, which is why they always get in your face with rubbish in order
to produce replies to them. You can't run a progressive technical thread without addressing nonsense disruption that decieve things.

Stop being weird about what I post that you don't like. Ignore it. Then you will do much better here. Or waste your breath discussing what is not worth discussing and fail to get on with what ever it is you are trying to do.

It's actually you making weird illogical comments to disrupt.

What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well. I don't use Forth a lot. I have designed stack processors over the years and have some ideas I'd

like to work on, but have many other priorities at this time. My lack of experience with Forth actually holds me back in not being able to design a good software development tool for one of the processors I want to extend.

Ok, so you don't really know what you are talking about, and are not naming any adequate forth stack processor design or saying the stack designs were forth ones, where you say you are not familiar with Forth. One can throw an egg at a pot and claim to
know how to make scrambled eggs and that others who can design a recipe don't know. Between the two of us, who is the one coming with irrational illogical statements following and hassling better people around who do have an idea? Where have you ever
given evidence you have a mind good in design thinking or logic?

The continuous rubbish about shorting the design process for a general purpose processor to be more specialist, was a give away.

--- SoupGate-Win32 v1.05
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On Sunday, July 10, 2022 at 12:04:53 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Saturday, July 9, 2022 at 8:00:09 AM UTC-4, Kerr-Mudd, John wrote:

But sometimes, and maybe especially here in this NG, you have to get down and apply things.

New here, huh? This has been going on for a while in many posts, across many threads.

Kerr-Mudd, when you do something, or try to do something, there are people who act unsatisfied. Such people don't see real design work as work. It's all about them. If you get rid of them, everybody will be happier and things might get done... Instead
of scaring away good people. Such nutters shouldn't be allowed on the internet, or in our business. But, this is the newsgroups, unmoderated, people with no real.interest, function or source of support, coming in to disrupt, like they are somehow
important, without actually being so, with nothing to offer.

--- SoupGate-Win32 v1.05
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On Sunday, July 10, 2022 at 12:11:19 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Saturday, July 9, 2022 at 9:20:43 AM UTC-4, Wayne morellini wrote:

On Saturday, July 9, 2022 at 4:06:58 PM UTC+10, Gerry Jackson wrote:

On 07/07/2022 14:58, Wayne morellini wrote:

That is mostly because no one understands what you are talking about.

Be truthful. I have never known you to be intelligent, or are you pretending?

What I don't understand is why you spend so much time responding to posts here,

Because of the disruptive deception trying to undermine good work.

--- SoupGate-Win32 v1.05
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Well. It looks like another 3 to 4 hours of life wasted by people with nothing to do, but complain that things are not happening, while stopping people from doing urgent things, stopping them from doing things, as they actually are trying to do them.
Which is strange.

--- SoupGate-Win32 v1.05
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On Saturday, July 9, 2022 at 11:33:53 AM UTC-4, Wayne morellini wrote:

Well. It looks like another 3 to 4 hours of life wasted by people with nothing to do, but complain that things are not happening, while stopping people from doing urgent things, stopping them from doing things, as they actually are trying to do them.

Which is strange.

No one is complaining. Just pointing out the facts. I don't especially care what you do with your life. If you are not getting anything done, that is not because of me. That is purely on you.

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Sunday, July 10, 2022 at 12:18:40 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Saturday, July 9, 2022 at 11:19:12 AM UTC-4, Wayne morellini wrote:

On Sunday, July 10, 2022 at 12:11:19 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Saturday, July 9, 2022 at 9:20:43 AM UTC-4, Wayne morellini wrote:

On Saturday, July 9, 2022 at 4:06:58 PM UTC+10, Gerry Jackson wrote:

On 07/07/2022 14:58, Wayne morellini wrote:

That is mostly because no one understands what you are talking about.

Be truthful. I have never known you to be intelligent, or are you pretending?

What I don't understand is why you spend so much time responding to posts here,

Because of the disruptive deception trying to undermine good work.

Ah, I get it now. Paranoia. Whether or not anyone is "trying to undermine" your work, there's nothing anyone can do. These are just words thrown across the aether and have no impact unless someone reads them and takes them to heart. They can be read

and ignored, or just ignored and they have no impact.

Whatever. It's a rainy Saturday and I'm just waiting for my dinner to cook. Opps, I waited too long to hit send and the rain came roaring back, so the sat signal will be lost. This message will have to wait to be posted.

What an idiot. I care about good work in general, if you don't, that's up to you, but go away and don't come back to any place. Deception has great usefulness in undermining efforts. What you just said is deception, and the record shows you
irrationally interfering in other's threads. You are just irrelevant.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

You run Arius, or are you somebody pretending to be that person? It's extremely strange behaviour for somebody is business to be doing this for years, or days.
https://www.arius.com/

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Sunday, July 10, 2022 at 8:41:59 PM UTC-4, Wayne morellini wrote:

You run Arius, or are you somebody pretending to be that person? It's extremely strange behaviour for somebody is business to be doing this for years, or days.
https://www.arius.com/

Yes, it is a bit odd to bother with someone who is playing around with processor designs, or more accurately, playing around with the idea of designing a processor.

Whatever. I just finished my shrimp dinner and was checking for something interested in this group. I guess that will need to wait a while longer.

So what is your next step on the road to your stack processor? Or are you just going to harangue me as your only accomplishment today?

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Sunday, July 10, 2022 at 12:18:52 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Saturday, July 9, 2022 at 11:33:53 AM UTC-4, Wayne morellini wrote:

Well. It looks like another 3 to 4 hours of life wasted by people with nothing to do, but complain that things are not happening, while stopping people from doing urgent things, stopping them from doing things, as they actually are trying to do them.

Which is strange.

No one is complaining. Just pointing out the facts. I don't especially care what you do with your life. If you are not getting anything done, that is not because of me. That is purely on you.

It's all on the record for your Arius customers to read.

https://www.arius.com/

You complaining I am not doing anything after just wasting hundreds of hours pestering. Maybe you should find a real life.. Your "facts" are often not really facts just some mistaken/deluded illogic. You have hardly ever contributed anything of real
worth, but a lot of harm. So, be honest, stop acting nutty, and behave yourself or begone. Very simple, but like most things you irrationally don't get it.

Is this how you conduct yourself?

We also note, you haven't designed any stack forth processors, but only mention stacks in some attempt to make yourself look knowledgeable, but still unable to logically speak in terms of design language. We also note, that rather than correctly address
what has been said, or apologize for each mistake, you go on the attack. Now, why should we hear you in other people's thread going on like a chook that doesn't know the difference between a stone and grain attacking people?

--- SoupGate-Win32 v1.05
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On Monday, July 11, 2022 at 10:59:31 AM UTC+10, gnuarm.del...@gmail.com wrote: ..

Yes, it is a bit odd to bother with someone who is playing around with processor designs, or more accurately, playing around with the idea of designing a processor.

Whatever. I just finished my shrimp dinner and was checking for something interested in this group. I guess that will need to wait a while longer.

So what is your next step on the road to your stack processor? Or are you just going to harangue me as your only accomplishment today?

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

As we can all see, this is deceptive, as this is the research and discussion portion of design, and I often am harangued around here, faced with strange diversionary comments and questions
I had hoped for change.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 7, 2022 at 11:58:39 PM UTC+10, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor

plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

Thanks again.

Wayne.

Ok. There has been too many repeated attempts to interfere with business of things, which were invalid. This will probably have to go to a closed group eventually for security, and, as the design is at risk itself from interference, potentially open
source license that includes only limited parties, for security, and nobody that does business outside of those parties could use. I do hope to eventually displace most all FPGA, that doesn't have a license, which would lower amortisation per unit.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 9:28:22 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Monday, July 11, 2022 at 6:05:45 PM UTC-4, Wayne morellini wrote:

On Monday, July 11, 2022 at 10:59:31 AM UTC+10, gnuarm.del...@gmail.com wrote:
..

Yes, it is a bit odd to bother with someone who is playing around with processor designs, or more accurately, playing around with the idea of designing a processor.

Whatever. I just finished my shrimp dinner and was checking for something interested in this group. I guess that will need to wait a while longer.

So what is your next step on the road to your stack processor? Or are you just going to harangue me as your only accomplishment today?

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

As we can all see, this is deceptive, as this is the research and discussion portion of design, and I often am harangued around here, faced with strange diversionary comments and questions
I had hoped for change.

Anything that is not productive, you can ignore. Why do you continue to participate in non-productive conversations??? I don't understand you at all.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

Everybody. Here is another one. Participating, and starting non productive conversations, now accuses the one who has to deal with them in order to keep things on track and address falsehoods. What is evident, is that the one producing such disruption,
should review their own usefulness.

Please also note, how when shown wrong, they divert and change to something else, and when nothing note worthy sounding, can be said, these sort of statements are used. Also note, that when their business is pointed out, suddenly they become more
reserved. If the way they act and what they say, is valid, then why does it matter?

Please note, this person has been wasting many hours, weeks and years, dragging themselves into such "non-productive conversations" wasting their time.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 8:27:17 AM UTC+10, Wayne morellini wrote:

On Thursday, July 7, 2022 at 11:58:39 PM UTC+10, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000

transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

Thanks again.

Wayne.

Ok. There has been too many repeated attempts to interfere with business of things, which were invalid. This will probably have to go to a closed group eventually for security, and, as the design is at risk itself from interference, potentially open

source license that includes only limited parties, for security, and nobody that does business outside of those parties could use. I do hope to eventually displace most all FPGA, that doesn't have a license, which would lower amortisation per unit.


I sincerely thank everybody who has been of help here for their help. This is going take a while before I can devote time to it exclusively. At the moment, it is still preliminary. Can anybody suggest a venue with web like interface, where I can run
an invitation only, or barring, discussion? There has been too much harrasment over the years, and evidently faux claims of truth used, to anybody with skill and talent. We must view the design process as the rain drops, in this time of (large) designs
which are floods. Many rain drops, make a flood. Just reviewing the SBC maker space, there is very good room, for a better form factor and platform. It is evident, that there is major advantages to such a design in 16 and 32 bits, even in 4 or 8 bit
versions.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Monday, July 11, 2022 at 6:05:45 PM UTC-4, Wayne morellini wrote:

On Monday, July 11, 2022 at 10:59:31 AM UTC+10, gnuarm.del...@gmail.com wrote:
..

Yes, it is a bit odd to bother with someone who is playing around with processor designs, or more accurately, playing around with the idea of designing a processor.

Whatever. I just finished my shrimp dinner and was checking for something interested in this group. I guess that will need to wait a while longer.

So what is your next step on the road to your stack processor? Or are you just going to harangue me as your only accomplishment today?

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

As we can all see, this is deceptive, as this is the research and discussion portion of design, and I often am harangued around here, faced with strange diversionary comments and questions
I had hoped for change.

Anything that is not productive, you can ignore. Why do you continue to participate in non-productive conversations??? I don't understand you at all.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Monday, July 11, 2022 at 8:00:26 PM UTC-4, Wayne morellini wrote:

On Tuesday, July 12, 2022 at 9:28:22 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Monday, July 11, 2022 at 6:05:45 PM UTC-4, Wayne morellini wrote:

On Monday, July 11, 2022 at 10:59:31 AM UTC+10, gnuarm.del...@gmail.com wrote:
..

Yes, it is a bit odd to bother with someone who is playing around with processor designs, or more accurately, playing around with the idea of designing a processor.

Whatever. I just finished my shrimp dinner and was checking for something interested in this group. I guess that will need to wait a while longer.

So what is your next step on the road to your stack processor? Or are you just going to harangue me as your only accomplishment today?

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

As we can all see, this is deceptive, as this is the research and discussion portion of design, and I often am harangued around here, faced with strange diversionary comments and questions
I had hoped for change.

Anything that is not productive, you can ignore. Why do you continue to participate in non-productive conversations??? I don't understand you at all.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

Everybody. Here is another one. Participating, and starting non productive conversations, now accuses the one who has to deal with them in order to keep things on track and address falsehoods. What is evident, is that the one producing such disruption,

should review their own usefulness.

In this regard, you fit in perfectly here. We used to have a Mad Max type who would argue with anyone at the drop of a hat. Then we have Juergen and Peter Forth (haven't seen much of him lately) who would burn down the woods to save the animals or
whatever analogy is appropriate for someone who creates a greater disturbance than the person he is arguing with.

Absolutely nothing I've posted at any time deserves any response from you if you don't want to discuss the matter. Anyone reading YOUR posts can judge for themselves what they think of your ideas. Responding to my posts does nothing to change what you
have already written.

Please also note, how when shown wrong, they divert and change to something else, and when nothing note worthy sounding, can be said, these sort of statements are used. Also note, that when their business is pointed out, suddenly they become more

reserved. If the way they act and what they say, is valid, then why does it matter?

Please note, this person has been wasting many hours, weeks and years, dragging themselves into such "non-productive conversations" wasting their time.

What have I said that I am "wrong" about? Why do you continue to rail about my posts when, at this point, they are pretty much all about the fact that you can't help yourself from responding?

I'm ordering you to stop responding to my posts!!!

Actually, I was conversing with someone else when you replied to me. So don't act like I did anything wrong by replying to YOUR post to me.

Yes, indeed. I think you are just the right level of crazy to be in this group.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 10:38:33 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Monday, July 11, 2022 at 8:00:26 PM UTC-4, Wayne morellini wrote:

..

Everybody. Here is another one. Participating, and starting non productive conversations, now accuses the one who has to deal with them in order to keep things on track and address falsehoods. What is evident, is that the one producing such

disruption, should review their own usefulness.

In this regard, you fit in perfectly here. We used to have a Mad Max type who would argue with anyone at the drop of a hat. Then we have Juergen and Peter Forth (haven't seen much of him lately) who would burn down the woods to save the animals or

whatever analogy is appropriate for someone who creates a greater disturbance than the person he is arguing with.

Another twist. Here we have somebody starting disruption from no disruption, at the proverbial drop of a hat, he would say, destroying the threads to save the wild beasts of opinion, or something.

Absolutely nothing I've posted

Is correct? I wouldn't say that, I'm sure some things you posted were correct.

at any time deserves any response from you..

Oh! Well, yes! If it was just to me I could just ignore everything you say, but we have to save the minds of all those little woodland creatures of yours! They might get confused, and start thinking a Z80 is a Transputer, or something!
.

Please also note, how when shown wrong, they divert and change to something else, and when nothing note worthy sounding, can be said, these sort of statements are used. Also note, that when their business is pointed out, suddenly they become more

reserved. If the way they act and what they say, is valid, then why does it matter?

Please note, this person has been wasting many hours, weeks and years, dragging themselves into such "non-productive conversations" wasting their time.

What have I said that I am "wrong" about? Why do you continue to rail about my posts when, at this point, they are pretty much all about the fact that you can't help yourself from responding?

I'm ordering you to stop responding to my posts!!!

I'm sure, I speak for others here, after a very long time: Piss off! Rick, stop interfering with threads and posting responses to do so. Get a real life and start working instead.
..

Yes, indeed. I think you are just the right level of crazy to be in this group.

Please note, after a the "crazy" stuff, he is calling others here crazy, even someone more sensible than himself. Out styled and classed again.

How idiotic!

Ever here of the game whack a troll? Trolls poke their heads up out of holes pretending to be demented Yoda puppets, you bop them on the head, and if they come up again, you keep bopping them, until they leave you alone or waste their poor lives trying
to express their superior arrogance on others, not realising they are nuttily playing themselves, while the rest of us just look at what they are, bemusingly. The truth hurts.

I'll ask again, is this really the guy from here?:

https://www.arius.com/

--

Rick C.

Arius

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

In article <4786725b-4598-49d3-9a52-7424102197d2n@googlegroups.com>,
Wayne morellini <waynemorellini@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and years, dragging themselves into such "non-productive conversations" wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette. (Undoubtedly you are asked before.)

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and years, dragging themselves into such "non-productive conversations" wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette. (Undoubtedly you are asked before.)

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

Never heard of this made up verse of etiquette. But it was less than 72 lines, and virtually every reply to an individual assertion is less than 72 lines.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and years, dragging themselves into such "non-productive conversations" wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette. (Undoubtedly you are asked before.)

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

Ok, sent a feedback request. I suggest you do the same. Strength in numbers.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and years, dragging themselves into such "non-productive conversations" wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette. (Undoubtedly you are asked before.)

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

Ok you must mean 72 characters per line. I'm a Google user, so that's practically impossible. You can do
What I do, and contact them about putting options in to line break auto wrap Posts, but I find the Google group people are one of the ones who rarely listen, and the email people a bit.
However, one you start quoting people the indentations are going go over.
So, you can take responsibility, and get news readers that wrap lines. Also, explain yourself better. Look
At all the time I spend on examining myself, and how rude some are who don't bother to make effort to
read the explanation built for them
Read the following article on the basis of this etiquette, and how some of those
things are not really current:

https://www.theguardian.com/technology/2001/apr/26/onlinesupplement10

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tue, 12 Jul 2022 01:07:39 -0700 (PDT)
Wayne morellini <waynemorellini@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

Please can you restrict your lines to 72 as per the usenet etiquette. (Undoubtedly you are asked before.)

Groetjes Albert

Never heard of this made up verse of etiquette. But it was less than 72 lines, and virtually every reply to an individual assertion is less than 72 lines.

http://linux.sgms-centre.com/misc/netiquette.php#wrap

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, 12 July 2022 at 09:44:47 UTC+1, Wayne morellini wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and years, dragging themselves into such "non-productive conversations" wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette. (Undoubtedly you are asked before.)

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

Ok you must mean 72 characters per line. I'm a Google user, so that's practically impossible. You can do
What I do, and contact them about putting options in to line break auto wrap Posts, but I find the Google group people are one of the ones who rarely listen, and the email people a bit.
However, one you start quoting people the indentations are going go over.
So, you can take responsibility, and get news readers that wrap lines. Also, explain yourself better. Look
At all the time I spend on examining myself, and how rude some are who don't bother to make effort to
read the explanation built for them
Read the following article on the basis of this etiquette, and how some of those
things are not really current:

https://www.theguardian.com/technology/2001/apr/26/onlinesupplement10

What a silly post.

Either you post for yourself - then it does not matter.
And just do not waste everybody's time including yours.
Post nothing.

Option 2: Or you post for peop[le here.
Then you should do it in a way that the receiving end likes it.
Then you should be clever enough to count to 72.
I just add in CRs where you find it suitable. I do it that way.

Option 3: Just make the reading window narrower and the internet does it for you.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

In article <69d17083-30c2-4d70-a558-79642e9d0e8dn@googlegroups.com>,
Wayne morellini <waynemorellini@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and

years, dragging themselves into such "non-productive conversations"
wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette.
(Undoubtedly you are asked before.)

Groetjes Albert

Ok you must mean 72 characters per line. I'm a Google user, so that's >practically impossible. You can do
What I do, and contact them about putting options in to line break auto wrap >Posts, but I find the Google group people are one of the ones who rarely >listen, and the email people a bit.

Conclusion, don't use Google.

https://www.theguardian.com/technology/2001/apr/26/onlinesupplement10

This note confirms the use of 8o character lines, preferably 72.

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, 12 July 2022 at 12:16:02 UTC+1, none albert wrote:

In article <69d17083-30c2-4d70...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and

years, dragging themselves into such "non-productive conversations"
wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette.
(Undoubtedly you are asked before.)

Groetjes Albert

Ok you must mean 72 characters per line. I'm a Google user, so that's >practically impossible. You can do
What I do, and contact them about putting options in to line break auto wrap >Posts, but I find the Google group people are one of the ones who rarely >listen, and the email people a bit.

Conclusion, don't use Google.

https://www.theguardian.com/technology/2001/apr/26/onlinesupplement10

This note confirms the use of 8o character lines, preferably 72.
Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 12

Why change the setup I use.
This is how long about 72 characters are.
So just use a few CRs - problem solved.
And other posts within the range are a simple reference.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 9:16:02 PM UTC+10, none albert wrote:

In article <69d17083-30c2-4d70...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and

years, dragging themselves into such "non-productive conversations"
wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette.
(Undoubtedly you are asked before.)

Groetjes Albert

Ok you must mean 72 characters per line. I'm a Google user, so that's >practically impossible. You can do
What I do, and contact them about putting options in to line break auto wrap >Posts, but I find the Google group people are one of the ones who rarely >listen, and the email people a bit.

Conclusion, don't use Google.

https://www.theguardian.com/technology/2001/apr/26/onlinesupplement10

This note confirms the use of 8o character lines, preferably 72.
Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

Conclusion, fit in with Google. My accounts tied to it. You can petition them for change, I just asked for a auto line clip feature. Or maybe you can petition the developers of what software you have to put in an auto wrap. It's there job.


@Jan, it was already answered in the previous post. Albert had meant 72 characters per line, there is no 72 line rule.

@Jpit, yes, Indeed silly, I would had presumed it was my softwares fault if it didn't wrap, and not consumed about it.
You only let things go off screen for no reason if you can't do your job, don't want to, or just want to annoy people.
Sorry, I have no control over mine of their software, but mine does their job and wraps the paragraphs.

Rather than post for the never ending fashionable unjust whims of certain people, just past for the information
and objectives of the thread for them. They are going to waste your time somehow, rather than get descent software
which auto wraps.

Counting 72 characters as you type is just not credible. Most people can't write properly and edit each character,
Then you end up with a mess. Just get descent software it don't bother reading. It's more likely that one end is using
soft returns for lines breaks and hard returns fir paragraph breaks, and the other is using it some other way, and it's
really an incomplete compatability issue. Anyway, if people don't truely care about the content of messages, they should
retire. There is enough faux intellectuals around that always go on about trivial form and lack substantial substance.
One will make one trivial and trivialising, to drag the conversation back down to their level, the other, will make you substantive.
I wish I knew the Latin for this, but, Read what can be read.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, 12 July 2022 at 13:36:44 UTC+1, Wayne morellini wrote:

On Tuesday, July 12, 2022 at 9:16:02 PM UTC+10, none albert wrote:

In article <69d17083-30c2-4d70...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and

years, dragging themselves into such "non-productive conversations" >wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette.
(Undoubtedly you are asked before.)

Groetjes Albert

Ok you must mean 72 characters per line. I'm a Google user, so that's >practically impossible. You can do
What I do, and contact them about putting options in to line break auto wrap
Posts, but I find the Google group people are one of the ones who rarely >listen, and the email people a bit.

Conclusion, don't use Google.

https://www.theguardian.com/technology/2001/apr/26/onlinesupplement10

This note confirms the use of 8o character lines, preferably 72.
Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

Conclusion, fit in with Google. My accounts tied to it. You can petition them for change, I just asked for a auto line clip feature. Or maybe you can petition the developers of what software you have to put in an auto wrap. It's there job.

@Jan, it was already answered in the previous post. Albert had meant 72 characters per line, there is no 72 line rule.

@Jpit, yes, Indeed silly, I would had presumed it was my softwares fault if it didn't wrap, and not consumed about it.
You only let things go off screen for no reason if you can't do your job, don't want to, or just want to annoy people.
Sorry, I have no control over mine of their software, but mine does their job and wraps the paragraphs.

Rather than post for the never ending fashionable unjust whims of certain people, just past for the information
and objectives of the thread for them. They are going to waste your time somehow, rather than get descent software
which auto wraps.

Counting 72 characters as you type is just not credible. Most people can't write properly and edit each character,
Then you end up with a mess. Just get descent software it don't bother reading. It's more likely that one end is using
soft returns for lines breaks and hard returns fir paragraph breaks, and the other is using it some other way, and it's
really an incomplete compatability issue. Anyway, if people don't truely care about the content of messages, they should
retire. There is enough faux intellectuals around that always go on about trivial form and lack substantial substance.
One will make one trivial and trivialising, to drag the conversation back down to their level, the other, will make you substantive.
I wish I knew the Latin for this, but, Read what can be read.

AND ANOTHER SILLY POST OF YOURS.
AND AS ONE CAN SEE LINES TOO LONG AGAIN.
You just give a monkeys,
so live with the reactions.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 10:45:33 PM UTC+10, jpit...@gmail.com wrote:

On Tuesday, 12 July 2022 at 13:36:44 UTC+1, Wayne morellini wrote:

On Tuesday, July 12, 2022 at 9:16:02 PM UTC+10, none albert wrote:

In article <69d17083-30c2-4d70...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

Please note, this person has been wasting many hours, weeks and >years, dragging themselves into such "non-productive conversations" >wasting their time.

Please can you restrict your lines to 72 as per the usenet etiquette. >> (Undoubtedly you are asked before.)

Groetjes Albert

Ok you must mean 72 characters per line. I'm a Google user, so that's >practically impossible. You can do
What I do, and contact them about putting options in to line break auto wrap
Posts, but I find the Google group people are one of the ones who rarely >listen, and the email people a bit.

Conclusion, don't use Google.

https://www.theguardian.com/technology/2001/apr/26/onlinesupplement10 This note confirms the use of 8o character lines, preferably 72.

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

Conclusion, fit in with Google. My accounts tied to it. You can petition them for change, I just asked for a auto line clip feature. Or maybe you can petition the developers of what software you have to put in an auto wrap. It's there job.

@Jan, it was already answered in the previous post. Albert had meant 72 characters per line, there is no 72 line rule.

@Jpit, yes, Indeed silly, I would had presumed it was my softwares fault if it didn't wrap, and not consumed about it.
You only let things go off screen for no reason if you can't do your job, don't want to, or just want to annoy people.
Sorry, I have no control over mine of their software, but mine does their job and wraps the paragraphs.

Rather than post for the never ending fashionable unjust whims of certain people, just past for the information
and objectives of the thread for them. They are going to waste your time somehow, rather than get descent software
which auto wraps.

Counting 72 characters as you type is just not credible. Most people can't write properly and edit each character,
Then you end up with a mess. Just get descent software it don't bother reading. It's more likely that one end is using
soft returns for lines breaks and hard returns fir paragraph breaks, and the other is using it some other way, and it's
really an incomplete compatability issue. Anyway, if people don't truely care about the content of messages, they should
retire. There is enough faux intellectuals around that always go on about trivial form and lack substantial substance.
One will make one trivial and trivialising, to drag the conversation back down to their level, the other, will make you substantive.
I wish I knew the Latin for this, but, Read what can be read.

AND ANOTHER SILLY POST OF YOURS.
AND AS ONE CAN SEE LINES TOO LONG AGAIN.
You just give a monkeys,
so live with the reactions.

Silly alright. Setup your software properly. So, slightly too long, I don't have a ruler on here.
Are you Peter forth that Rick mentions. I can't tell, because you don't have a proper name
or sig with a proper name, and lost track of your name, sorry..

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, July 12, 2022 at 10:41:13 PM UTC+10, jpit...@gmail.com wrote:

On Tuesday, 12 July 2022 at 12:16:02 UTC+1, none albert wrote:

In article <69d17083-30c2-4d70...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

..

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 12

Why change the setup I use.
This is how long about 72 characters are.

That line is 79 characters long!

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, 12 July 2022 at 14:07:33 UTC+1, Wayne morellini wrote:

On Tuesday, July 12, 2022 at 10:41:13 PM UTC+10, jpit...@gmail.com wrote:

On Tuesday, 12 July 2022 at 12:16:02 UTC+1, none albert wrote:

In article <69d17083-30c2-4d70...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

..

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 12

Why change the setup I use.
This is how long about 72 characters are.

That line is 79 characters long!

Well, I tried to make it easy for you to get to 72
- and it worked as I can see, so a real 72 is slightly shorter
you might be able to fathom.

Just do a copy and paste as top of your post and stay shorter - then it is as well clearly coming from you.
1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 1234567

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, July 13, 2022 at 12:56:04 AM UTC+10, jpit...@gmail.com wrote:

On Tuesday, 12 July 2022 at 14:07:33 UTC+1, Wayne morellini wrote:

On Tuesday, July 12, 2022 at 10:41:13 PM UTC+10, jpit...@gmail.com wrote:

On Tuesday, 12 July 2022 at 12:16:02 UTC+1, none albert wrote:

In article <69d17083-30c2-4d70...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

On Tuesday, July 12, 2022 at 6:01:55 PM UTC+10, none albert wrote:

In article <4786725b-4598-49d3...@googlegroups.com>,
Wayne morellini <waynemo...@gmail.com> wrote:

..

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 1234567890 12

Why change the setup I use.
This is how long about 72 characters are.

That line is 79 characters long!

Well, I tried to make it easy for you to get to 72
- and it worked as I can see, so a real 72 is slightly shorter
you might be able to fathom.

I did, you did not.

I notice I get things here you guys have missed in these recent posts. Anyway, the very sine solution,
I have been robbed of enough time deliberately. So, I don't have time left and am not interested in
counting anything. It is only a few people trying to not pick, wrongly or rightly, unnecessarily, and
me having to respond. So the solution is simple, change your software to work properly, and leave.

There will always be something minor for certain people to fund to complain about, which Is a
A significant problem in thinking, rather than the more weighty issues. Do you deserve to be here
On the minor, ignoring the greater issues, probably not. So you have a point, not much of one,
And my time has simply been too side tracked already to send time in this bandwidth wasting
Campaign. The real solution, is just to block you.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:

What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well.

Well said! And InMyOpinion, the smaller the design commitee, the better. (I'm not good at politics.)
What enables me is cheap FPGA eval kits and free Icarus Verilog design and simulation tools (and doc).

Trade secret1: You don't need to be a Grand Master Of Verilog to express the desired results.
Trade secret2: Test your original hardware modules with at least 1 test bench before you trust them.
These pertain to the entire design, whether CPU, (initialized)RAM, or IO modules.

I posit that since I have designed reliable SoCs on FPGA eval boards, anyone else can, with due diligence.
Due diligence starts with knowing what you want, and what the board, FPGA fabric and tools you are using provide.
We have vast opportunities.

Jimbo is not James Bond.
- Myron Plichota

You realise who has done 0 to doing a public forth processor outside undermining and holding people back?
That you aren't good at politics, otherwise you would recognise the proverbial Nazi's in the room, who have
hooked you on a leash. Seriously, who are the only people who haven't really contributed anything much?

Nobody much, is interested in virtually unsellable FPGA, where a proper forth design would be much better. If you
want fpga, there, are processors on some, and smaller FPGA CPU images to use than forth. If you want to
make an FPGA into a Forth processor, you have a very slow expensive power hungry forth processor. An
FPGA is often about the functionality programmed in, requiring little in an administrative soft CPU. In most
instances where this CPU would sell, and fpga one wouldn't, because of their inefficient sloppy style.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well.

Well said! And InMyOpinion, the smaller the design commitee, the better. (I'm not good at politics.)
What enables me is cheap FPGA eval kits and free Icarus Verilog design and simulation tools (and doc).

Trade secret1: You don't need to be a Grand Master Of Verilog to express the desired results.
Trade secret2: Test your original hardware modules with at least 1 test bench before you trust them.
These pertain to the entire design, whether CPU, (initialized)RAM, or IO modules.

I posit that since I have designed reliable SoCs on FPGA eval boards, anyone else can, with due diligence.
Due diligence starts with knowing what you want, and what the board, FPGA fabric and tools you are using provide.
We have vast opportunities.

Jimbo is not James Bond.
- Myron Plichota

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:

On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:

What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well.

Well said! And InMyOpinion, the smaller the design commitee, the better. (I'm not good at politics.)
What enables me is cheap FPGA eval kits and free Icarus Verilog design and simulation tools (and doc).

Trade secret1: You don't need to be a Grand Master Of Verilog to express the desired results.
Trade secret2: Test your original hardware modules with at least 1 test bench before you trust them.
These pertain to the entire design, whether CPU, (initialized)RAM, or IO modules.

I posit that since I have designed reliable SoCs on FPGA eval boards, anyone else can, with due diligence.
Due diligence starts with knowing what you want, and what the board, FPGA fabric and tools you are using provide.
We have vast opportunities.

Jimbo is not James Bond.
- Myron Plichota

You realise who has done 0 to doing a public forth processor outside undermining and holding people back?
That you aren't good at politics, otherwise you would recognise the proverbial Nazi's in the room, who have
hooked you on a leash. Seriously, who are the only people who haven't really contributed anything much?

Nobody much, is interested in virtually unsellable FPGA, where a proper forth design would be much better. If you
want fpga, there, are processors on some, and smaller FPGA CPU images to use than forth. If you want to
make an FPGA into a Forth processor, you have a very slow expensive power hungry forth processor. An
FPGA is often about the functionality programmed in, requiring little in an administrative soft CPU. In most
instances where this CPU would sell, and fpga one wouldn't, because of their inefficient sloppy style.

More fool me, I thought I was being 100% positive about grassroots effort in Forth CPU design.
If you (or anyone else) wish to peruse one of my entirely public (and copyright free) designs, unzip
https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=sharing

Jimbo is not James Bond.
- Myron Plichota

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, July 13, 2022 at 6:17:26 PM UTC+2, Myron Plichota wrote:

What enables me is cheap FPGA eval kits and free Icarus Verilog design
and simulation tools (and doc).

Trade secret1: You don't need to be a Grand Master Of Verilog to express
the desired results.
Trade secret2: Test your original hardware modules with at least 1 test
bench before you trust them.
These pertain to the entire design, whether CPU, (initialized)RAM,
or IO modules.

In your opinion: would it be worth the (i.e. my) effort to translate algorithms into an FPGA implementation? I need FP (double precision) and it would need
to be faster than a current PC (e.g. very-wide instructions, and/or > 64 mini-cores,
cheaper than PC with equivalent throughput)?
I have wanted to do this since 1985, and the necessity has not diminished
since then.

-marcel

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, July 13, 2022 at 1:27:35 PM UTC-4, Marcel Hendrix wrote:

On Wednesday, July 13, 2022 at 6:17:26 PM UTC+2, Myron Plichota wrote:

What enables me is cheap FPGA eval kits and free Icarus Verilog design
and simulation tools (and doc).

Trade secret1: You don't need to be a Grand Master Of Verilog to express the desired results.
Trade secret2: Test your original hardware modules with at least 1 test bench before you trust them.
These pertain to the entire design, whether CPU, (initialized)RAM,
or IO modules.

In your opinion: would it be worth the (i.e. my) effort to translate algorithms
into an FPGA implementation? I need FP (double precision) and it would need to be faster than a current PC (e.g. very-wide instructions, and/or > 64 mini-cores,
cheaper than PC with equivalent throughput)?
I have wanted to do this since 1985, and the necessity has not diminished since then.

-marcel

It's always worth investigating the benefits of a hardware investment.

I'd be delighted to share Verilog for (unsigned) integer algorithms such as a divide/remainder step or Will Baden's square root/remainder step.
Email me directly at myronplichota@gmail.com to request the goods.

I'm inclined to use a 2's-complement integer core that punts floating-point operations to a "move machine" memory-mapped IO interface.
I have nothing up my sleeve re said FPU ops, but I'd love to contibute to any public-domain Verilog effort that strives to realize such goals.

I doubt that any FPGA results would surpass Big Silicon FPU performance :)

- Myron Plichota

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, July 13, 2022 at 9:45:38 PM UTC+2, Myron Plichota wrote:
[..]

I doubt that any FPGA results would surpass Big Silicon FPU performance :)

A hardcoded circuit simulation task does not need to fetch code from
program memory (after some finite number of cycles). Organized as a
pipeline it produces (at best) 1 timepoint per clock (say 200
double-precision words/cycle). It should be possible to store that in a parallel fashion to 200 standard memory banks. If I understand Emma
and Ian correctly (https://www.youtube.com/watch?v=iUjfRBfSN-o&t=4s),
that should do it.

-marcel

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Marcel Hendrix <mhx@iae.nl> writes:

In your opinion: would it be worth the (i.e. my) effort to translate algorithms into an FPGA implementation? I need FP (double precision)
and it would need to be faster than a current PC

There are definitely applications where using an FPGA is a big win,
because of the high amount of parallelism available. But, you likely
have to design the algorithm specifically for FPGA implementation.

It may be simpler to use a GPU, if your algorithm can be arranged to
make good use of one.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 14, 2022 at 2:54:15 AM UTC+2, Paul Rubin wrote:

Marcel Hendrix <m...@iae.nl> writes:

In your opinion: would it be worth the (i.e. my) effort to translate algorithms into an FPGA implementation? I need FP (double precision)
and it would need to be faster than a current PC

There are definitely applications where using an FPGA is a big win,
because of the high amount of parallelism available. But, you likely
have to design the algorithm specifically for FPGA implementation.

It may be simpler to use a GPU, if your algorithm can be arranged to
make good use of one.

I would need a sponsor (NVIDIA H100 GPU == $36,550).

-marcel

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On 14/07/2022 15:52, Marcel Hendrix wrote:

On Thursday, July 14, 2022 at 2:54:15 AM UTC+2, Paul Rubin wrote:

Marcel Hendrix <m...@iae.nl> writes:

In your opinion: would it be worth the (i.e. my) effort to translate
algorithms into an FPGA implementation? I need FP (double precision)
and it would need to be faster than a current PC

There are definitely applications where using an FPGA is a big win,
because of the high amount of parallelism available. But, you likely
have to design the algorithm specifically for FPGA implementation.

It may be simpler to use a GPU, if your algorithm can be arranged to
make good use of one.

I would need a sponsor (NVIDIA H100 GPU == $36,550).

iForth Pty Ltd

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 14, 2022 at 8:29:16 AM UTC+2, Paul Rubin wrote:

Marcel Hendrix <m...@iae.nl> writes:

I would need a sponsor (NVIDIA H100 GPU == $36,550).

Can you use a smaller gpu? Or several? Look on tensordock.com for
rentals starting at 0.32 USD/hour.

Interesting idea! Maybe I can go one step further before throwing cash around.

-marcel

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 14, 2022 at 8:06:48 AM UTC+2, dxforth wrote:

On 14/07/2022 15:52, Marcel Hendrix wrote:

On Thursday, July 14, 2022 at 2:54:15 AM UTC+2, Paul Rubin wrote:

Marcel Hendrix <m...@iae.nl> writes:

In your opinion: would it be worth the (i.e. my) effort to translate
algorithms into an FPGA implementation? I need FP (double precision)
and it would need to be faster than a current PC

There are definitely applications where using an FPGA is a big win,
because of the high amount of parallelism available. But, you likely
have to design the algorithm specifically for FPGA implementation.

It may be simpler to use a GPU, if your algorithm can be arranged to
make good use of one.

I would need a sponsor (NVIDIA H100 GPU == $36,550).

iForth Pty Ltd

They might sponsor a few tons of flour.

-marcel

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

Marcel Hendrix <mhx@iae.nl> writes:

I would need a sponsor (NVIDIA H100 GPU == $36,550).

Can you use a smaller gpu? Or several? Look on tensordock.com for
rentals starting at 0.32 USD/hour.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:

On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:

On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:

What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well.

Well said! And InMyOpinion, the smaller the design commitee, the better. (I'm not good at politics.)
What enables me is cheap FPGA eval kits and free Icarus Verilog design and simulation tools (and doc).

Trade secret1: You don't need to be a Grand Master Of Verilog to express the desired results.
Trade secret2: Test your original hardware modules with at least 1 test bench before you trust them.
These pertain to the entire design, whether CPU, (initialized)RAM, or IO modules.

I posit that since I have designed reliable SoCs on FPGA eval boards, anyone else can, with due diligence.
Due diligence starts with knowing what you want, and what the board, FPGA fabric and tools you are using provide.
We have vast opportunities.

Jimbo is not James Bond.
- Myron Plichota

You realise who has done 0 to doing a public forth processor outside undermining and holding people back?
That you aren't good at politics, otherwise you would recognise the proverbial Nazi's in the room, who have
hooked you on a leash. Seriously, who are the only people who haven't really contributed anything much?

Nobody much, is interested in virtually unsellable FPGA, where a proper forth design would be much better. If you
want fpga, there, are processors on some, and smaller FPGA CPU images to use than forth. If you want to
make an FPGA into a Forth processor, you have a very slow expensive power hungry forth processor. An
FPGA is often about the functionality programmed in, requiring little in an administrative soft CPU. In most
instances where this CPU would sell, and fpga one wouldn't, because of their inefficient sloppy style.

More fool me, I thought I was being 100% positive about grassroots effort in Forth CPU design.
If you (or anyone else) wish to peruse one of my entirely public (and copyright free) designs, unzip
https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=sharing
Jimbo is not James Bond.
- Myron Plichota

I love you man! I agree with
your effort, but my point
was that you shouldn't be
positive about people so
positive, that they hold
positive people back. We
see this in most threads on
the subject, it is just killing
things for decades.
Imagine 100's of billions of
dollars just vanishing into
the distance. That's the
difference negative people have made to forth
hardware Now, it's nearly
pointless. GA should make
a different language and
call it Glow! (Glow for
schools, include some icon
and object based
programming modelling).
Just to try to stay away
from this sort of
negativity. People with low
real forwards talent, that
just want to jump in on
things.

Now, for FPGA. Until a
programmable circuit costs
closer to the same as custom
silicon, in high volume and
performs just as well, it is
two different markets. FPGA
lower entry point for lower
volumes often, and custom
for lower price at higher
volumes with higher
performance. FPGA, is there,
I'm more interested in the
custom silicon. If I can get
close enough with a
programmable circuit device
on metrics, that would be ok,
then. If the difference in
energy, speed, price, were 10
times or less (such as, for
example, each were 3.33
times different, combined,
that would be great. Which is
why I'm thinking a more
conventional single
programmable hard gate
array device, similar to
performance difference as
they did with Novix) might
get on that range. You can
literally manufacture
hundreds of millions of
blanks, and everybody buy a
pack according to the size
they need, and keep using the
same pack for projects for
years. When I did my
research into doing in house
fabrication years ago, I
determined such a scheme
es the way to go.

It's a shame Chuck didn't just
go to Mos technologies years
ago. Sure Jack would
probably try to give him a
pretty resistible deal, but they
could have afforded to
upgrade the plant to smaller
node processes, and
manufacture cheap and sold
a stack of chips, at 10mhz
maybe, on the old lines, and
keep up to 3x clock
advantage on a new process.
The whole bottom end of the
industry could still be
dominated by a superior
efficiency it.

When we look at what can be
done cheaper, it's pretty
poor. In matter of fact, those
4 bit Chinese processor
factories could be used to
make an ultra low spec misc,
as part of the product line.
They could literally make
smart watch MCU lines,
cheaper than wear os
devices. People lack
inventive practical
imaginations. Such a design.
Would be suitable for
wireless autonomous
interactive smart tags.
Starting at around a cent or
something. Program and
install, and you are off. An
advanced tag is an Access or
Info Panel, even a $1000
dollar one, controlled by the
same sort of technology.
Military for $10,000 all
endurance panel.

The truth of the matter. You ask some people, and
you won't make a single
dollar, even loose millions.
They will say it won't
succeed, that won't succeed.
All in their superiority, which
has no evidence. We all seen
tech companies fall over left
right and centre due to
incompetence over the
decades. You sit back and
say why are they doing this or
that for years, and they fall
over, not being able to see
how wrong those decisions
were, and not selecting the
right decisions which made
other companies succeed.
I've done enough with
companies to know, even
when you hand them things
on a platter, they still manage
to stuff things up. You can't
even help them for their own
good.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, 14 July 2022 at 08:23:54 UTC+1, Wayne morellini wrote:

On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:

On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:

On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:

What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well.

Well said! And InMyOpinion, the smaller the design commitee, the better. (I'm not good at politics.)
What enables me is cheap FPGA eval kits and free Icarus Verilog design and simulation tools (and doc).

Trade secret1: You don't need to be a Grand Master Of Verilog to express the desired results.
Trade secret2: Test your original hardware modules with at least 1 test bench before you trust them.
These pertain to the entire design, whether CPU, (initialized)RAM, or IO modules.

I posit that since I have designed reliable SoCs on FPGA eval boards, anyone else can, with due diligence.
Due diligence starts with knowing what you want, and what the board, FPGA fabric and tools you are using provide.
We have vast opportunities.

Jimbo is not James Bond.
- Myron Plichota

You realise who has done 0 to doing a public forth processor outside undermining and holding people back?
That you aren't good at politics, otherwise you would recognise the proverbial Nazi's in the room, who have
hooked you on a leash. Seriously, who are the only people who haven't really contributed anything much?

Nobody much, is interested in virtually unsellable FPGA, where a proper forth design would be much better. If you
want fpga, there, are processors on some, and smaller FPGA CPU images to use than forth. If you want to
make an FPGA into a Forth processor, you have a very slow expensive power hungry forth processor. An
FPGA is often about the functionality programmed in, requiring little in an administrative soft CPU. In most
instances where this CPU would sell, and fpga one wouldn't, because of their inefficient sloppy style.

More fool me, I thought I was being 100% positive about grassroots effort in Forth CPU design.
If you (or anyone else) wish to peruse one of my entirely public (and copyright free) designs, unzip
https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=sharing
Jimbo is not James Bond.
- Myron Plichota

I love you man! I agree with
your effort, but my point
was that you shouldn't be
positive about people so
positive, that they hold
positive people back. We
see this in most threads on
the subject, it is just killing
things for decades.
Imagine 100's of billions of
dollars just vanishing into
the distance. That's the
difference negative people have made to forth
hardware Now, it's nearly
pointless. GA should make
a different language and
call it Glow! (Glow for
schools, include some icon
and object based
programming modelling).
Just to try to stay away
from this sort of
negativity. People with low
real forwards talent, that
just want to jump in on
things.

Now, for FPGA. Until a
programmable circuit costs
closer to the same as custom
silicon, in high volume and
performs just as well, it is
two different markets. FPGA
lower entry point for lower
volumes often, and custom
for lower price at higher
volumes with higher
performance. FPGA, is there,
I'm more interested in the
custom silicon. If I can get
close enough with a
programmable circuit device
on metrics, that would be ok,
then. If the difference in
energy, speed, price, were 10
times or less (such as, for
example, each were 3.33
times different, combined,
that would be great. Which is
why I'm thinking a more
conventional single
programmable hard gate
array device, similar to
performance difference as
they did with Novix) might
get on that range. You can
literally manufacture
hundreds of millions of
blanks, and everybody buy a
pack according to the size
they need, and keep using the
same pack for projects for
years. When I did my
research into doing in house
fabrication years ago, I
determined such a scheme
es the way to go.

It's a shame Chuck didn't just
go to Mos technologies years
ago. Sure Jack would
probably try to give him a
pretty resistible deal, but they
could have afforded to
upgrade the plant to smaller
node processes, and
manufacture cheap and sold
a stack of chips, at 10mhz
maybe, on the old lines, and
keep up to 3x clock
advantage on a new process.
The whole bottom end of the
industry could still be
dominated by a superior
efficiency it.

When we look at what can be
done cheaper, it's pretty
poor. In matter of fact, those
4 bit Chinese processor
factories could be used to
make an ultra low spec misc,
as part of the product line.
They could literally make
smart watch MCU lines,
cheaper than wear os
devices. People lack
inventive practical
imaginations. Such a design.
Would be suitable for
wireless autonomous
interactive smart tags.
Starting at around a cent or
something. Program and
install, and you are off. An
advanced tag is an Access or
Info Panel, even a $1000
dollar one, controlled by the
same sort of technology.
Military for $10,000 all
endurance panel.

The truth of the matter. You ask some people, and
you won't make a single
dollar, even loose millions.
They will say it won't
succeed, that won't succeed.
All in their superiority, which
has no evidence. We all seen
tech companies fall over left
right and centre due to
incompetence over the
decades. You sit back and
say why are they doing this or
that for years, and they fall
over, not being able to see
how wrong those decisions
were, and not selecting the
right decisions which made
other companies succeed.
I've done enough with
companies to know, even
when you hand them things
on a platter, they still manage
to stuff things up. You can't
even help them for their own
good.

Can you please reset you mental countar from 25 to 75 characters per line. Lines will then be 3x longer than you did,
and normal people can more easily read them.
Thank you.
Or are you doing this on purpose to annoy us?

--- SoupGate-Win32 v1.05
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Marcel Hendrix <mhx@iae.nl> writes:

It may be simpler to use a GPU, if your algorithm can be arranged to
make good use of one.

I would need a sponsor (NVIDIA H100 GPU == $36,550).

You made me curious... it's an April Fool's joke?

https://wccftech.com/nvidia-h100-hopper-gpu-monster-graphics-card-with-100-billion-transistors-across-2-dies-43008-cuda-cores-and-48-gb-hbm4-memory/

Andy Valencia
Home page: https://www.vsta.org/andy/
To contact me: https://www.vsta.org/contact/andy.html

--- SoupGate-Win32 v1.05
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On Thursday, July 14, 2022 at 6:04:58 PM UTC+10, jpit...@gmail.com wrote:

On Thursday, 14 July 2022 at 08:23:54 UTC+1, Wayne morellini wrote:

On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:

On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:

On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:

Can you please reset you mental countar from 25 to 75 characters per line. Lines will then be 3x longer than you did,
and normal people can more easily read them.
Thank you.
Or are you doing this on purpose to annoy us?

No, it fits the screen. Is easy to cut.
Makes it easier to read.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Thursday, July 14, 2022 at 3:15:33 PM UTC+2, Andy Valencia wrote:

Marcel Hendrix <m...@iae.nl> writes:

It may be simpler to use a GPU, if your algorithm can be arranged to
make good use of one.

I would need a sponsor (NVIDIA H100 GPU == $36,550).

You made me curious... it's an April Fool's joke?

https://wccftech.com/nvidia-h100-hopper-gpu-monster-graphics-card-with-100-billion-transistors-across-2-dies-43008-cuda-cores-and-48-gb-hbm4-memory/

I don't think so. Google returns a couple of references, and at least one
of them is from Nvidia's website.

-marcel

--- SoupGate-Win32 v1.05
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On Thursday, 14 July 2022 at 17:04:10 UTC+1, Wayne morellini wrote:

On Thursday, July 14, 2022 at 6:04:58 PM UTC+10, jpit...@gmail.com wrote:

On Thursday, 14 July 2022 at 08:23:54 UTC+1, Wayne morellini wrote:

On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:

On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:

On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:

Can you please reset you mental countar from 25 to 75 characters per line. Lines will then be 3x longer than you did,
and normal people can more easily read them.
Thank you.
Or are you doing this on purpose to annoy us?

No, it fits the screen. Is easy to cut.
Makes it easier to read.

So you are saying
that you already have a very narrow screen
for an even narrower Forth chip?
Can we still take you serious?

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Friday, July 15, 2022 at 2:11:03 AM UTC+10, jpit...@gmail.com wrote:

On Thursday, 14 July 2022 at 17:04:10 UTC+1, Wayne morellini wrote:

On Thursday, July 14, 2022 at 6:04:58 PM UTC+10, jpit...@gmail.com wrote:

On Thursday, 14 July 2022 at 08:23:54 UTC+1, Wayne morellini wrote:

On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:

On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:

On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:

Can you please reset you mental countar from 25 to 75 characters per line.
Lines will then be 3x longer than you did,
and normal people can more easily read them.
Thank you.
Or are you doing this on purpose to annoy us?

No, it fits the screen. Is easy to cut.
Makes it easier to read.

So you are saying
that you already have a very narrow screen
for an even narrower Forth chip?
Can we still take you serious?

Narrower forth chip ? I didn't mention that in
my reply (actually that was one actual plan that
has some advantages).

But seriously, I knew you would be back to
complain about something. Accept it. I've
got trouble typing at the moment and will have
to leave it.

--- SoupGate-Win32 v1.05
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On Thursday, July 7, 2022 at 11:58:39 PM UTC+10, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor

plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

Thanks again.

Wayne.

Syncing forth processor project threads.

--- SoupGate-Win32 v1.05
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On Sunday, September 4, 2022 at 3:06:16 PM UTC+10, Wayne morellini wrote:

On Thursday, July 7, 2022 at 11:58:39 PM UTC+10, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000

transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

Thanks again.

Wayne.

Syncing forth processor project threads.

Forth processor project

Is it time for another Forth chip?

https://groups.google.com/u/2/g/comp.lang.forth/c/6adve-Z1ppU

Designing a Forth Processor?

https://groups.google.com/u/2/g/comp.lang.forth/c/9lpG9yey_NQ

A low cost chip prototyping technique.

https://groups.google.com/u/2/g/comp.lang.forth/c/s27tSebmF-I

Comments: ColorForth binary in JavaScript!

https://groups.google.com/u/2/g/comp.lang.forth/c/3py7TwKu6b0

Looking for some advice on Offete p8, p16, p24, p32, p64. Ep16, ep24, ep32, and others.

https://groups.google.com/u/2/g/comp.lang.forth/c/EMgCYdV8NR8

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Monday, September 5, 2022 at 1:23:41 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:06:16 PM UTC+10, Wayne morellini wrote:

On Thursday, July 7, 2022 at 11:58:39 PM UTC+10, Wayne morellini wrote:

So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000

transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially

with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

Thanks again.

Wayne.

Syncing forth processor project threads.

Forth processor project

Is it time for another Forth chip?

https://groups.google.com/u/2/g/comp.lang.forth/c/6adve-Z1ppU

Designing a Forth Processor?

https://groups.google.com/u/2/g/comp.lang.forth/c/9lpG9yey_NQ

A low cost chip prototyping technique.

https://groups.google.com/u/2/g/comp.lang.forth/c/s27tSebmF-I

Comments: ColorForth binary in JavaScript!

https://groups.google.com/u/2/g/comp.lang.forth/c/3py7TwKu6b0

Looking for some advice on Offete p8, p16, p24, p32, p64. Ep16, ep24, ep32, and others.

https://groups.google.com/u/2/g/comp.lang.forth/c/EMgCYdV8NR8

First list:

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

--- SoupGate-Win32 v1.05
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