On Saturday, June 18, 2022 at 1:07:07 PM UTC+10, Paul Rubin wrote:

I'm sorry but I just can't read those long walls of text. Could you
give a description of the chip you're proposing, the kind of description
one would see on a data sheet? Not a 500 page manual or anything like
that. Just a few lines with the basics. Examples:

Not discussing building my own chip. This is about you guys discussing for the last time.

I mentioned, I am personally looking at other things.

But. I am considering doing the Google thing, to give you guys a pep up.


- A simple 1000 transistor+ core.

- a macro core to be used to roll your own chip

-16 bit colorforth or machine forth comparable.

Optionals:

-reconfigurable pins so maybe used as 16 bit data/address/clocked IO DMA/digital/analogue pins

-nesting of clocks

-comfiguration of pins to different levels.

-No DMA side code insertion and control mechanism. System activated and chooses to service.

-At some time, an isolation circuit on each pin, to protect the circuits.

-maybe a group of pins you can configure for one or two displays. Maybe just USB/TB/MHL video and sound.

-io pin protocol rules list

-All pins can be set to trigger action

-64KB to 1MB of SRAM on chip, and 1-3 trasistor parasitic capacitance ram if available, and it's better to use instead. The parasitic is almost like nonvolatile.

-variable power control on memory capacity, to match variable sized banks. 16 words, 32 words, 64 words 128 words, etc up to X size. 16 - X words is the fastest memory place internally. Externally to core up to X2. I'm making all this up here. Plus I'
m using the some obviouse stuff here from the past, rather than the really good stuff I have to really sit down and nut out again with this brain damage.

You guys are getting the low hanging fruit, but that's why it's 1000 transistors plus, if I can figure out how to do the bits and pieces. This is basically a bread board hyper small complexity chip design with some additions to soup up performance.

-rom support. Dead cold starts and power while in use then auto down power. If I can get full speed with out biasing the circuit, it will probably just cold start per access.

-want to use om chip laser if supported.

-low cost package if available that simply touches traces I'm the main board.

-vectored lookup table processing, as alternative to FPGA.

-special multiplication circuit. This might break the core budget.

-various unused circuits remain lowered down. Such as multiplication.

-use powers up circuit.

Did I forget anything. Oh yes. Stack handling. Each pin can bring up the processor, so each pin had its own stacks, maybe its own processor that can associative act with surrounding pins for variable length port of pins, enable as many of the pins as
needed to boot up a processor. But, in this version, there is likely one processor, and the stacks for the pins will be in memorym. The interrupt here, is the pin has gone active, and some basic timing rules to stop clashing and hogging. However, the
pins would round robin multi task with main memory. The processor state being defined by the seperate stacks and pointers for each customer (pin and processor). The pins may then be directly attached to memory via DMA to allow for high speed dumping
into memory and hand off and power down, to the main processor to pickup. But pin processing will be slower and more energy intensive in the cheap system. The single app base model is a competitive model so the programmer designs it bit to clash with
itself.

- stacks 16 deep, finally.

This is a single control app base system, so security is not needed.

See how fast and low power this can go on
Lots of time to use the simple tools (OkCAD2 probably easier).

Actually, you could just apply to google for funding and use their facilities to make server chips for Google server wharehouses, if you were a small silicon chip designer with some promising technology.

So, you can have one or however many pins you can fit on this. Hundreds of thousands of pins coming off of a 16 bit chip.

Designed to be a thumb like extension to the x86 architecture.

Maybe will have 4 bit words, maybe 5 bit words. I don't want to use my own instruction set techniques, took me many years to come up with those.

Does everything, simply compactly and with low energy. See how fast it can go on a modern process. Doesn't matter, as using internal memory and rom.

Essentially a sub set of that.

- 32 bit version more of the same.

Advanced 16 and 32 bit versions with more desktop features. You are welcome to try that yourself, or pay for it.

Networked array, I've got my own design. But, one or more control/interface/memory io processes, then process units. Simple synchronisation bus, simple column row message bus. 16k+ interchip exchange memory is possible. It allows for efficient
communications coordination for multiple forms of parralel processing. Just ideas I've had.

The essence of this is IO variability, storage and execution, an essentially embedded processor.

However, having said that a version of the design could use pins to have a wide bus to ram, and an array of processesors on a dual bus onntje other side. Or, the processes in the middle. The data is then parralel memory processed rapidly. On the other
side could be an output bus. So, it's a flat single dimension array with no networking, to process masses of parralel data or separate streams. Very simple.

Anyway, I'm interested in flip package (or drill through) with contacts/bumps forming the bottom of the package, whatever is to pick from out there. So packaging can be very cheap. So, unused pins aren't very expensive. Can be designed to have
different memory sizes and pins. Should 1MB version fit in 1mm2 now?

There are some external optical and packaging enhancements too, but not for this. I'm very interested in making a new wireless optical version.

GREENARRAYS GA144
- 144 nodes of F18A MISC processors, about 750 mhz each
- 4 interconnect paths from each node, connecting to the adjacent
nodes in rectangular layout
- 18 bit word size, 64 words RAM and 64 words ROM per node, plus
8 level control stack and 10 level data stack at each node

ATMEGA ATTINY1616
- 8 bit word size, 32 registers, RISC-like architecture, 16 mhz
- 2KB ram, 16KB program flash
- GPIO, ADC, programmable timers yada yada

Just basic outline. Otherwise the picture is way too vague.

Next question: who would want to use it? That is, why wouldn't they use
chip XYZ instead, where XYZ is some popular existing chip?

All the wrong statements and questions. It's marketing and need. Coolness sells to one, efficient practicality to another. I am looking at both. The cheapest version could go in a coffee maker, especially if I put a proximity sensing circuit on it.
You run the display and machine with it, and it senses you finger near the display, so no buttons needed, and better contol for user. Now. If I can mount a scanning laser display circuit in it, you could do the display too, on the surface of the machine
too. Anyway, it's that easy, words mean so much, design means a lot. You can do things better, just the hassle of implementation.

Now, if I came along along and quoted specs for a floor sized super computer in a 1mm chip that runs off a watch battery for a year, you would have your Words, but they wouldn't mean much, it's how you are going do it, design it, which is the reality.
The simpler the description, often the more innacurate it can be. You quoted texts that don't tell me much of how a chip is going work. Give me design documents and I might be able to figure out how it's programmed and used. Give me the code documents
and I know. With those documents, one could work out the basic design flow and most of the data sheet, but probably not the other way about with simple specs.

Plus we wouldn't know how fast this could be made to running the Google process, until we model design and try it. It could be 5ghz, it might be 20Ghz (100 pins at 200Mhz each round robin, single processor, with DMA feed for higher pin feed). Going on
Green Arrays speed results at 180nm, at low energy maybe it could get 1Ghz, 2 or 5? Maybe anything above 2Ghz is wishful. You don't di the best design you can afford to do for customers, and see if it's prefered to your competitors.

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-16 bit colorforth or machine forth comparable. ...

Ah, thank you very much, this post actually seems to contain some useful
info. I will look at it more closely. In this context MISC may be more
useful as a coprocessor for a conventional core, than one for general computation.

Have you looked at the RP2040? It has a PIO (programmable I/O)
peripheral which is a simple state machine (runs programs up to 32 words
long) that lets you implement protocols like SPI on the I/O pins without getting the main CPU involved. MISC could be nice for that since the
PIO is quite limited.

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On Sunday, June 19, 2022 at 8:02:49 AM UTC+10, Paul Rubin wrote:

-16 bit colorforth or machine forth comparable. ...

Ah, thank you very much, this post actually seems to contain some useful info.

You lack the idea. It wasn't about me saying what it should be, but now I do, because nobody is doing anything but wasting their the being negative. I thought people would be happy to finally organise a regular/sane chip option to use regularly.


I've talked about stuff before. It's up to you to read, don't blame me. It's fairly straight forwards and not as complex as chip design normally would be

I will look at it more closely. In this context MISC may be more
useful as a coprocessor for a conventional core, than one for general computation.

Well, a array of this sort of misc would be a good coprocessor, but this chip is good on its own.

Have you looked at the RP2040? It has a PIO (programmable I/O)
peripheral which is a simple state machine (runs programs up to 32 words long) that lets you implement protocols like SPI on the I/O pins without getting the main CPU involved. MISC could be nice for that since the
PIO is quite limited.

No, pretty much what I'm stating here, is simpler format shaping, but my own processor designs has state like features. But thanks for being this to my attention Paul. I often developed things in black box isolation, so am unaware of what's happening on
the outside

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On Sunday, June 19, 2022 at 5:38:24 AM UTC-4, Wayne morellini wrote:

On Sunday, June 19, 2022 at 8:02:49 AM UTC+10, Paul Rubin wrote:

-16 bit colorforth or machine forth comparable. ...

Ah, thank you very much, this post actually seems to contain some useful info.

You lack the idea. It wasn't about me saying what it should be, but now I do, because nobody is doing anything but wasting their the being negative. I thought people would be happy to finally organise a regular/sane chip option to use regularly.

We actually aren't being negative. We are pointing out that you aren't saying anything useful. I still have no idea what you are suggesting other than that we should all be behind some idea of designing stack processors. Ok, I'm behind that. Let's go!

I've talked about stuff before. It's up to you to read, don't blame me. It's fairly straight forwards and not as complex as chip design normally would be

But most of what you say is not remotely useful in the context of designing a chip or even processor IP.

I will look at it more closely. In this context MISC may be more
useful as a coprocessor for a conventional core, than one for general computation.

Well, a array of this sort of misc would be a good coprocessor, but this chip is good on its own.

Have you looked at the RP2040? It has a PIO (programmable I/O)
peripheral which is a simple state machine (runs programs up to 32 words long) that lets you implement protocols like SPI on the I/O pins without getting the main CPU involved. MISC could be nice for that since the
PIO is quite limited.

No, pretty much what I'm stating here, is simpler format shaping, but my own processor designs has state like features. But thanks for being this to my attention Paul. I often developed things in black box isolation, so am unaware of what's happening

on the outside

Yup. We heard that!

--

Rick C.

-+-+ Get 1,000 miles of free Supercharging
-+-+ Tesla referral code - https://ts.la/richard11209

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Wayne morellini <waynemorellini@gmail.com> writes:

But. I am considering doing the Google thing, to give you guys a pep up.
- A simple 1000 transistor+ core.
- a macro core to be used to roll your own chip
-16 bit colorforth or machine forth comparable.
Optionals:
-reconfigurable pins so maybe used as 16 bit data/address/clocked IO DMA/digital/analogue pins ...

Ok, I read the whole post. It starts out pretty good but then goes off
the rails. Some comments:

- The reconfigurable pins with a processor on each pin sounds like a
good idea. Take a look at the Parallax P2 for how they do
reconfigurable pins, and look at the RP2040 PIO system for how they
supply some minimal coprocessors for pins. The PIO processors are
very limited though, so MISC would make them more capable.

- Regarding some of the higher end ideas, I would start out by checking
the resources available in the free fab program. 1MB of SRAM might
not be doable but if 64K is possible, that is great.

- I think MISC as a main processor on a chip these days is hard to find
uses for. As a peripheral processor it could be very nice.

An RP2040-like chip containing a RISC-V core, 64K of ram, some program
flash if possible, and reconfigurable pins with MISC processors that
could implement functions like SPI and UART would be of some actual
interest, imho.

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On Monday, June 20, 2022 at 7:02:40 AM UTC+10, Paul Rubin wrote:

Wayne morellini <waynemo...@gmail.com> writes:

But. I am considering doing the Google thing, to give you guys a pep up.
- A simple 1000 transistor+ core.
- a macro core to be used to roll your own chip
-16 bit colorforth or machine forth comparable.
Optionals:
-reconfigurable pins so maybe used as 16 bit data/address/clocked IO DMA/digital/analogue pins ...

Ok, I read the whole post. It starts out pretty good but then goes off
the rails. Some comments:

- The reconfigurable pins with a processor on each pin sounds like a
good idea. Take a look at the Parallax P2 for how they do
reconfigurable pins, and look at the RP2040 PIO system for how they
supply some minimal coprocessors for pins. The PIO processors are
very limited though, so MISC would make them more capable.

- Regarding some of the higher end ideas, I would start out by checking
the resources available in the free fab program. 1MB of SRAM might
not be doable but if 64K is possible, that is great.

- I think MISC as a main processor on a chip these days is hard to find
uses for. As a peripheral processor it could be very nice.

An RP2040-like chip containing a RISC-V core, 64K of ram, some program
flash if possible, and reconfigurable pins with MISC processors that
could implement functions like SPI and UART would be of some actual interest, imho.

That's much more useful comment than the rationality disrespectful ramblings we getting here from elsewhere. I mean I sight, I groan, particularly examining the logic of such comments, and utter some short phrases starting with what a.
-


On Rationality and giving up:

Referring to above other comments. I've had brain damage, retirement can't can't come fast enough when your mentally challenged. You got to lay down your tools, and not try to convince yourself you are mentally the way you were

(not such a problem with me. I clipped the wings, and go away, but also maintained a high level of rational functionality, up to this year or so, before the lyme treatment cleared things.

Now am externally reading challenged like you, some cognitive and functional, from damage, which I continue to retrain my mind to map around (was going to write a book on my experiences I discovered, which I latter found out were called Neural Plasticity)
etc).
-


Now, back onto your interesting message
-


Pins and IP:

I have my own adequate ideas for reconfigurable pins, and as such only want to look at other sources outside the patent period. I really appreciate the sources. If the IP period has passed, I would be happy to view that.
-


IP:

I did the above isolation with my operating system mainly.

Have government military grade related standards document I ordered decades back, somewhere. That went somewhat to my own system.

So, a lot of the time, in the OS, I was dealing with texts from the 1970's on operating systems on various mini computers and mainframe and such forth. A lot of that stuff is the same sort of thing that went into desktop operating systems.

The above maintained IP distance, and is what AMD and others do. When you go to court, if you accidentally have used something covered in present IP, the situation is much better, and damages limited. Even if you read modern IP and try to avoid it,
even if you forgot before doing something, you have still read it. Plus, you get subconsciously biased down similar paths to other Intellectual Property, and into trouble, rather than separately finding your own path. If Rick wishes to disagree, I can
point out this is how it's been done at a high level for a very long time, by big players producing more than a few boards.
-

Peripheral. Replacement and MCU device, and thought processes again:

The chip is a high speed alternative to what the GA is. So yes, you can program it as a peripheral device. But, that doesn't matter.

My own ideas for a seperate system, even emulate and processor chipset. I was doing the logical constructs for that months back.

So, it's possible to make something like this a drop in replacement part, for dead parts. It's very versatile, which might be a bit challenging for some.

If you ask an idiot, about this, then the idiot is likely to say things are impossible. In autism spectrum it is blinkered limited thinking. My Tourette's though, is not. So, I get the best of all these worlds.

Framing, explaining and framing comments as useful to understand the layout and boundaries, and relationships to other things, in design. So, you'll have to bare with it, otherwise a bad product will likely be designed.
-

PIO
Yes, PIO processors. As refered to before, GA's target market was low level glue logic, which would include programmable IO, and parralel processing streams, and low energy computing. That's what it was useful for. A great deal of devices. Except
that integration was rapidly integrating these functions.

My own personal chip design could lead to boards with just the chip and hardly any other components at all, apart from the ports. I had long ago worked on an proposal to isolate the chip from the port and eliminate the need for external conditioning
circuits to reduce damage to the chip. We are not talking about up to that level technology in this design though.
-

Extendable design: Memory storage and higher end ideas. Design stage and great design.

I do extendable design. Meaning, even if this process offer limits the memory to 64KB, the design itself has logical, and physical, constructs to support more for when it is upgraded on another process.

Great design happens at this stage, not the draftsman stage, who fails to see the design expansion and suitability, and may be more obsessed about how it compares to certain other parts in a target market. That might tell you what to do. How to do, or
what can be done. Your interest is in the design that takes you efficiently past your competitors, for wins rather than failures.
-


On Misc suitability, and promoting forth hardware:

Of course Misc is suitable and has use. As I stated before it has a lot of good performance metrics.

Don't get confused with programming the 144 compared to a simple misc chip with large conventional address space. Much simpler. My scheme is just a series of large address spaces to program, with no routing.

What is the use of promoting other hardware, instead of trying to do it better in the reason this forum is set up, Forth!? It's not the Arm or RiscV forum. Things start from somewhere, or restart. The tool level can be raised.


New additions to processor proposal:


However, I would like to add to the design proposal, the reconfiguration aggregation of address spaces of neighbouring pins. At simplest in this, each pin gets a program memory for context, which can be a seperate bid, for parralel operation, however,
most pins could be unused (say only 4 pints out of 40).

Now the pins can divide up the context memory amount themselves. Likely on bit boundaries, but could be more dynamic or both. I'll have to decide latter. But, it's possible, the pins refer based on its addressing being relative around it's context
memory location. So, a pin could be a lifi protocol to off chip and get so much context segments of memory, another a uart, another few video etc. The unused pins inbetween sacrifice their segments to the used pins.

But, if it is a processor per pin, the processor group of the unused pins can run in parallel as well, with programming making the best out of the parralel memory segments for each processor.

What does this look like to the main processor, banks of flat main memory, through dual bus, with each segment having its own bus.

Let's step back and compare to the 144. USB. The 144 runs at lower energy, lower performance, and can use a many core model to stream/pipeline process incoming data by multiple cores in the way through. On this however. One processor could handle a
variety of USB dates, and process the results. Let's say it's an outrageous 20Ghz. That's like 17 144 cores, except with more flexibility and higher performance overall from lack of inter node communications, and you can switch to a regular program to
use the data. Power savings, maybe not, but it's about performance, and handling high data rates.

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