• Re: A Forth MCU for Digilent Cmod S7 users

    From Myron Plichota@21:1/5 to Paul Rubin on Sat Apr 9 06:28:49 2022
    On Friday, April 8, 2022 at 8:52:17 PM UTC-4, Paul Rubin wrote:
    "myronp...@gmail.com" <myronp...@gmail.com> writes:
    The users' manual (forthBoard.pdf) can be downloaded from https://drive.google.com/file/d/1PN6igK_-DLcrx2OWT1H5mXyfrT4OAAq3/view?usp=sharing
    This is nice, is it your design? It reminds me a little of the b16 and GreenArrays cpus, which I guess is unsurprising. Can you run it on
    other FPGA boards? How many LUTs etc. does it require? Are you going
    to make a chip? You can get it fabbed in 130nm for free:

    https://www.fossi-foundation.org/2020/06/30/skywater-pdk

    It would be cool if someone here did that.
    Dear Paul,

    It is my design, but is influenced by Chuck Moore's chips Mup21, F21, and ShBoom.

    Being written in Verilog, the possibility of implementing it on other FPGA platforms is open. But note that the Xilinx Vivado wizards used to generate the Series7 MMCM clock generator and XADC A/D convertor IP cores produced files with prominent
    copyright notices, so they are missing from from my source files offering. FPGA pin number/attribute assignments would also need to be redefined.

    Resource usage:
    LUT 907 of 14600
    FF 934 of 29200
    BRAM 36 of 45
    DSP 2 of 80
    IO 56 of 150
    BUFG 2 of 32
    MMCM 1 of 3
    (no XADC report!)

    Being reliant on many Series7 hardware fabric features, I have no desire to attempt a chip fab, PCB design, SMT board assembly, etc.

    I hope to spark a community of Cmod S7 users that shares their hardware/software adventures like in the pioneering 8-bit days. AFAIK, there have been hundreds (if not thousands) of units purchased by end users like me.

    My next steps:

    1) Acquire 3 more units (ordered, awaiting delivery).
    2) Attempt to burn fresh units using Xilinx Vivado from the existing config files. This would skip rerunning the MMCM and XADC (GUI) wizards and the synthesis and implementation phases.
    3) Document the resulting procedure and revise the users' manual to include it. 4) Continue to provide a zipped snapshot of the design files and forthBoard applications source code examples to anyone who requests it, for free.

    - Myron

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  • From Myron Plichota@21:1/5 to Myron Plichota on Sat Apr 23 12:13:40 2022
    On Saturday, April 9, 2022 at 9:28:51 AM UTC-4, Myron Plichota wrote:
    My next steps:

    1) Acquire 3 more units (ordered, awaiting delivery).
    2) Attempt to burn fresh units using Xilinx Vivado from the existing config files. This would skip rerunning the MMCM and XADC (GUI) wizards and the synthesis and implementation phases.
    3) Document the resulting procedure and revise the users' manual to include it.

    These 3 objectives have been accomplished. Also, the new users' manual includes a link to the zipped design files. Please see:
    https://drive.google.com/file/d/1PN6igK_-DLcrx2OWT1H5mXyfrT4OAAq3/view?usp=sharing

    - Myron

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