On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Syncing forth processor project threads.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.

Syncing forth processor project threads.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

Well, people suggest FPGA'S, which are slow, power hungry and costly.

But, I'm more interested in something closer to a Sea of Gates Array. But, what about PLD and PLA to do a better mini forth processor than FPGA?

These things have a matrix which could be read like a read only memory. So, can a misc processor fit on one, and use the spare array points like a read only storage.


The other interesting thing I've noticed, is that there is no predefined matrix of gate product you can program to route a circuit, but there is a technology used in some FPGAs, which could enable that, by setting up resistance to define a current flow
path. Allowing a programmable sea of gates product, and programmable memory, at higher performance lower energy, than FPGA's maybe. I can't remember the name of the technology. But, you should be able to design such a circuit with memresistor
technology. There are potential ls there.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

Well, people suggest FPGA'S, which are slow, power hungry and costly.

People suggest FPGAs as design platforms for testing and evaluation of designs. But some people can't hear the voices of reason over their own screaming.

But, I'm more interested in something closer to a Sea of Gates Array. But, what about PLD and PLA to do a better mini forth processor than FPGA?

Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly.
There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively
consistently.

The devices that use smaller arrays of logic with more rigid interconnect are typically termed CPLD or SPLD. None of these are very suitable for what you are talking about doing. However, if Hugh were around, he would be quick to tell you the company
he used to work for developed a stack processor on a CPLD with capability of executing multiple instructions per clock. A practical and useful feature when the instructions are so simple. With the large instruction word this is practical. Other
designs which have a tiny opcode size may still have one instruction per word, or may combine multiple instructions into one instruction memory word, such as F18A, b16, etc.

To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.

Check out some low power FPGAs and you may be surprised.

These things have a matrix which could be read like a read only memory. So, can a misc processor fit on one, and use the spare array points like a read only storage.

Which PLD are you refering to? I'm not aware of any such PLD with logic that can be "read like a read only memory". Many PLDs include memory in several forms. Lattice is a company with a number of devices with internal RAM and Flash. Gowin is
another.

The other interesting thing I've noticed, is that there is no predefined matrix of gate product you can program to route a circuit, but there is a technology used in some FPGAs, which could enable that, by setting up resistance to define a current flow

path. Allowing a programmable sea of gates product, and programmable memory, at higher performance lower energy, than FPGA's maybe. I can't remember the name of the technology. But, you should be able to design such a circuit with memresistor technology.
There are potential ls there.

In ASICs, the gate interconnect is formed by a mask layer implementing metal interconnect. Sometimes they provide two layers for more flexibility. All PLDs have defined routing/interconnect and are programmed by either RAM which controls multiplexers
or in some obsolete technologies, fuses, or in others, "anti-fuses".

No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.

--

Rick C. (Lorem Ipsum)

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.

--

Rick C. (Lorem Ipsum)

---+ Get 1,000 miles of free Supercharging
---+ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
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On Wednesday, September 14, 2022 at 2:24:04 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.

Globalspecs

Lorem Ipsum

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 10:34:36 AM UTC+10, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

..

Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.

Sorry, I got that wrong Rick, that's embedded fpga. Common antifuses operate like that, but aren't reprogrammable.

https://en.m.wikipedia.org/wiki/Antifuse

It's says that they are still commonly used, and may offer some speed advantage.

Sorry, still recovering here. Hard to write.


Thanks


Wayne.

--

Rick C..

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

Thank you

Wayne

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

..

Rick, than you for your generous straight forwards explanations and help below.

Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly. There

are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively consistently.

PAL and PLA use different technology architectures. I read one of these offers significance higher speed performance advantages over FPGA.

The devices that use smaller arrays of logic with more rigid interconnect are typically termed CPLD or SPLD. None of these are very suitable for what you are talking about doing. However, if Hugh were around, he would be quick to tell you the company

he used to work for developed a stack processor on a CPLD with capability of executing multiple instructions per

Yes, I think I remember, which was a sort of background thought here.

clock. A practical and useful feature when the instructions are so simple. With the large instruction word this is practical. Other designs which have a tiny opcode size may still have one instruction per word, or may combine multiple instructions into

one instruction memory word, such as F18A, b16, etc.

Rigidity is not a problem, as you implement one design for use or sale, then there's GAL's, which were erasable.

The priority here, is if something on the level of b/p16 f18 like, can be fully implemented, at lower energy and higher speed then FPGA. My target energy envelope is really low for the performance. I'm not having success yet with an FPGA part anywhere
near the target. No body has answered, these are the lowest energy FPGA's with enough gates for a single misc processor at significant performance, or simply, these are the lowest energy parts in the industry, so I can check if they have anything
suitable in the range. I have found one or two low energy manufacturers but the are still 10-100 times too much energy.

I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions, to high
speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

it's a matter of how long a piece of string being: as short as you can get and building implementation feature set up around that, as long as it comes under 1-2mw at at least 1000's of cycles, preferably at least 10 million.

To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.

I'm aware of some of these things. Apparently there are three or four technology architectures now, where regard only sea of gates implementations as true FPGA. None. Ones out of an array of simple programmable logic devices (the cpld version).

Check out some low power FPGAs and you may be surprised.

Couldn't find one yet.

These things have a matrix which could be read like a read only memory. So, can a misc processor fit on one, and use the spare array points like a read only storage.

Which PLD are you refering to? I'm not aware of any such PLD with logic that can be "read like a read only memory". Many PLDs include memory in several forms. Lattice is a company with a number of devices with internal RAM and Flash. Gowin is another.

PAL, PLA. I'm not saying they work the same way as common ROM does, but they use a matric for sum of products calculations, which could be something to explore.

In ASICs, the gate interconnect is formed by a mask layer implementing metal interconnect. Sometimes they provide two layers for more flexibility. All PLDs have defined routing/interconnect and are programmed by either RAM which controls multiplexers

or in some obsolete technologies, fuses, or in others, "anti-fuses".

No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.

Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.

--

Rick C..

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

Thank you

Wayne

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 13, 2022 at 5:45:38 AM UTC-5, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

A partial list is at:
https://github.com/jimbrake/FPGA-parts-with-free-tools
A more extensive list is available.
Lists a mm dimension of smallest part.
Have not included any performance info other than fabrication node.
Generallly, you need to run your design through the vendor's tools to get a power estimate.
https://github.com/jimbrake/cpu_soft_cores gives some indication of performance.
The fastest devices generally use the latest fab node and cost more than slower parts.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 13, 2022 at 7:35:14 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:24:04 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.

Globalspecs

Lorem Ipsum

So did they show you want you wanted?

I think not, because they only cover the products they are paid to advertise. LOL

--

Rick C. (Lorem Ipsum)

--+- Get 1,000 miles of free Supercharging
--+- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 13, 2022 at 9:11:14 PM UTC-4, James Brakefield wrote:

On Tuesday, September 13, 2022 at 5:45:38 AM UTC-5, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

A partial list is at:
https://github.com/jimbrake/FPGA-parts-with-free-tools
A more extensive list is available.
Lists a mm dimension of smallest part.
Have not included any performance info other than fabrication node. Generallly, you need to run your design through the vendor's tools to get a power estimate.
https://github.com/jimbrake/cpu_soft_cores gives some indication of performance.
The fastest devices generally use the latest fab node and cost more than slower parts.

The only low power FPGAs I know of are CoolRunner II from Xilinx which are really CPLDs and can get very pricey, ice40 from Lattice and parts from Gowin.

I don't recall details on the Gowin parts, but the Lattice parts have ~100 uA static current and a low ramp of dynamic power.

The CoolRunner II parts aren't very useful for more complex designs because they are CPLDs and the die size increases rapidly with the number of elements, meaning high $$$.

--

Rick C. (Lorem Ipsum)

-+-- Get 1,000 miles of free Supercharging
-+-- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 13, 2022 at 8:34:36 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

..

Rick, than you for your generous straight forwards explanations and help below.

Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly.

There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively
consistently.

PAL and PLA use different technology architectures. I read one of these offers significance higher speed performance advantages over FPGA.

Perhaps I did not explain it clearly. PAL IS A TRADEMARK, NOT A TECHNOLOGY. NO ONE MAKES PLAs OF ANY VALUE IF AT ALL.

The devices that use smaller arrays of logic with more rigid interconnect are typically termed CPLD or SPLD. None of these are very suitable for what you are talking about doing. However, if Hugh were around, he would be quick to tell you the company

he used to work for developed a stack processor on a CPLD with capability of executing multiple instructions per

Yes, I think I remember, which was a sort of background thought here.

clock. A practical and useful feature when the instructions are so simple. With the large instruction word this is practical. Other designs which have a tiny opcode size may still have one instruction per word, or may combine multiple instructions

into one instruction memory word, such as F18A, b16, etc.

Rigidity is not a problem, as you implement one design for use or sale, then there's GAL's, which were erasable.

Again, GAL is a trademark, not a technology. In general, GAL was a 24 pin 22V10. The part number means it had 22 I/Os, of which 10 could be outputs. Not very high complexity, SPLD.

The priority here, is if something on the level of b/p16 f18 like, can be fully implemented, at lower energy and higher speed then FPGA.

We've had this discussion before. I believe you are putting the cart before the horse by focusing on silicon implementation before the architecture. I would hash out a design in an FPGA to get it working. Then worry about minimizing power consumption
by using an ASIC.

But it doesn't matter. I've explained the reasons before.

My target energy envelope is really low for the performance. I'm not having success yet with an FPGA part anywhere near the target. No body has answered, these are the lowest energy FPGA's with enough gates for a single misc processor at significant

performance, or simply, these are the lowest energy parts in the industry, so I can check if they have anything suitable in the range. I have found one or two low energy manufacturers but the are still 10-100 times too much energy.

I don't recall you ever specifying a target power level.

I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions, to

high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

You say 1 or 2 mW, but you don't give a performance figure. When you say "cycles", what is that? It's not MIPS, it's not MHz. What is it?

it's a matter of how long a piece of string being: as short as you can get and building implementation feature set up around that, as long as it comes under 1-2mw at at least 1000's of cycles, preferably at least 10 million.

To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.

I'm aware of some of these things. Apparently there are three or four technology architectures now, where regard only sea of gates implementations as true FPGA. None. Ones out of an array of simple programmable logic devices (the cpld version).

Check out some low power FPGAs and you may be surprised.

Couldn't find one yet.

Where have you looked?

These things have a matrix which could be read like a read only memory. So, can a misc processor fit on one, and use the spare array points like a read only storage.

Which PLD are you refering to? I'm not aware of any such PLD with logic that can be "read like a read only memory". Many PLDs include memory in several forms. Lattice is a company with a number of devices with internal RAM and Flash. Gowin is another.

PAL, PLA. I'm not saying they work the same way as common ROM does, but they use a matric for sum of products calculations, which could be something to explore.

The "matrix" is a set of interconnects feeding AND gates and connecting the AND gate outputs which are hardwired to the OR gates. There's no memory of any type you can use.

In ASICs, the gate interconnect is formed by a mask layer implementing metal interconnect. Sometimes they provide two layers for more flexibility. All PLDs have defined routing/interconnect and are programmed by either RAM which controls multiplexers

or in some obsolete technologies, fuses, or in others, "anti-fuses".

No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.

Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.

If so, please educate me. No, I don't care, because I'm not designing any ASICs.

--

Rick C. (Lorem Ipsum)

--++ Get 1,000 miles of free Supercharging
--++ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 11:30:33 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 7:35:14 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:24:04 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.

Globalspecs

Lorem Ipsum

So did they show you want you wanted?

I think not, because they only cover the products they are paid to advertise. LOL
--

Rick C. (Lorem Ipsum)
--+- Get 1,000 miles of free Supercharging
--+- Tesla referral code - https://ts.la/richard11209

I saw it last night after, but have to get to sign up. The thing is, that I've know about parts lists and book before. So, there might be that there is an FPGA list. Specialist sites tend to do that, like specific technology information and news sites.
That's an idea I haven't thought about.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 11:50:53 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 8:34:36 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

..

Rick, than you for your generous straight forwards explanations and help below.

Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly.

There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively
consistently.

PAL and PLA use different technology architectures. I read one of these offers significance higher speed performance advantages over FPGA.

Perhaps I did not explain it clearly. PAL IS A TRADEMARK, NOT A TECHNOLOGY. NO ONE MAKES PLAs OF ANY VALUE IF AT ALL.

Now Rick, you don't have to get off key. You did say they hadn't been used for decades before,

Wikipedia describes PAL as fixed OR, programmable AND combination and PLA as programmable OR and AND, which slows it down, and looking around on line it is more expensive to make, but has higher density devices. I also see that PAL is said to be very
common.

https://en.m.wikipedia.org/wiki/Programmable_logic_device

GAL.is a reprgammable version of PAL.

The priority here, is if something on the level of b/p16 f18 like, can be fully implemented, at lower energy and higher speed then FPGA.

We've had this discussion before. I believe you are putting the cart before the horse by focusing on silicon implementation before the architecture. I would hash out a design in an FPGA to get it working. Then worry about minimizing power consumption

by using an ASIC.

We have architectures worked out and tested already. Now, seeking right horse to pull it.

But it doesn't matter. I've explained the reasons before.

My target energy envelope is really low for the performance. I'm not having success yet with an FPGA part anywhere near the target. No body has answered, these are the lowest energy FPGA's with enough gates for a single misc processor at significant

performance, or simply, these are the lowest energy parts in the industry, so I can check if they have anything suitable in the range. I have found one or two low energy manufacturers but the are still 10-100 times too much energy.

I don't recall you ever specifying a target power level.

Why do you think I'm looking for the lowest energy performance parts and then see which applications I have can fit? I asked very simple advice often, but usually never get answers.

I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions, to

high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

You say 1 or 2 mW, but you don't give a performance figure. When you say "cycles", what is that? It's not MIPS, it's not MHz. What is it?

End cycles of course. In misc cycles and instructions are often the same, but in progress htammable logic that is not necessarily possible.

it's a matter of how long a piece of string being: as short as you can get and building implementation feature set up around that, as long as it comes under 1-2mw at at least 1000's of cycles, preferably at least 10 million.

To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.

I'm aware of some of these things. Apparently there are three or four technology architectures now, where regard only sea of gates implementations as true FPGA. None. Ones out of an array of simple programmable logic devices (the cpld version).

Check out some low power FPGAs and you may be surprised.

Couldn't find one yet.

Where have you looked?

With everything that is going on over here, but no real answers, done summaries to get an idea where to look, Wikipedia (ugh) magnetic computing related site, but those FPGA's appears to not have come out, and probably are not the best architecture. Don'
t have time with people siendimg a thousand times on other things than saying these are the things you are looking for over there. Instead of these are the things I want to say, look over here. The confidential commercial nature means I keep it to
myself, and ask relevant questions, not that people not privileged to the commercial process have to question questions and dictate. I could come along and say a lot about people's projects and businesses, and be correct, but that's not my business, I'm
not a potential customer or that they are destroying society, community or life, it's their business. If they ask questions, and I can give relevant beneficial answers, ok. If I have to spend more time on noise than I would wrecking my life trying to
find answers on google. As it is I've had to do both. Where do I send the lawyers. People are asked answers to make life simpler than it could be, by community simpler consciousness (collective knowledge). :)

..

The "matrix" is a set of interconnects feeding AND gates and connecting the AND gate outputs which are hardwired to the OR gates. There's no memory of any type you can use.

Deterministic results from deterministic inputs.

No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.

Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.

If so, please educate me. No, I don't care, because I'm not designing any ASICs.

I posted it before.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 11:55:54 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 9:11:14 PM UTC-4, James Brakefield wrote:

On Tuesday, September 13, 2022 at 5:45:38 AM UTC-5, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

A partial list is at: https://github.com/jimbrake/FPGA-parts-with-free-tools
A more extensive list is available.
Lists a mm dimension of smallest part.
Have not included any performance info other than fabrication node. Generallly, you need to run your design through the vendor's tools to get a power estimate.
https://github.com/jimbrake/cpu_soft_cores gives some indication of performance.
The fastest devices generally use the latest fab node and cost more than slower parts.

The only low power FPGAs I know of are CoolRunner II from Xilinx which are really CPLDs and can get very pricey, ice40 from Lattice and parts from Gowin.

I don't recall details on the Gowin parts, but the Lattice parts have ~100 uA static current and a low ramp of dynamic power.

The CoolRunner II parts aren't very useful for more complex designs because they are CPLDs and the die size increases rapidly with the number of elements, meaning high $$$.
--

Rick C. (Lorem Ipsum)
-+-- Get 1,000 miles of free Supercharging
-+-- Tesla referral code - https://ts.la/richard11209

Thank you Rick.

Quicklogic anti-fuse, and this article talks about 20 µA .

https://www.renesas.com/tw/en/blogs/new-era-programmable-logic https://www.renesas.com/tw/en/products/programmable-mixed-signal-asic-ip-products/forgefpga-low-density-fpgas#document

Though, how could you possibly tell the maximum performance of a full design from the site any current?

Thanks again Rick.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Tuesday, September 13, 2022 at 10:42:55 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 11:30:33 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 7:35:14 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:24:04 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.

Globalspecs

Lorem Ipsum

So did they show you want you wanted?

I think not, because they only cover the products they are paid to advertise. LOL
--

Rick C. (Lorem Ipsum)
--+- Get 1,000 miles of free Supercharging
--+- Tesla referral code - https://ts.la/richard11209

I saw it last night after, but have to get to sign up. The thing is, that I've know about parts lists and book before. So, there might be that there is an FPGA list. Specialist sites tend to do that, like specific technology information and news sites.

That's an idea I haven't thought about.

The trouble is it is very hard to keep current. I tried to create a list of ARM MCUs back when there were maybe a half dozen companies making them. Within six months it had doubled and the number of devices had blossomed even faster. I had to give it
up after another six months, it was just too much work.

FPGAs would be similarly messy as there are a number of Chinese companies with new devices. I've never found any such list. Why can't you just visit the manufacturers and download their product selection guides???

--

Rick C. (Lorem Ipsum)

-+-+ Get 1,000 miles of free Supercharging
-+-+ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 12:40:34 AM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 11:50:53 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 8:34:36 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

..

Rick, than you for your generous straight forwards explanations and help below.

Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly.

There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively
consistently.

PAL and PLA use different technology architectures. I read one of these offers significance higher speed performance advantages over FPGA.

Perhaps I did not explain it clearly. PAL IS A TRADEMARK, NOT A TECHNOLOGY. NO ONE MAKES PLAs OF ANY VALUE IF AT ALL.

Now Rick, you don't have to get off key. You did say they hadn't been used for decades before,

Wikipedia describes PAL as fixed OR, programmable AND combination and PLA as programmable OR and AND, which slows it down, and looking around on line it is more expensive to make, but has higher density devices. I also see that PAL is said to be very

common.

https://en.m.wikipedia.org/wiki/Programmable_logic_device

GAL.is a reprgammable version of PAL.

I guess you still have not figured out that Wikipedia is not a reference. It's just a web site. I've found entries where, when I checked the reference they provided, it said the exact opposite of what the wikipedia article said.

As I said, GAL as used with PLDs is a trademark, not a type of device. NO ONE ELSE THAN LATTICE SEMI WILL SAY THEIR PARTS ARE GALs.

https://trademarks.justia.com/735/64/gal-73564809.html

Many manufacturers have made reprogrammable PLDs over the years. They even make 22V10 devices. Non of them are called GALs other than from Lattice semi.

The priority here, is if something on the level of b/p16 f18 like, can be fully implemented, at lower energy and higher speed then FPGA.

We've had this discussion before. I believe you are putting the cart before the horse by focusing on silicon implementation before the architecture. I would hash out a design in an FPGA to get it working. Then worry about minimizing power consumption

by using an ASIC.

We have architectures worked out and tested already. Now, seeking right horse to pull it.

What architectures are those?

But it doesn't matter. I've explained the reasons before.

My target energy envelope is really low for the performance. I'm not having success yet with an FPGA part anywhere near the target. No body has answered, these are the lowest energy FPGA's with enough gates for a single misc processor at

significant performance, or simply, these are the lowest energy parts in the industry, so I can check if they have anything suitable in the range. I have found one or two low energy manufacturers but the are still 10-100 times too much energy.

I don't recall you ever specifying a target power level.

Why do you think I'm looking for the lowest energy performance parts and then see which applications I have can fit? I asked very simple advice often, but usually never get answers.

You mean you get answers you don't like.

I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions, to

high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

You say 1 or 2 mW, but you don't give a performance figure. When you say "cycles", what is that? It's not MIPS, it's not MHz. What is it?

End cycles of course. In misc cycles and instructions are often the same, but in progress htammable logic that is not necessarily possible.

What is an "end cycle"???

it's a matter of how long a piece of string being: as short as you can get and building implementation feature set up around that, as long as it comes under 1-2mw at at least 1000's of cycles, preferably at least 10 million.

To show you your bias against FPGAs is not based in reality, many CPLDs are actually organized internally as FPGAs. The CPLD nomenclature often is simply an indicator of the size of the device, rather than the architecture.

I'm aware of some of these things. Apparently there are three or four technology architectures now, where regard only sea of gates implementations as true FPGA. None. Ones out of an array of simple programmable logic devices (the cpld version).

Check out some low power FPGAs and you may be surprised.

Couldn't find one yet.

Where have you looked?

With everything that is going on over here, but no real answers, done summaries to get an idea where to look, Wikipedia (ugh) magnetic computing related site, but those FPGA's appears to not have come out, and probably are not the best architecture.

Don't have time with people siendimg a thousand times on other things than saying these are the things you are looking for over there. Instead of these are the things I want to say, look over here. The confidential commercial nature means I keep it to
myself, and ask relevant questions, not that people not privileged to the commercial process have to question questions and dictate. I could come along and say a lot about people's projects and businesses, and be correct, but that's not my business, I'm
not a potential customer or that they are destroying society, community or life, it's their business. If they ask questions, and I can give relevant beneficial answers, ok. If I have to spend more time on noise than I would wrecking my life trying to
find answers on google. As it is I've had to do both. Where do I send the lawyers. People are asked answers to make life simpler than it could be, by community simpler consciousness (collective knowledge). :)

Sorry, not sure what's happening to you, but this is incomprehensible.

The "matrix" is a set of interconnects feeding AND gates and connecting the AND gate outputs which are hardwired to the OR gates. There's no memory of any type you can use.

Deterministic results from deterministic inputs.

No one is using memristor technology. I don't believe anyone has found an actual, practical application for memristors.

Maybe my memory is failing me. I thought memresistor was available on low energy processor node at one of the top foundry companies. Anyway, efpga I think it was, used some sort of technology that I mentioned.

If so, please educate me. No, I don't care, because I'm not designing any ASICs.

I posted it before.

As usual, this turns into a "whatever".

--

Rick C. (Lorem Ipsum)

-++- Get 1,000 miles of free Supercharging
-++- Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 3:28:16 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 10:42:55 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 11:30:33 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 7:35:14 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:24:04 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:45:38 AM UTC-4, Wayne morellini wrote:

On Tuesday, September 13, 2022 at 8:42:18 PM UTC+10, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Sorry for the mispost before.
Syncing forth processor project threads.

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ

I still have not found a site which lists every fpga, or other programmable device, by performance, energy and size.

And you won't. There's no incentive for anyone to do that. Each manufacturer typically has a selection guide that provides basic info on each of their lines and devices. It helps if you know what you want.

Globalspecs

Lorem Ipsum

So did they show you want you wanted?

I think not, because they only cover the products they are paid to advertise. LOL
--

Rick C. (Lorem Ipsum)
--+- Get 1,000 miles of free Supercharging
--+- Tesla referral code - https://ts.la/richard11209

I saw it last night after, but have to get to sign up. The thing is, that I've know about parts lists and book before. So, there might be that there is an FPGA list. Specialist sites tend to do that, like specific technology information and news

sites. That's an idea I haven't thought about.

The trouble is it is very hard to keep current. I tried to create a list of ARM MCUs back when there were maybe a half dozen companies making them. Within six months it had doubled and the number of devices had blossomed even faster. I had to give it

up after another six months, it was just too much work.

FPGAs would be similarly messy as there are a number of Chinese companies with new devices. I've never found any such list. Why can't you just visit the manufacturers and download their product selection guides???
--

Rick C. (Lorem Ipsum)
-+-+ Get 1,000 miles of free Supercharging
-+-+ Tesla referral code - https://ts.la/richard11209

Lol. A list of Arm MCU's is even more messy than a FPGA list. I asked am Arm contact person about this, and not even they knew what was out there, incredibly. It's very important for sales, but Arm is the Intel of complex MCU designs, so they have
most of the sales already.

I was, and continue to be, only well enough to deal with a limited amount at one time, and that means one thing at a time, and have to put everything else aside. I technically needed a carer, and have been trying to get well enough so if I put all my
effort slowly over 60 hours to do 20 hours a week of work, I could afford to hire somebody to look after all my personal chores and responsibilities, as I would no longer be able to keep up. Things were picking up after hardly eating for three weeks
after my father died, and some new Lyme treatment the week before, and went way down since eating again (lots of internal problems that eating affects badly) and the issues happening. So, things are not as well, and all design processors, anymore.

This is costing me 90%, when I was just trying to short cut to where the actual research and work needed to be done, so I could do it. Spending 90% of next to nothing, as a non hardware engineer, just trying to find what bits to learn to work with, is
not on. It's so bad, I've been trying to figure out a simple way to make a circuit alternative at home instead. Quicker to come up with mechanisms for that instead. I'm looking at simple some speedy low energy stuff, but simple lower performance
alternatives that can.br used in 3D printed products, as 3D printed circuits run pretty badly). The sicker things get though, the less you can do, and having to deal with people trying to take advantage of me I've here, is putting too much on.

Anyway, I might still be a good writer when well, but that's most of it. As long as I can write from my own working out. Even reading data sheets, or technical pages, now makes my head spin. But, writer thinker is really good for some things, like
politics (due to a lack of competition, and ability to pace yourself if you concentrate on writing law, and avoid all the fancy power, position ambition, in charge of everything everywhere, games. :)


On a side note:

I'm just been watching a recording of the Oppenheimer lecture, and the guy actually stumble into saying that they had teleportation working, and he has been involved somehow, that he promised not to reveal in the lecture, relating to the discoveries he
was talking about. It's about time. One of my original science fiction jump drive proposals (methodology), is close to what he is telling about, but none of this space folding model people are talking about (the reality is probably more interesting,
but they seem to be ignoring looking at that. Quantum knots (processing technology model, is something relative to that, which seems incredible and unexpected). Some interesting mechanics if you try to jump into another star system, that can smear you
accross space, on one of the other models. Anyway, great lecture, but people are getting too mixed up with holographic universe theory, which is related to mysticism. My hypothesis gets around all the remote intermixed cause and affect paradoxes there
into a potential workable mechanical solution. I mean, you should see the stuff they are saying now. One of the scientists were criticising this fantasy science on some video I watched. Basically the same way I've been feeling. I menton this, because
a never of people here could probably relate to that. The theories are so overly complex and elaborate now, mysticism is creeping in. So, people can slip ever unceasingly incredible subversive stuff in now, and avoid sufficient exploration of real
phenomenon and evidence, slipping in dancing puppets instead.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 3:38:59 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Wednesday, September 14, 2022 at 12:40:34 AM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 11:50:53 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 8:34:36 PM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 2:22:54 AM UTC+10, gnuarm.del...@gmail.com wrote:

On Tuesday, September 13, 2022 at 6:42:18 AM UTC-4, Wayne morellini wrote:

On Monday, September 5, 2022 at 1:32:20 AM UTC+10, Wayne morellini wrote:

On Sunday, September 4, 2022 at 3:40:50 PM UTC+10, Wayne morellini wrote:

On Sunday, January 23, 2022 at 8:51:00 PM UTC+11, Wayne morellini wrote:

..

Rick, than you for your generous straight forwards explanations and help below.

Hmmm... I'll try to explain. PLD is a generic term that includes FPGA, but some people choose to use it for all devices that are not FPGAs. PLA has not been used for decades and no longer exist. It was an early form of PLD that died off quickly.

There are numerous other terms that are either trademarks or simply not used or both. None of these terms are standardized other than FPGA (basic elements larger than a gate or FF) and CPLD (everything that's not an FPGA) which are used relatively
consistently.

PAL and PLA use different technology architectures. I read one of these offers significance higher speed performance advantages over FPGA.

Perhaps I did not explain it clearly. PAL IS A TRADEMARK, NOT A TECHNOLOGY. NO ONE MAKES PLAs OF ANY VALUE IF AT ALL.

Now Rick, you don't have to get off key. You did say they hadn't been used for decades before,

Wikipedia describes PAL as fixed OR, programmable AND combination and PLA as programmable OR and AND, which slows it down, and looking around on line it is more expensive to make, but has higher density devices. I also see that PAL is said to be very

common.

https://en.m.wikipedia.org/wiki/Programmable_logic_device

GAL.is a reprgammable version of PAL.

I guess you still have not figured out that Wikipedia is not a reference. It's just a web site. I've found entries where, when I checked the reference they provided, it said the exact opposite of what the wikipedia article said.

I actually looked up a number of university course and other sites, which said the same. Wikipedia has missed a number of them. These alterations to device technology can lead to a lot of advantages. They should cover those, but Wikipedia.

As I said, GAL as used with PLDs is a trademark, not a type of device. NO ONE ELSE THAN LATTICE SEMI WILL SAY THEIR PARTS ARE GALs.

It's an enhanced PAL, a different technology. Like a modern car is still a car but not a Model T. The problem is that these guys have been using generic terms, even for things that are not really the same type which f thing.
.

I don't recall you ever specifying a target power level.

Why do you think I'm looking for the lowest energy performance parts and then see which applications I have can fit? I asked very simple advice often, but usually never get answers.

You mean you get answers you don't like.

I mean relevant answers that address the question.

I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions,

to high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

You say 1 or 2 mW, but you don't give a performance figure. When you say "cycles", what is that? It's not MIPS, it's not MHz. What is it?

End cycles of course. In misc cycles and instructions are often the same, but in progress htammable logic that is not necessarily possible.

What is an "end cycle"???

It is the clock of the end circuit. A lot of misc fpga designs have a horrible ratio of clock compared to the FPGA. As long as the fpga is sufficient to get a misc design near the target clock. You guys would understand how to estimated that better
then I.

Sorry, not sure what's happening to you, but this is incomprehensible.

I posted it before.

As usual, this turns into a "whatever".

Don't you remember, I covered it in one of the processor threads, to do with on chip memory?


Thanks Rick.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 4:55:19 AM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 3:38:59 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Wednesday, September 14, 2022 at 12:40:34 AM UTC-4, Wayne morellini wrote:
You mean you get answers you don't like.

I mean relevant answers that address the question.

I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of millions,

to high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

You say 1 or 2 mW, but you don't give a performance figure. When you say "cycles", what is that? It's not MIPS, it's not MHz. What is it?

End cycles of course. In misc cycles and instructions are often the same, but in progress htammable logic that is not necessarily possible.

What is an "end cycle"???

It is the clock of the end circuit. A lot of misc fpga designs have a horrible ratio of clock compared to the FPGA. As long as the fpga is sufficient to get a misc design near the target clock. You guys would understand how to estimated that better

then I.

I assume by "end cycle" you are talking about clock cycles? James Brakefield has a fantastic list of soft CPU designs with size and speed data, very comprehensive. You can spend a few days looking at his data. There's no power data, but you can
compare designs bases on size. In the same FPGA, the power will roughly scale with size. If you dig into the tools for building one of the interesting designs, you can get power estimates.

So what is the bottom line? What do you want to do now? Please answer in simple terms. I'm not ready to deal with teleportation yet.

--

Rick C. (Lorem Ipsum)

-+++ Get 1,000 miles of free Supercharging
-+++ Tesla referral code - https://ts.la/richard11209

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)

On Wednesday, September 14, 2022 at 11:18:34 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Wednesday, September 14, 2022 at 4:55:19 AM UTC-4, Wayne morellini wrote:

On Wednesday, September 14, 2022 at 3:38:59 PM UTC+10, gnuarm.del...@gmail.com wrote:

On Wednesday, September 14, 2022 at 12:40:34 AM UTC-4, Wayne morellini wrote:
You mean you get answers you don't like.

I mean relevant answers that address the question.

I have done the figures for one of my lowest energy targets for year. But we are talking about <1 or 2mw. I would like to run something 168 hours on a 50-100mw battery, at either thousands of cycles to 10 million cycles, to hundreds of

millions, to high speed, depending on the edition of the product from least capable up. This is also the sort of range to run parasitic power off of an RCA video plug for filter processing.

You say 1 or 2 mW, but you don't give a performance figure. When you say "cycles", what is that? It's not MIPS, it's not MHz. What is it?

End cycles of course. In misc cycles and instructions are often the same, but in progress htammable logic that is not necessarily possible.

What is an "end cycle"???

It is the clock of the end circuit. A lot of misc fpga designs have a horrible ratio of clock compared to the FPGA. As long as the fpga is sufficient to get a misc design near the target clock. You guys would understand how to estimated that better

then I.

I assume by "end cycle" you are talking about clock cycles? James Brakefield has a fantastic list of soft CPU designs with size and speed data, very comprehensive. You can spend a few days looking at his data. There's no power data, but you can compare

designs bases on size. In the same FPGA, the power will roughly scale with size. If you dig into the tools for building one of the interesting designs, you can get power estimates.

So what is the bottom line? What do you want to do now? Please answer in simple terms. I'm not ready to deal with teleportation yet.
--

Rick C. (Lorem Ipsum)
-+++ Get 1,000 miles of free Supercharging
-+++ Tesla referral code - https://ts.la/richard11209

Well teleportation back in time from transistor to transistor to save time. Hold it what, not that, scrap the old plan.

Not much, got hurdles. Until then, I've slowed down for months. I need to keep myself usefully distracted, so I'll just tick over work on this slowly and lightly off and on until the hurdles are off. Truth be told, I need to see what GA and Stephens
mob might be announcing this year, as it looks like I can find a low powered MCU with memory but not a high speed adc. The misc is the opposite, high speed adc but needs an external memory chip, that will give performance off of it, in the range of
50mhz or less MCU. So, the package is always going need an extra significant chip. But fpga doesn't but uses too much energy, but a lot of things are ok otherwise. So, there is a lot of compromises, and a good part is something useful which doesn't
compromise top much.

The easy stuff is finding the key non generic parts and related technologies, research and develop for them, instead of reading up on 1000 parts. Now I have some names, and a search engine that works, I can feed in all the existing low energy devices or
technologies into a search and find discussions where they talk about them and any better parts, and adjust the search terms till I get something with the minimum performance in the required power envelope for the desired functionality. Price is
affected by quantity, so I'll just have to eyeball what information is out there, and the retail price for low quantity project, to get an idea of who might be supplying cheaper. To get people interested, it needs certain performance, low energy and
price. It's very tight, and this things are very crucial. Things don't get made and designed, if they can't hit the desired metrics in industry, so it's important to work out if you can

The issue with going to every fpga manufacturer, is there are too many of them. Again, don't want to review 100-1000 documents, I can't read much complex stuff anymore. But, just te essential documents, I can read eventually, if I take long enough.

--- SoupGate-Win32 v1.05
* Origin: fsxNet Usenet Gateway (21:1/5)