• Can you use a function to populate a ROM?

    From silverace99@gmail.com@21:1/5 to All on Mon Jan 13 16:03:40 2020
    Hi all,

    I'm building a quarter wave lookup table for sin/cos.

    I know in VHDL, that it is possible in design rtl to write a behavioral function and then reference that function to set the values of a ROM.

    Is that possible in verilog? If so, how might I go about doing it?

    If it's not possible, are there any alternative ways I could use behavioral calculations to initialize my lookup table without pre-building with .hex files or scripts?

    The idea is to make the whole thing parameterizable.

    Thanks,
    Stephen

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  • From Kevin Neilson@21:1/5 to silve...@gmail.com on Fri Jan 17 12:46:35 2020
    On Monday, January 13, 2020 at 5:03:42 PM UTC-7, silve...@gmail.com wrote:
    Hi all,

    I'm building a quarter wave lookup table for sin/cos.

    I know in VHDL, that it is possible in design rtl to write a behavioral function and then reference that function to set the values of a ROM.

    Is that possible in verilog? If so, how might I go about doing it?

    If it's not possible, are there any alternative ways I could use behavioral calculations to initialize my lookup table without pre-building with .hex files or scripts?

    The idea is to make the whole thing parameterizable.

    Thanks,
    Stephen

    That is possible, but many synthesizers won't do this well or at all. It's probably easier to use a different program to generate a ROM in a case statement or to put data in a file which you can read in using $readmemh. I have used a function to
    populate a wire or parameter which acts as a ROM. It will probably have to be flattened into a vector:

    parameter X = 7; // Some function input
    wire [128*8-1:0] tbl = gen_tbl(X); // 128-byte table flattened into vector

    ...

    function [128*8-1:0] gen_tbl
    (input integer X); // some parameter
    integer ii; // loop variable
    begin
    for (ii=0; ii<128-1; ii=ii+1)
    gen_tbl[ii*8+:8]=$some_function(ii);
    end
    endfunction

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  • From Remigiusz Kaletka@21:1/5 to All on Thu Oct 15 02:26:10 2020
    piątek, 17 stycznia 2020 o 21:46:37 UTC+1 Kevin Neilson napisał(a):
    On Monday, January 13, 2020 at 5:03:42 PM UTC-7, silve...@gmail.com wrote:
    Hi all,

    I'm building a quarter wave lookup table for sin/cos.

    I know in VHDL, that it is possible in design rtl to write a behavioral function and then reference that function to set the values of a ROM.

    Is that possible in verilog? If so, how might I go about doing it?

    If it's not possible, are there any alternative ways I could use behavioral calculations to initialize my lookup table without pre-building with .hex files or scripts?

    The idea is to make the whole thing parameterizable.

    Thanks,
    Stephen
    That is possible, but many synthesizers won't do this well or at all. It's probably easier to use a different program to generate a ROM in a case statement or to put data in a file which you can read in using $readmemh. I have used a function to
    populate a wire or parameter which acts as a ROM. It will probably have to be flattened into a vector:

    parameter X = 7; // Some function input
    wire [128*8-1:0] tbl = gen_tbl(X); // 128-byte table flattened into vector

    ...

    function [128*8-1:0] gen_tbl
    (input integer X); // some parameter
    integer ii; // loop variable
    begin
    for (ii=0; ii<128-1; ii=ii+1)
    gen_tbl[ii*8+:8]=$some_function(ii);
    end
    endfunction

    BTW, do you have any simple method to access this table byte-wise, in such manner that i.e. calling get(6, tbl), will get you tbl[47:40], but without need to use function?

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  • From Gabor@21:1/5 to silverace99@gmail.com on Tue Oct 20 09:30:52 2020
    On Monday, 1/13/2020 7:03 PM, silverace99@gmail.com wrote:
    Hi all,

    I'm building a quarter wave lookup table for sin/cos.

    I know in VHDL, that it is possible in design rtl to write a behavioral function and then reference that function to set the values of a ROM.

    Is that possible in verilog? If so, how might I go about doing it?

    If it's not possible, are there any alternative ways I could use behavioral calculations to initialize my lookup table without pre-building with .hex files or scripts?

    The idea is to make the whole thing parameterizable.

    Thanks,
    Stephen


    I know Xilinx synthesis allows this. You just need to use the function
    in an initial block. Typically you'd use a for loop in the initial
    block to populate the ROM using the function.

    --
    Gabor

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