• Module Instantiation: How does Verilog identify an instantiated module?

    From Otto Hunt@21:1/5 to All on Wed Dec 11 18:57:06 2019
    Examples of module instantiation are given here:

    http://web.engr.oregonstate.edu/~traylor/ece474/beamer_lectures/modules.pdf

    and here:

    https://www.chipverify.com/verilog/verilog-module-instantiations

    My question is: when instantiating a module under the top level module, none of the examples above used the keyword "module". Instead, the name of an external module is stated, followed by a new module name. Is it necessary that the external module be in
    the same file as the top level module? If not, how does this work?

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  • From Gabor@21:1/5 to Otto Hunt on Thu Dec 12 22:10:44 2019
    On Wednesday, 12/11/2019 9:57 PM, Otto Hunt wrote:
    Examples of module instantiation are given here:

    http://web.engr.oregonstate.edu/~traylor/ece474/beamer_lectures/modules.pdf

    and here:

    https://www.chipverify.com/verilog/verilog-module-instantiations

    My question is: when instantiating a module under the top level module, none of the examples above used the keyword "module". Instead, the name of an external module is stated, followed by a new module name. Is it necessary that the external module be
    in the same file as the top level module? If not, how does this work?


    The instantiated module does not need to be in the same file as the code
    that instantiates it. In fact a very common practice is to place each
    module in its own file, typically module_name.v

    That being said, the tools that are compiling your code need to know
    where to find the module. Most GUI tools allow the concept of a project
    which keeps track of files to be included when compiling. Another way
    is to explicitly list the files to be compiled when running the
    compilation, which might be more common in command-line tools than in a
    GUI project. So the answer to your second question is essentially it
    depends on the tools you're using.

    --
    Gabor

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  • From Otto Hunt@21:1/5 to Gabor on Thu Dec 12 19:30:04 2019
    On Thursday, December 12, 2019 at 7:10:57 PM UTC-8, Gabor wrote:
    On Wednesday, 12/11/2019 9:57 PM, Otto Hunt wrote:
    Examples of module instantiation are given here:

    http://web.engr.oregonstate.edu/~traylor/ece474/beamer_lectures/modules.pdf

    and here:

    https://www.chipverify.com/verilog/verilog-module-instantiations

    My question is: when instantiating a module under the top level module, none of the examples above used the keyword "module". Instead, the name of an external module is stated, followed by a new module name. Is it necessary that the external module
    be in the same file as the top level module? If not, how does this work?


    The instantiated module does not need to be in the same file as the code
    that instantiates it. In fact a very common practice is to place each
    module in its own file, typically module_name.v

    That being said, the tools that are compiling your code need to know
    where to find the module. Most GUI tools allow the concept of a project which keeps track of files to be included when compiling. Another way
    is to explicitly list the files to be compiled when running the
    compilation, which might be more common in command-line tools than in a
    GUI project. So the answer to your second question is essentially it
    depends on the tools you're using.

    --
    Gabor

    Thanks, Gabor, that clears things up.

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