• HDLC Clocking

    From digitalguy33@gmail.com@21:1/5 to All on Sat Aug 17 08:01:41 2019
    Is there a standard for the clocking in HDLC? I have seen examples where data is transmitted on rising edge of TXCLK and sampled on falling edge ... as well as examples where data is transmitted on falling edge of TXCLK and sampled on rising edge.

    I can't seem to find any mention in the HDLC standard.

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  • From Allan Herriman@21:1/5 to All on Sun Aug 18 00:53:40 2019
    On Sat, 17 Aug 2019 08:01:41 -0700, digitalguy33 wrote:

    Is there a standard for the clocking in HDLC? I have seen examples
    where data is transmitted on rising edge of TXCLK and sampled on falling
    edge ... as well as examples where data is transmitted on falling edge
    of TXCLK and sampled on rising edge.

    I can't seem to find any mention in the HDLC standard.

    All the HDLC standards I've read just talk about a stream of bits (or
    bytes, for the byte-oriented versions that work slightly differently).
    They don't mention clocking at all.

    Some of the HDLC controllers that I've designed pulled their bits from a timeslot in a PDH or SDH frame.

    Allan

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