• Up/Down Binary Counter with Dynamic Count-to Flag

    From buse.victorstefan@decathlon.com@21:1/5 to All on Sun Apr 21 15:33:31 2019
    hello, i need to solve this problem in verilog:Up/Down Binary Counter with Dynamic Count-to Flag

    this is start cod:


    module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn,
    inst_load, inst_cen, inst_clk, inst_reset, count_inst, tercnt_inst );
    parameter width = 8;
    input [width-1 : 0] inst_data;
    input [width-1 : 0] inst_count_to;
    input inst_up_dn;
    input inst_load;
    input inst_cen;
    input inst_clk;
    input inst_reset;
    output [width-1 : 0] count_inst;
    output tercnt_inst;
    // Instance of DW03_bictr_dcnto
    DW03_bictr_dcnto #(width)
    U1 ( .data(inst_data), .count_to(inst_count_to), .up_dn(inst_up_dn), .load(inst_load), .cen(inst_cen), .clk(inst_clk),
    .reset(inst_reset), .count(count_inst), .tercnt(tercnt_inst) );
    endmodule


    i already have: test.v

    module DW03_bictr_dcnto_inst( inst_data, inst_count_to, inst_up_dn,
    inst_load, inst_cen, inst_clk, inst_reset, count_inst, tercnt_inst );
    parameter width = 8;
    input [width-1 : 0] inst_data;
    input [width-1 : 0] inst_count_to;
    input inst_up_dn;
    input inst_load;
    input inst_cen;
    input inst_clk;
    input inst_reset;
    output [width-1 : 0] count_inst;
    output tercnt_inst;
    // Instance of DW03_bictr_dcnto
    always @(posedge inst_clk or negedge inst_reset)
    if (~inst_reset) begin
    count_inst<={width{4'b0000}};
    end
    else begin
    if(~inst_load) begin
    count_inst<=inst_data;
    end
    else begin
    if (inst_cen) begin
    if (inst_up_dn) begin
    count_inst<=count_inst+1;
    if (count_inst==inst_count_to)
    tercnt_inst<=1;
    end
    else begin
    count_inst<=count_inst-1;
    if (count_inst==inst_count_to)
    tercnt_inst<=1;
    end
    end
    end
    end
    always @(count_inst or inst_up_dn)
    if (&count_inst && inst_up_dn)
    tercnt_inst <= 1;
    else
    if (~|count_inst && !inst_up_dn)
    tercnt_inst <= 1;
    else
    tercnt_inst <= 0;

    DW03_bictr_dcnto #(width)
    U1 ( .data(inst_data), .count_to(inst_count_to), .inst_up_dn(inst_up_dn), .load(inst_load), .cen(inst_cen), .clk(inst_clk),
    .reset(inst_reset), .count(count_inst), .tercnt(tercnt_inst) );
    endmodule


    I need the test_branch.V and DUT.V
    Thanks a lot!

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  • From robeeert138@gmail.com@21:1/5 to All on Wed Mar 25 13:00:35 2020
    joi, 15 mai 2008, 14:40:44 UTC+3, SweetMusic a scris:
    Hi,
    I need to simulate this thing in Verilog vega.unitbv.ro/~nicula/asd/ hdl_lab/tema_pdf/DW03_bictr_dcnto.pdf :)

    And here is my counter.v file

    module counter(data, up_dn, cen, load, clk, count, tercnt, reset,
    count_to);
    parameter width=4;


    input[width-1:0] data;
    input[width-1:0] count_to;
    input up_dn, cen, load, clk, reset;


    output [width-1:0] count;
    reg [width-1:0] count;
    output tercnt;
    reg tercnt;



    always @(posedge clk or negedge reset)
    if (~reset) begin
    count<={width{4'b0000}};
    end
    else begin
    if(~load) begin
    count<=data;
    end
    else begin
    if (cen) begin
    if (up_dn) begin
    count<=count
    +1;
    if (count==count_to)
    tercnt<=1;
    end
    else begin

    count<=count-1;
    if (count==count_to)
    tercnt<=1;
    end
    end
    end
    end

    always @(count or up_dn)

    if (&count && up_dn)
    tercnt <= 1;

    else
    if (~|count && !up_dn)
    tercnt <= 1;

    else
    tercnt <= 0;


    endmodule


    ****************************************************************************************************************

    The problem is that when the count reaches to the count_to value(witch
    is an input signal), tercn signal(terminate counting) dosent goes to
    "1"

    What do i do wrong?
    thank you

    Salut! Mai ai cumva aceasta tema salvata prin PC? :)

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  • From Beniamin Antal-Vaida@21:1/5 to All on Mon Mar 28 08:54:32 2022
    Pe miercuri, 25 martie 2020, la 22:00:39 UTC+2, robee...@gmail.com a scris:
    joi, 15 mai 2008, 14:40:44 UTC+3, SweetMusic a scris:
    Hi,
    I need to simulate this thing in Verilog vega.unitbv.ro/~nicula/asd/ hdl_lab/tema_pdf/DW03_bictr_dcnto.pdf :)

    And here is my counter.v file

    module counter(data, up_dn, cen, load, clk, count, tercnt, reset, count_to);
    parameter width=4;


    input[width-1:0] data;
    input[width-1:0] count_to;
    input up_dn, cen, load, clk, reset;


    output [width-1:0] count;
    reg [width-1:0] count;
    output tercnt;
    reg tercnt;



    always @(posedge clk or negedge reset)
    if (~reset) begin
    count<={width{4'b0000}};
    end
    else begin
    if(~load) begin
    count<=data;
    end
    else begin
    if (cen) begin
    if (up_dn) begin
    count<=count
    +1;
    if (count==count_to)
    tercnt<=1;
    end
    else begin

    count<=count-1;
    if (count==count_to)
    tercnt<=1;
    end
    end
    end
    end

    always @(count or up_dn)

    if (&count && up_dn)
    tercnt <= 1;

    else
    if (~|count && !up_dn)
    tercnt <= 1;

    else
    tercnt <= 0;


    endmodule


    ****************************************************************************************************************

    The problem is that when the count reaches to the count_to value(witch
    is an input signal), tercn signal(terminate counting) dosent goes to
    "1"

    What do i do wrong?
    thank you
    Salut! Mai ai cumva aceasta tema salvata prin PC? :)

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  • From Beniamin Antal-Vaida@21:1/5 to All on Mon Mar 28 08:58:19 2022
    Pe miercuri, 25 martie 2020, la 22:00:39 UTC+2, robee...@gmail.com a scris:
    joi, 15 mai 2008, 14:40:44 UTC+3, SweetMusic a scris:
    Hi,
    I need to simulate this thing in Verilog vega.unitbv.ro/~nicula/asd/ hdl_lab/tema_pdf/DW03_bictr_dcnto.pdf :)

    And here is my counter.v file

    module counter(data, up_dn, cen, load, clk, count, tercnt, reset, count_to);
    parameter width=4;


    input[width-1:0] data;
    input[width-1:0] count_to;
    input up_dn, cen, load, clk, reset;


    output [width-1:0] count;
    reg [width-1:0] count;
    output tercnt;
    reg tercnt;



    always @(posedge clk or negedge reset)
    if (~reset) begin
    count<={width{4'b0000}};
    end
    else begin
    if(~load) begin
    count<=data;
    end
    else begin
    if (cen) begin
    if (up_dn) begin
    count<=count
    +1;
    if (count==count_to)
    tercnt<=1;
    end
    else begin

    count<=count-1;
    if (count==count_to)
    tercnt<=1;
    end
    end
    end
    end

    always @(count or up_dn)

    if (&count && up_dn)
    tercnt <= 1;

    else
    if (~|count && !up_dn)
    tercnt <= 1;

    else
    tercnt <= 0;


    endmodule


    ****************************************************************************************************************

    The problem is that when the count reaches to the count_to value(witch
    is an input signal), tercn signal(terminate counting) dosent goes to
    "1"

    What do i do wrong?
    thank you
    Salut! Mai ai cumva aceasta tema salvata prin PC? :)


    Salut , ai facut cumva rost de aceasta tema ?

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