From nikhil777nix@gmail.com@21:1/5 to All on Fri Sep 7 01:51:55 2018
Hello,
I have a few packages that I have written like this:
package A;
--
--
endpackage
package B;
import A::*
---
--
endpackage
package C;
import A::*;
import B::*;
endpackage
In the file using package C, the error I am getting is as follows:
Error (10864): SystemVerilog error at C.sv(26): TMP was imported from multiple packages with ::* - none of the imported declarations are visible.
Is this problem because I am importing A::* in both package A and package C? Any help to rsolve this is greatly appreciated.
From Y.V.V.Nagendra@21:1/5 to All on Sat Sep 8 00:05:08 2018
First of all: importing a package into a file means.... You are giving access of fields in the package to the file.
Assuming a variable "tmp" in package A, according to code u've written, the file in which u've written package C is getting access of variable "tmp" twice (once through importing package A and second time by importing package B), which is illegal