• UVM on FPGA

    From kadarshankumar@gmail.com@21:1/5 to All on Sun Jan 6 22:50:20 2019
    Hi all,
    Can UVM code dumped on FPGA .Does UVM TB can synthesized.

    Regards
    DARSHAN

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  • From Kevin Neilson@21:1/5 to kadarsh...@gmail.com on Tue Jan 8 02:26:25 2019
    On Sunday, January 6, 2019 at 11:50:22 PM UTC-7, kadarsh...@gmail.com wrote:
    Hi all,
    Can UVM code dumped on FPGA .Does UVM TB can synthesized.

    Regards
    DARSHAN

    No.

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  • From HT-Lab@21:1/5 to Kevin Neilson on Tue Jan 8 20:24:26 2019
    On 08/01/2019 10:26, Kevin Neilson wrote:
    On Sunday, January 6, 2019 at 11:50:22 PM UTC-7, kadarsh...@gmail.com wrote:
    Hi all,
    Can UVM code dumped on FPGA .Does UVM TB can synthesized.

    Regards
    DARSHAN

    No.

    Moving your testbench onto hardware is not new and is being used by many companies. You will find that high-end synthesis tools, P&R vendors and
    some custom tools will give you access to synthesizable modules like bus checkers, protocol checkers, random number generators, traffic analysers
    etc which can be used to build an on-chip testbench. In addition PSL/SVA
    and some OVL monitor can be synthesised as well.

    So Kevin is right that UVM cannot be synthesised out of the box but if simulation is too slow and you can't afford an emulator then moving your testbench on-chip is not a bad idea. In addition most simulator are
    faster on synthesizable code so trying to keep your testbench
    synthesizable might improve simulation speed.

    Good luck,
    Hans.
    www.ht-lab.com

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