• Java or Python parser for System Verilog testbench ?

    From Bobby@21:1/5 to All on Sat Sep 1 15:56:24 2018
    I have a very simple System Verilog (SV) decoder as my DUT (device under test). I would like to generate a test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my
    grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

    Questions:

    (1) Considering my end goal, i.e. to generate SV TB,
    a java parser would be better or python ?

    (2) Given the generated python parser from grammar,
    will any kind of python scripting will help me to generate
    the testbench in SV for my DUT ? My confusion at this point
    is that most of all the literature I am reading
    suggests linguistic techniques. Any non-linguistic technique ?



    (3) Any technique to go on further with java parser ?


    Looking forward for suggestions :-)




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  • From Johann Klammer@21:1/5 to Bobby on Sun Sep 2 17:01:52 2018
    On 09/02/2018 12:56 AM, Bobby wrote:

    I have a very simple System Verilog (SV) decoder as my DUT (device under test). I would like to generate a test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my
    grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

    Questions:

    (1) Considering my end goal, i.e. to generate SV TB,
    a java parser would be better or python ?

    (2) Given the generated python parser from grammar,
    will any kind of python scripting will help me to generate
    the testbench in SV for my DUT ? My confusion at this point
    is that most of all the literature I am reading
    suggests linguistic techniques. Any non-linguistic technique ?



    (3) Any technique to go on further with java parser ?


    Looking forward for suggestions :-)






    I believe pyparsing comes with a verilog parser in the examples directory.(verilogParse.py)

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  • From Petter Gustad@21:1/5 to Bobby on Wed Sep 5 21:50:29 2018
    Bobby <italienisch1987@gmail.com> writes:

    I have a very simple System Verilog (SV) decoder as my DUT (device under test). I would like to generate a test bench for this DUT based on the 'requirements'. I wrote its (DUT) functions in simple text as 'requirements' . Now through the help of my
    grammar, I can give the requirement input to my grammar to generate a parser in Java or Python.

    Questions:

    (1) Considering my end goal, i.e. to generate SV TB,
    a java parser would be better or python ?

    ANTLR4 is a pretty good parser generator. It supports both Java and
    Python. I would say the parser generator and grammar specification
    support is more important than your implementation language. Even though
    the internals of ANTLR is written in Java.

    //Petter


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