• Verilog template for template engine

    From Bobby@21:1/5 to All on Sun Oct 28 17:46:58 2018
    Hi

    I'm using a template engine to generate a System Verilog file from my data model (data model is in Java). This generated SV file has to be used in a database.
    Therefore, I'm trying to make a generic template with placeholders in it for a simple Verilog'Watchdog timer' testbench (my DUT is Watchdog). I will map the given requirements of Watchdog in these placeholders. Someone recommended me that as my SV
    generated file has to be used in a database, I have to write template with 'header' and 'body' parts in it. But this is where I'm struggling. How to make such a generic template with 'header' and 'body' parts? I have the SV global code templates for '
    module', 'module with ports' 'always..if', 'if..else' 'begin' 'assert'. etc already in my template folder.
    Can someone please refer me a Watchdog template example where I can see the format?
    Or may be someone can share an example here? Any help would be appreciable...

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